JPH07105148B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor (hereinafter
The present invention relates to a non-volatile semiconductor memory device whose main constituent element is an IGFET), and particularly to an electrically writable / erasable semiconductor memory device (hereinafter referred to as an EEPROM).

[Prior Art] An example of a conventional EEPROM is shown in a block diagram of FIG. Here, the X decoder circuit and the Y decoder circuit that select the byte designated by the address are omitted. In the figure, Q ₁₂
Is an N-channel enhancement type IGFET (hereinafter referred to as NE-IGFET) for selecting the Y address of the memory cells M ₁₁ , ... M _n1 , and the memory cells M _{11 to} M _n1 are NE-IGFET selection cells M _S11 . , A storage cell M _M11 having a floating gate and storing information of “0” or “1”. Q ₁₃ is the NE-IGFET for selecting the Y address of the byte, M _B11 ... M _Bn1 is the NE-IGFET for selecting the X ₁ ... _n address of the byte, and Q ₁₁ is the memory cell selected by the address. It is a NE-IGFET for writing that is conductive in some cases.

Hereinafter, for simplification of description, the thresholds of NE-IGFETs are all set to the same V _TN , and the storage cell is defined as a conductive state defined as “0” and a non-defined as “1” according to the stored information. It is assumed that there is continuity.

As shown in FIG. 7, the EEPROM requiring a high read speed has a voltage of the output SA of the sense amplifier circuit 12 and an output RA of the reference voltage generation circuit 15 which change depending on the information stored in the memory cell M _M11. Is compared with the voltage V _REF by the comparison detector 16 to detect and amplify whether the selected storage cell is in the conductive state or the non-conductive state, and the result is output from the output buffer 17.

This EEPROM has a high voltage generation circuit (charge pump circuit) 11 which internally generates a high voltage V _PP necessary for writing / erasing from a power supply voltage V _CC, and the voltage of this output CP is
V _PP in write and erase modes, V _PP in read mode
_CC, or is set to a value close to V _CC. In the control gate voltage control circuit 13, the voltage of the output CGS is set to "0" in the write mode, to V _PP in the erase mode, and to the read voltage V _R in the read mode. The write control circuit 10 sets the output WC to the voltage V _PP when writing the memory cell in the write mode, and sets the output WC to the voltage “0” when not writing, in the erase mode and in the read mode. To do. The source voltage control circuit 14 controls the output VS voltage to V _{CC in the} write mode.
In the erase mode and the read mode, it is set to "0".

Next, a case where the memory cell M _M11 is written and the memory cell M _Mn1 is erased will be described.

First, when programming the memory cell M _M11 , the address lines Y ₁ , X
_{Set 1} to high voltage V _PP , output WC to V _PP , output CGS to “0”
, V _S1 is set to V _CC . Therefore, the transistor Q ₁₁ ,
Since Q ₁₂ , M _S11 , Q ₁₃ , and M _B11 are conducting, and (V _PP −V _TN ) is applied to the drain of the memory cell M _M11 and “0” is applied to the gate, it is injected into the floating gate. Electrons are released to the drain. At this time, the threshold value of the memory cell M _M11 shifts from the initial state to a negative value. Therefore, when the read voltage V _R is applied to the gate electrode in the read mode, the memory cell M _M11 becomes conductive and the current I _ON flows. .

When erasing the memory cell M _Mn1 , set the address lines Y ₁ and X _n to V
_{As PP} , the output WC of the write control circuit 10 is set to 0, the output CGS of the control gate voltage control circuit 13 is set to V _PP , and V _S1 is set to 0. Thus, the transistors Q _13, M _Bn1, the memory cell M _Mn1 is turned on, the drain of the memory cell M _Mn1 0 is,
V _PP is applied to the gate, and electrons are injected from the drain to the floating gate. At this time, since the threshold value of the memory cell M _Mn1 is shifted from the initial state to the positive state, the memory cell M _Mn1 becomes non-conductive even when the read voltage V _R is applied to the gate electrode in the read mode.

FIG. 2 shows the threshold value V _TM (W) of the written memory cell with respect to the write / erase pulse time when the charge pump circuit 11 is designed so that V _PP = 19V, 20V, 21V. , And shows how the threshold V _TM (E) of the erased storage cell changes for each V _PP . The higher the voltage V _PP , the longer the write pulse time and the erase pulse time, the greater the change in the threshold value with respect to the initial value.

FIG. 8 is a block diagram of an example of the sense amplifier circuit 12 of FIG. Q ₈ is a P-channel enhancement type IGFET (hereinafter referred to as PE-IGFET) whose source is connected to the power supply V _CC and whose gate and drain are commonly connected as output SA. Q ₉ is the drain to output SA and the source to the other. Inverting amplifier, output SB
To the input of the I _2, NE connected gate to the input of the inverting amplifier I ₂
-It is IGFET.

First, the operation of the sense amplifier circuit 12 when the written memory cell M _M11 is selected will be described.

The current I _on flows through the memory cell M _M11 , the voltage of the output SB decreases, the output voltage of the inverting amplifier I ₂ increases, and the transistor Q ₉
Conducts. The voltage of the output SA drops, and the voltage of the output SA balances when it matches the current I _on flowing in the transistor Q ₈ . Output SA as more current flows to memory cell M _M11
Voltage becomes smaller.

The output SA of the sense amplifier circuit 12 when the written memory cell is selected is set to the voltage V _on .

Next, the operation of the sense amplifier circuit when the erased memory cell M _Mn1 is selected will be described. At this time, since the cell M _Mn1 becomes non-conductive, the voltage of the output SB is charged and increases, and the gate voltage of the transistor Q ₉ decreases and becomes non-conductive. Therefore, the voltage of the output SA is balanced at (V _CC −V _TP ) where the threshold of the PE-IGFET is V _TP . The output SA of the sense amplifier circuit 12 when the erased memory cell is selected is set to the voltage V _off
And

FIG. 9 is a block diagram showing an example of the reference voltage generating circuit 15 of FIG. Transistor Q ₄ has source source V
PE with output RA by commonly connecting the gate and drain to _CC
-It has the same (gate width) / (gate length) as transistor Q _{9 in} IGFET. The transistor Q ₅ has a drain output RA,
The source is connected to the input of the inverting amplifier I ₁ as the output RB, the gate is connected to the output of the inverting amplifier I ₁ , and the NE-IGFET having the same (gate width) / (gate length) as Q ₉ and the transistor Q ₇ is the drain. N having the same (gate width) / (gate length) as the transistor Q ₁₂ with the gate connected to the power supply V _CC at the output RB
The drain of E-IGFET, M ₄ is the source of transistor Q ₇ ,
The gate is connected to the power supply V _CC , and the transistor M _S11 , ..., M
NE-IGFE with _Sn1 same as the (gate width) / (gate length)
T and M ₅ are NE-IGFETs (hereinafter referred to as reference IGFETs) whose drains are connected to the sources of the FETs M ₄ , their sources are connected to the ground, and their gates are connected to the reference read control line CGR.

This conventional reference voltage generation circuit 15 controls the voltage of (gate width) / (gate length) / CGR of the IGFET M ₅ to output the output voltage V _REF when the written memory cell is selected. an output voltage V _on the sense amplifier circuit 12, which functions by setting between the output voltage V _off of the sense amplifier circuit 12 when the memory cell that has been erased is selected.

Next, a method for setting the output voltage (RA) V _REF of the reference voltage generation circuit 15 will be described.

Figure 10 shows the write voltage determined by the charge pump circuit 11.
V _PP , the current-voltage characteristic I _ce of the memory cell written by the write pulse width t _PW , the current-voltage characteristic I _R3 of the current I _REF flowing in the reference IGFET M ₅ of the reference voltage generation circuit 15, and
In the sense amplifier circuit 12, it is composed of Q ₈ , Q ₉ , I ₂ , Q ₁₂ , M _S11 , and in the reference voltage generation circuit 15, Q ₄ , Q ₅ , I ₁ , Q ₇ , M ₄
The load characteristics L ₁ , L ₂ , L ₃ (hereinafter referred to as load curve) of the load circuit configured by are shown. FETQ ₈ and Q ₄ , Q ₉ and Q ₅ ,, Q ₁₂
And Q ₇ , and M _S11 and M ₄ have the same (gate width) / (gate length), and I ₂ has the same input / output characteristics as I ₁ , so that the sense amplifier circuit 12 and the reference voltage generation circuit 15 Shows the same characteristics as the load curve of.

L ₁ in the case of the logic threshold design value of I _S1, I _R1, the logic threshold value of L ₂ and L ₃ I _S1, I _R1 is the threshold value of variation of the process conditions change or the like It shows a load curve when the design value is shifted to the negative and the positive.

_Each of the memory cells M _{M11 to} M _Mn1 has a thin oxide film of about 100 Å called a tunnel gate through which electrons pass in the drain, and the gate and the drain are strongly capacitively coupled.
As shown by I _ce in FIG. 10, the drain current increases as the drain voltage increases, and the saturation region shown in the current-voltage characteristic I _R3 of the IGFET does not exist.

FIG. 11 shows the output voltage V _off and V _{ON of} the sense amplifier circuit 12 and the output voltage V of the reference voltage generation circuit 15 with respect to the current I _ON flowing in the written memory cell and the current I _REF flowing in the reference IGFET. FIG. 9 is a characteristic diagram showing how the value of _REF changes. The load curve shown by L _O is mainly determined by (gate width) / (gate length) of FET Q ₈ and Q ₄ , and
12. The reference voltage generating circuit 15 has the same characteristics.

In FIG. 10, the current value I _ON (1) at the intersection P ₁ between the written memory cell current-voltage characteristic I _ce and the load curve L ₁ of the sense amplifier circuit and the reference voltage generation circuit 15 is the design value. In Fig. 11, the current value actually flowing in the memory cell is shown. From Fig. 11, the output of the sense amplifier circuit 12 corresponding to I _ON (1) is V
You can see that it is _on (1). The current value I _REF (D) flowing through the reference IGFET M ₅ of the reference voltage generation circuit 15 is V _REF
It is designed so that = {V _off −V _on (1)} / 2. The current-voltage characteristic I _R3 of this reference IGFET M ₅ and the load curve L ₁
The crossing point Q ₁ is the reference IG of the reference voltage generation circuit 15.
It is the equilibrium point in the design value of the drain of FETM ₅ .

Next, a case where the load curve L _{1 of} the reference voltage generation circuit 15 and the sense amplifier circuit 12 changes to L ₂ will be described. In this case, the intersection P ₁ of the load curve and I _ce changes to P ₂ and the current I _on (1) flowing in the memory cell changes to I _on (2), but the reference IGFET M ₅ operates in the saturation region. Because
The current flowing through this reference IGFET remains I _REF (D). Therefore, the output voltage V _on of the sense amplifier circuit
(1) will change to V _on (2). At this time, the difference between the output voltage of the sense amplifier circuit 12 and the output voltage of the reference voltage generating circuit 15 (V _REF (D) -V _on (2)) is the design value (V _REF (D) -V). Since it is smaller than _on (1)), it becomes difficult to detect by the comparison detector 16 in the next stage.

Next, the load curves of the sense amplifier circuit and the reference voltage generation circuit
A case where L ₁ changes to L ₃ will be described. In this case, the intersection P ₁ of the load curve and I _ce changes to P ₃ and the current I _on (1) flowing in the memory cell changes to I _on (3), but the current flowing in the reference IGFET M ₅ changes to I _{Remains REF} (D),
The output voltage V _on (1) of the sense amplifier circuit 12 changes to V _on (3).

In this case, the difference between the output voltage of the output voltage and a reference voltage generating circuit of the sense amplifier circuit _{(V REF (D) -V on} (3)) is the difference in the case of the design value _{(V REF (D) -V on} ( 1)) is larger, so when the next erased memory cell is selected,
There is a drawback that the reading speed becomes slow.

There is also a method of using a memory cell that has not been written or erased as M ₅ , but the memory cell has a tunnel gate of about 100Å, and the floating gate is charged up through the tunnel gate during the manufacture of the EEPROM. Since the threshold value of the memory cell varies within the chip, a memory cell that has not been written or erased cannot be used as M ₅ .

[Problems to be Solved by the Invention]

As described above, the conventional reference voltage generation circuit 15 uses the IGFET as the current source that determines the output voltage V _REF, and the (gate width) / (gate length) of the IGFET, the reference connected to the gate electrode of the IGFET. By controlling the voltage of the read control line for output, the output voltage V _{REF is set} to the output voltage V _on of the sense amplifier circuit 12 when the written memory cell is selected,
Designed so that the erased memory cell is in the middle of the output voltage V _off of the sense amplifier circuit when selected.
The current-voltage characteristics of the IGFET and the written memory cells are different, so if the load curves of the sense amplifier circuit and the reference voltage generation circuit shift negatively due to variations in threshold values and process conditions. , If the difference between V _on and V _REF becomes smaller than the design value and the written memory cell is selected, it is difficult to detect with the comparison detector.

If the load curve shifts positively due to threshold variation and process condition variation, the difference between V _on and V _off becomes larger than the design value, and if the erased memory cell is selected, There is a drawback that the reading speed becomes slow. In addition, since the reference voltage generation circuit of the conventional example cannot arbitrarily change the output voltage at the stage of checking the function of the chip, it is estimated how much the current flowing in the written memory cell varies within the chip. It was not possible, and there was a drawback that it was not suitable for large capacity EEPROM.

It is an object of the present invention that, even if there is a variation in threshold value or a change in process condition, the comparison detector operates according to the design value, and the written memory cell is selected in the function check of the chip. Another object of the present invention is to provide a non-volatile semiconductor memory device capable of evaluating the variation in the current flowing through the memory cell and setting the output voltage of the reference voltage generating circuit to an appropriate value based on the evaluation result.

[Means for Solving the Problems]

The configuration of the present invention is a digital signal "0" or "1".
Corresponding to the output voltages of these sense amplifier circuits, a plurality of storage elements that store the data, a plurality of digit lines that output a voltage according to the stored contents of these storage elements, a sense amplifier circuit that detects a voltage change of these digit lines. In a non-volatile semiconductor memory device having a reference voltage generation circuit for generating a reference voltage for level determination, and a comparison detector for comparing the output voltage of the reference voltage generation circuit with the output voltage of the sense amplifier and taking out as an output voltage. The reference voltage generating circuit has a pseudo memory element having the same structure and the same characteristics as the memory element, a write circuit for writing the digital signal into the pseudo memory element, and the pseudo circuit supplied to the write circuit. At least a write control circuit for setting the write voltage of the storage element and the write time thereof is provided, and the write control circuit for writing to the pseudo storage element is provided. By setting the absolute value of the threshold value to be lower than the threshold value written in the storage element, the output voltage of the sense amplifier circuit when the storage element storing "0" is selected. And the output voltage of the sense amplifier circuit when the storage element storing "1" is selected.

〔Example〕

 The present invention will now be referred to the drawings.

FIG. 1 is a circuit block diagram of a reference voltage generating circuit (15) used in an embodiment of the present invention. In the figure, Q ₄ , Q ₅ , and I ₁ are the same as in FIG. 9, and M ₃ is a reference cell (hereinafter referred to as a reference cell) having the same structure and characteristics as the memory cells M _M11 to _Mn1 . The Y select line Y _R and the X select line X _R are connected to the reference cell Y decoder 4 and the reference cell X decoder 3, and when the reference cell M ₃ is selected by the control signal, the voltage V _PP is set in the write / erase mode. In read mode, voltage V _PP is supplied.
The drain of Q ₂ is the drain of FET Q ₅ and the gate is Y.
NE-IGFET for selection connected to select line Y _R and having the same (gate width) / (gate length) as Q _{7 in} FIG. 9, M ₁ has drain as the source of IGFET Q ₅ , and gate has X select NE-IGFET for selecting which is connected to line X _R, Q ₃ has its drain to the output CGS of the control gate voltage control circuit 13, the gate is Y
NE-IGFET connected to select line Y _R , M ₂ has drain IG
The source of FETQ ₃ is a NE-IGFET whose gate is connected to the X select line X _R , and the reference cell M ₃ has a drain
The source of IGFETM _{1 has} its source connected to the output V _S1 of (V _S ) and its gate connected to the source of IGFETM ₂ . Also, the charge pump circuit 2 condition for writing the reference cell M ₃ (V
_PP write pulse time) is determined, and the write control circuit 1 outputs V _PP to the output WCR when writing the reference cell M ₃ . In addition, the drain of Q ₁ is connected to the output CPR of the charge pump circuit 2, the source is connected to the drain of IGFET Q ₂ , and the gate is connected to the output WCR of the write control circuit 1, and the NE-IGFET for writing is used.
Is.

A method of setting the output voltage V _REF of the reference voltage generation circuit of this embodiment will be described.

As shown in FIG. 2, the threshold value of the written memory cell
V _Tn (W) depends on the write voltage V _PP and the write pulse width t _pw . For example, if the charge pump circuit 2 is V _PP = 20
It is understood from FIG. 2 that V _Tn (W) = − 4 V is obtained by designing V and t _pw = 1 ms and writing the memory cell. V
The current-voltage characteristic of the current flowing through the memory cell when _Tn (W) = − 4V is shown in I _ce of FIG. 3, which is the same as I _ce of FIG.

Since the reference voltage generating circuit of this embodiment has the reference cell M ₃ having the same structure and characteristics as the memory cell,
The reference cell M ₃ is written by the same means as the memory cell, the threshold V _TMR (W) is shifted more negatively than the initial state, and the current flowing through the reference cell M ₃ is controlled to output voltage V _REF. Can be set to a desired value.

For example, the threshold V _TMR (W) of the reference cell M ₃ is set to V
_When setting _TMR (W) = − 2V, charge pump circuit 2 shown in FIG. 2 to FIG. 1 should have V _PP = 20V, t _pw = 0.1ms.
Alternatively, it can be seen that the design should be V _PP = 19V and t _pw = 1ms.

The current-voltage characteristic of the current flowing through the reference cell when the reference cell M ₃ is written by designing as described above is as shown by I _R in FIG.

Comparing I _{R in} FIG. 3 with I _R3 in FIG. 10, the reference voltage generating circuit of the present embodiment has the reference cell M ₃ , so that I _R has the same saturation region as I _ce. The current-voltage characteristic does not exist. When this reference voltage generating circuit is used, the written memory cells are not written when the load curves of the sense amplifier circuit and the reference voltage generating circuit change from the design values due to variations in threshold values, fluctuations in process conditions, etc. The relationship between the output voltage V _on of the sense amplifier circuit when selected and the output voltage V _REF of the reference voltage generation circuit will be described with reference to FIGS. 3 and 4.

Similar to FIG. 11, FIG. 4 shows the output voltage of the sense amplifier circuit with respect to the current flowing in the memory cell and the reference cell.
The change in V _on and the output voltage V _REF of the reference voltage generation circuit are shown. The output voltage of the sense amplifier circuit when the current value is 0 is
It corresponds to the output voltage V _off of the sense amplifier circuit when the erased memory cell is selected.

(1) When the load curve L ₁ shifts negatively with L ₂ , the intersection point P ₁ between the load curve and I _ce changes to P ₂ and the intersection point R ₁ between the load curve and I _R
Changes to R ₂ . Therefore, the current I _ON flowing in the memory cell is
(1) changes to I _ON (2), and the current I _REF (1) flowing in the reference cell changes to I _REF (2). At this time, from FIG. 4, the output V _ON (1) of the sense amplifier circuit is V
_{When ON} (2), the output voltage V _REF (1) of the reference voltage generator is
It can be seen that it changes to V _REF (2).

(2) When the load curve L ₁ shifts positively with L ₃ , the intersection point P ₁ between the load curve and I _ce changes to P ₃ and the intersection point R ₁ between the load curve and I _R
Changes to R ₃ . Therefore, the current I _ON flowing in the memory cell is
(1) changes to I _ON (3), and the current I _REF (1) flowing in the reference cell changes to I _REF (3). At this time, from FIG. 4, the output V _ON (1) of the sense amplifier circuit is V
_{When ON} (3), the output voltage V _REF (1) of the reference voltage generator is
It can be seen that it changes to V _REF (3).

As described above, in the present embodiment, even if the load curve L ₁ shifts to a negative value like L ₂ , the output voltage V of the sense amplifier circuit is
The difference between _ON and the output voltage V _REF of the reference voltage generator (V
_REF (2) -V _ON (2)) is the difference (V
_REF (1) -V _ON (1)) has a smaller reduction amount than that of the conventional example. Therefore, as in the case of the conventional example, when the memory cell written by the comparison detector in the next stage is selected. It is not difficult to detect.

Even if the load curve L ₁ shifts positively to L ₃ , the output voltage V _ON of the sense amplifier circuit and the output voltage V V of the reference voltage generation circuit
_Since the difference in _REF (V _REF (3) -V _ON (3)) is smaller than the difference in the design value (V _REF (1) -V _ON (1)), it is smaller than in the case of the conventional example. As in the case of the conventional example, the read speed does not slow down even if the next erased storage cell is selected.

FIG. 5 is a block diagram of the second embodiment of the present invention. In this embodiment, instead of the charge pump 2 in the first embodiment, an external terminal 20 and a gate and a drain are commonly connected to the external terminal 20 and a source is connected to an output line.
NE-IGFET Q ₆ for backflow prevention to prevent current from flowing in
Is provided.

In this embodiment, a method of writing the reference cell M ₃ will be described.

In the first embodiment, the reference cell M ₃ is written by the write voltage V _PP and the write pulses S ₁ and T ₁ (FIG. 6) from the charge pump circuit 2 built in the chip. In the embodiment, the write voltage and the write pulse can be directly controlled by the external terminal 20. Also in this embodiment, as described in the first embodiment, the reference cell M ₃
An example in which the threshold value V _TMR (W) of is set to V _TMR (W) = − 2V will be described.

In the figure, the source of FERQ ₆ is the charge pump circuit 2.
Pulse voltage (for example, the maximum value is 22.5V, the pulse time is 0.1ms) is applied to the terminal 20 as shown by pulse S ₁ in FIG. 6 so that the source voltage is 20V. Or the source voltage of FET Q ₆ is ₁ as shown in pulse T 1.
A pulse voltage (for example, the maximum value is
21.5V, pulse time 1ms) should be added. Input voltage S ₁ ,
Source voltages S ₂ and T ₂ are shown for T ₁ .

In the present embodiment, when the load curve shifts from the design value to the positive or negative value due to the variation of the threshold value, the change of the process condition, etc., the change from the design value of the voltages V _on and V _off is the first value. This is exactly the same as the embodiment.

Further, the present embodiment, an arbitrary write voltage from the external terminal 20,
Since the reference cell M ₃ can be written in the write pulse time to change the threshold voltage and change the output voltage of the reference voltage generation circuit, by mounting this embodiment in the EEPROM, it is possible to check the function of the chip. By applying a high voltage from the external terminal to write the reference cell, changing the output voltage of the reference voltage generation circuit, and checking whether the written memory cell can be read correctly,
It is possible to evaluate how much the current flowing in the written memory cells varies in the memory cells in the chip, and from this evaluation result, the output voltage of the reference voltage generation circuit is considered in consideration of the variation in the current flowing in the memory cells. It can be set to an appropriate value.

〔The invention's effect〕

As described above, the semiconductor memory device of the present invention has, in the reference voltage generation circuit, the pseudo memory element (reference cell) having the same structure and characteristics as the memory cell, and the write circuit. A cell is written, the threshold value of this reference cell is changed, the current flowing through this reference cell is controlled, and the output voltage of the reference voltage generation circuit is set to the sense amplifier circuit when the written memory cell is selected. Output voltage and the output voltage of the sense amplifier circuit when the erased storage cell is selected can be set to an intermediate value.

Therefore, the current-voltage characteristics of the memory cell and the reference cell both have characteristics that do not have a saturation region, and the load curves of the sense amplifier circuit and the reference voltage generation circuit are designed due to changes in the threshold value and variations in process conditions. Change from the value,
Even if the current flowing through the memory cell changes and the output voltage of the sense amplifier circuit changes, the current flowing through the reference cell also changes and the output voltage of the reference voltage generating circuit can also change.

Therefore, even if the load curves of the sense amplifier circuit and the reference voltage generation circuit change from the design values, the output voltage V _REF of the reference voltage generation circuit and the sense amplifier circuit when the written memory cell is selected The difference in the output voltage V _on (V _REF −V _on ) becomes almost as designed, and this difference becomes small as in the case of the conventional example, making it difficult to detect with the comparison detector in the next stage,
If this difference becomes too large and the next erased storage cell is selected, the reading speed will not slow down.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a reference voltage generating circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing fluctuations of a threshold V _T during writing and erasing of a memory cell used in this embodiment. FIG. 3 is a current-voltage characteristic diagram of the load curve, the memory cell and the reference cell of this embodiment, FIG. 4 is an output voltage characteristic diagram of the memory cell of this embodiment, and FIG. 5 is the second embodiment of the present invention. FIG. 6 is a circuit diagram of a reference voltage generating circuit of the embodiment, FIG. 6 is a waveform diagram of a pulse applied to an external terminal of the second embodiment, and FIG. 7 is a conventional EEPR.
FIG. 8 is a block diagram of an example of OM, FIG. 8 is a circuit diagram of an example of the sense amplifier of FIG. 7, FIG. 9 is a circuit diagram of an example of the reference voltage generation circuit of FIG. 7, and FIG. FIG. 11 is a current-voltage characteristic diagram of the memory cell and the reference cell, and FIG. 11 is an output voltage characteristic diagram of the conventional memory cell. 1,10 ... write control circuit, 2, 11 ... charge pump circuit, 3 ... X decode circuit, 4 ... Y decode circuit, 12
...... Sense amplifier circuit, 13 …… Control gate voltage control circuit, 14 …… Source voltage control circuit, 15 …… Reference circuit, 16 …… Comparison detector, 17 …… Output buffer, 20
...... External terminal, 21 …… Output terminal, I ₁ , I ₂ …… Inverter, M ₁ , M ₂ , M ₄ , M ₅ …… NE-IGFET, M ₃ …… Reference cell, M _{11 to} M _n1 … … Memory cell, M _M11 …… Memory cell, M
_S11 …… Selection cell, Q ₁ …… Write NE-IGFET, Q ₂ , Q ₃ , Q
_{5 to} Q ₇ ,, Q ₉ , Q _{11 to} Q ₁₃ ...... NE-IGFET, Q ₄ , Q ₈ ...... PE-IGFET

Claims (1)

[Claims] 1. A plurality of storage elements that store "0" or "1" of a digital signal, a plurality of digit lines that output a voltage according to the stored contents of these storage elements, and a voltage change of these digit lines is detected. A plurality of sense amplifier circuits, a reference voltage generating circuit that generates a reference voltage for level determination corresponding to the output voltages of these sense amplifier circuits, an output voltage of the reference voltage generating circuit, and an output voltage of each of the sense amplifier circuits. In a non-volatile semiconductor memory device having a comparison detector for comparing and outputting as a comparison output, the reference voltage generating circuit includes a pseudo memory element having the same structure and the same characteristics as the memory element, and the pseudo memory element. A write circuit for writing the digital signal, a write voltage supplied to the write circuit and a write time for the pseudo memory element At least a write control circuit for setting the absolute value of the threshold value written in the pseudo storage element lower than the threshold value written in the storage element, With respect to the reference voltage of the generating circuit, the output voltage of the sense amplifier circuit when the storage element storing "0" is selected, and the output voltage of the sense amplifier circuit when the storage element storing "1" is selected A non-volatile semiconductor memory device characterized in that it can be set to a voltage.