JPH07105156B2 - Semiconductor non-volatile memory device - Google Patents

Description

The present invention relates to a semiconductor non-volatile memory device, and more particularly to a read data output when a memory device shifts from a non-selected state to a selected state. The technology relates to preventing a 1 "→“ 0 ”→“ 1 ”level glitch from occurring.

(Prior Art) A conventional semiconductor read-only memory device (hereinafter referred to as ROM),
For example, a part of a CMOS type (complementary insulated gate type) mask ROM is shown in FIG. That is, 1-11 to 1-mn are m rows × n
ROM cells arranged in a matrix of columns, each of which is composed of, for example, an N-channel MOS transistor whose source is connected to the ground potential Vss, and its gate threshold value is set according to "0" or "1" of stored data. ing.

In the memory cell array MA in which the ROM cells 1-11 to 1-mn are arranged in a matrix, WL1 to WLm are row lines commonly connected to the gates of the ROM cells in the same row, and BL1 to BLn are in the same column.
A column line commonly connected to the drains of the ROM cells. RD is a row decoder that selects the row line according to the row address input, CS1 to CSn are column selection transistors connected in series to the column lines BL1 to BLn, and the other ends thereof are commonly connected. For example, it comprises an N-channel MOS transistor. CD is a column decoder that selects the column selection transistor according to the column address input.

Between the Vcc power supply (for example, 5V) and the common connection point (common column line) of the column selection transistors CS1 to CSn, an N-channel MOS transistor QS controlled to be turned on / off by a chip selection signal ▼ ▲ given to the gate. It is connected. The common column line is connected to the input end of a sense amplifier SA that detects and amplifies a read signal. OB is a data output buffer that buffer-amplifies the output of the sense amplifier SA.

A semiconductor chip (ROM chip) on which the ROM is formed is provided with a control circuit (not shown) for controlling the selected state / non-selected state by the chip selection signal ▼ ▲.

The normal read operation of the ROM is well known and will be briefly described below. Here, it is assumed that the high level / low level of the potential of the selected column line is designed to correspond to the “0” level (low level) / “1” level (high level) of the read data output. .

At the time of access when the column address input remains unchanged and the row address input changes, the potential of each column line connected to each memory cell selected by row selection is such that the selected cell is in the OFF state (memory data “0” Condition), for example, 3.5V
High level (higher than the sense amplifier judgment standard),
When the selected cell is in the ON state (state of stored data “1”), it becomes a low level of 2.5 V (a level lower than the sense amplifier determination standard). That is, since the potential of the column line connected to the selected memory cell changes between the above 2.5V and 3.5V, the read data output changes between "1" and "0",
It changes like “1” → “0” or “1” → “1” or “0” → “0” or “0” → “1”.

On the other hand, at the time of access when the row address input is unchanged and the column address input is changed, the read data output corresponding to the level of the column line connected to the selected memory cell appears, and the read data output is “1” → “0” or “1” → “1” or “0” → “0” or “0” → “1”
It changes like.

Next, the read operation when the ROM chip shifts from the non-selected state to the selected state will be described with reference to FIG.

Now, when the ROM is used by being connected to a computer system, the row line W in the state where this ROM chip is not selected (the state where the N-channel MOS transistor QS is off) is used.
It is assumed that L1 and the column line BLn are selected, and the selected cell 1-1n at this time is in the off state (state of stored data “0”). In this state, the column line BLn is in an electrically floating state, and if this state lasts for a long time with respect to the memory cycle, the potential of the column line BLn will change to the cells 1 connected to it.
Junction leakage current of -1n to 1-mn decreases to ground potential.

After that, it is assumed that this ROM chip is in the selected state and the row line WL2 is selected in place of the row line WL1 that has been selected so far. Immediately after this selection, the potential of the column line BLn is the ground potential. However, during this selection, the chip selection signal ▼ ▲ becomes the ground potential (for example, 0V), which causes the N-channel NO
S transistor QS is turned on and the selected column line BLn
Begins to be charged.

On the other hand, normally, the row lines WL1 to WLm are made of polysilicon, polycide, etc., and due to the signal delay due to the presence of the resistance component thereof, the rise of the row selection signal is delayed more on the column line BLn side than on the column line BL1 side. The selection of cells 1-2n connected to the column line BLn is delayed from the start of row selection. During this delay, cell 1-
Since 2n is not selected, the column line BLn becomes transiently in a floating state, and this column line BLn is at a high level (a level higher than the sense amplifier determination standard) due to the charging current flowing through the N-channel MOS transistor QS and the column selection transistor CSn. Cells 1-2n that are charged up to and then connected to column line BLn
Will be selected. When the selected cell 1-2n is in the ON state (stored data "1" state), the potential of the column line BLn is at the low level (lower than the sense amplifier determination standard) that should be the original high level. Go down to.

In the above operation, the read data output of the data output buffer OB transiently becomes "0" during the change of "1" → "1" as shown in FIG. 5, and "1" → " A glitch from 0 "to" 1 "occurs.

However, as described above, the read data output changes from “1” to “0”.
→ When a glitch of “1” occurs, the transition of the normal read data output “1” → “0” or “0” → “1” changes in the power supply potential due to the change in the output current of the data output buffer OB (self Noise) becomes large, which causes deterioration of the operation margin of the input buffer and malfunction. Then, when the output of the sense amplifier SA is inverted by the output of the memory cell that is erroneously selected due to the malfunction of the address input buffer,
The operation in which the change in the output current of the data output buffer OB occurs again occurs repeatedly, causing oscillation.

The same applies to other ROMs.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor nonvolatile memory device, when the non-selected state shifts to the selected state, the read data output of “1” → “0” → “1” level is changed. A glitch may occur, which causes a large fluctuation in the power supply potential due to a change in the current of the data output buffer, which leads to deterioration of the operating margin of the input buffer, malfunction, and oscillation of the sense amplifier.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to output “1” → “0” → “1” level to the read data output when the storage device shifts from the non-selected state to the selected state. It is an object of the present invention to provide a semiconductor nonvolatile memory device capable of preventing the occurrence of the glitch.

[Configuration of the Invention] (Means for Solving the Problems) The present invention selects a memory cell array in which nonvolatile memory cells are arranged in a matrix of m rows × n columns, and m row lines of the memory cell array. A row decoder, and a column selection transistor for selecting n column lines of the memory cell array,
A column decoder that controls the column selection transistor, a sense amplifier that detects and amplifies a read signal from the selected column line that passes through the column selection transistor, a data output buffer that amplifies the output of the sense amplifier, and a selection control signal. And a control circuit for controlling the selected state / non-selected state of the memory device according to
One dummy row line added to the memory cell array and having the same shape as the row line;
N column dummy memory cells each connected to one column line and each having the same shape as the memory cell and set so as to be turned on when selected, and when the memory device is not selected. A dummy row line selection circuit that is controlled so as to select the dummy row line and not select the dummy row line when a memory device is selected, and when the memory device shifts from a non-selected state to a selected state, It is characterized in that the dummy row line shifts from the selected state to the non-selected state in synchronization with the change of the row line to be selected in the memory cell array from the non-selected state to the selected state.

(Operation) Since the dummy row line is in the selected state when the memory device is in the non-selected state, each column line is set to the ground potential by the dummy memory cell in the ON state. Then, when the memory device shifts from the non-selected state to the selected state, the dummy row line shifts from the selected state to the non-selected state in synchronization with the shift of the row line to be selected in the memory cell array from the non-selected state to the selected state. Move to. In this case, since the dummy memory cells in the same column are selected and the selected column line is held at the ground potential until the memory cell is selected, it is possible to prevent the selected column line from transiting to a floating state. Moreover, since the dummy memory cell is in the non-selected state when the selected memory cell is selected, it does not hinder the memory cell selection operation. Therefore, the potential of the column line connected to the selected memory cell becomes a low level or a high level from the ground potential that has been set up to that time, depending on the stored data of the selected memory cell, so that the read data is output. There is no glitch of “1” → “0” → “1” level.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows, for example, a part of the mask ROM, and in comparison with the conventional mask ROM described above with reference to FIG.
(A) A dummy row line WLd having the same shape as the row line is added to the memory cell array MA ″, and (b) each has the same shape as the memory cell and is turned on when selected (state of stored data “1”). ) N dummy memory cells (eg N-channel MOS transistor 1d-
1 to 1d-n), each gate is connected to the dummy row line WLd, and each drain is n of the memory cell array MA ″.
(C) Dummy row line WLd connected to the book column lines BL1 to BLn and controlled so as to select the dummy row line WLd when the storage device is not selected and not to select the dummy row line WLd when the storage device is selected. A selection circuit (column line reset circuit) DS is provided,
(D) The row decoder RD ″ is different in that all the row selection signals are set to a level equal to or lower than the threshold voltage of the memory cell when the memory device is not selected. Attached.

That is, a memory in which m rows × n columns of ROM cells 1-11 to 1-mn and 1 row × n columns of dummy memory cells 1d-1 to 1d-n are arranged in a matrix of (m + 1) rows × n columns. A cell array MA ″ is formed. Each row line WL1 to WLm of this memory cell array MA ″ is connected to the output of the row decoder RD ″, and the dummy row line WLd is connected to the output of the dummy row line selection circuit DS. Further, column selection transistors CS1 to CSn are connected in series to each column line BL1 to BLn of the memory cell array MA ″, and common connection points (common column lines) at the other ends of the column selection transistors CS1 to CSn are connected. Vcc
An N-channel MOS transistor QS, which is on / off controlled by a chip selection signal ▼, is connected to the power source. CD is a column decoder, SA is a sense amplifier, OB is a data output buffer, and a chip select signal ▼ ▲
Is provided with a control circuit (not shown) for controlling the ROM chip in the selected state / non-selected state.

Next, the operation of the ROM will be described. Here, the normal read operation is basically the same as the operation of the ROM shown in FIG. 3, so its detailed description is omitted, and the following will be selected from the non-selected state of the chip in which this ROM is formed. The read operation at the transition to the state will be described with reference to FIG.

Now, when the ROM is used by being connected to a computer system, in the state where this ROM chip is not selected (N-channel MOS transistor QS is off), the column line B
It is assumed that Ln is selected. In this state, since the dummy row line WLd is in the selected state, the dummy memory cells 1d-n in the on state set the column line BLn to the ground potential.
After that, it is assumed that this ROM chip is in the selected state and the row line WL2 is selected in place of the row line WL1 that has been selected so far. And at the time of this selection, the chip selection signal ▼ ▲
The voltage becomes 0 V, which turns on the N-channel MOS transistor QS and tries to start charging the selected column line BLn.

On the other hand, usually, the row lines WL1 to WLm and the dummy row line WLd are made of polysilicon, polycide, or the like. This allows the row line
WL1 to WLm are
The rising of the row selection signal is delayed on the column line BLn side than on the column line BL1 side, and the selection of the cells 1-2n connected to the column line BLn is delayed from the start of the row selection.

However, during this delay, the dummy row line WLd is connected to the column line BLn because the fall of the row selection signal is delayed on the column line BLn side than on the column line BL1 side due to the signal delay due to the presence of the resistance component. Since the transition of the dummy memory cells 1d-n to the non-selected state is delayed, the potential of the column line BLn is held at the ground potential and does not transitively enter the floating state. It is never charged to a high level. Then, after this, when the cells 1-2n connected to the column line BLn are selected, the dummy memory cells 1d-n are in the non-selected state,
It does not hinder the selection operation of the memory cells 1-2n. Therefore, the potential of the column line BLn becomes a low level or a high level from the ground potential that has been set so far, depending on the storage data of the selected memory cell 1-2n.

That is, in the ROM, since the dummy row line WLd is in the selected state when the ROM chip is in the non-selected state, each column line BL1 to BLn is set to the ground potential by the dummy memory cells in the ON state. Then, when the memory device shifts from the non-selected state to the selected state, the dummy row line WLd is in the selected state in synchronization with the shift of the row line to be selected in the memory cell array MA ″ from the non-selected state to the selected state. In this case, since the dummy memory cells in the same column are selected and the selected column line is held at the ground potential until the memory cell is selected, the selected column line is transiently changed. The floating state is prevented, and since the dummy memory cell is in the non-selected state when the memory cell is selected, it does not interfere with the memory cell selection operation. The potential of the column line changes from the previously set ground potential to the low level or the high level according to the data stored in the selected memory cell. Therefore, the read data output is "1" → "0" → "1" level. It never glitches.

Although the mask ROM is shown in the above embodiments, the present invention is a semiconductor nonvolatile memory device such as a UV erasable / rewritable ROM (EPROM) or an electrically erasable / rewritable ROM (EEPROM). Can also be applied to.

[Effect of the Invention] As described above, according to the semiconductor nonvolatile memory device of the present invention, when the memory device shifts from the non-selected state to the selected state,
Since it is possible to prevent glitches of "1" → "0" → "1" level from occurring in the read data output, deterioration of the operation margin of the input buffer or malfunction due to this glitch,
Oscillation of the sense amplifier can be prevented.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing a part of a ROM according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing an example of a read operation of the ROM of FIG. 1, and FIG. A configuration explanatory view showing a section,
FIG. 4 is a waveform diagram showing an example of a read operation of the ROM of FIG.
FIG. 5 is a waveform diagram showing the output potential of the data output buffer in the read operation of FIG. 1-11 to 1-mn ... ROM cells, 1d-1 to 1d-n ... dummy memory cells, MA ″ ... memory cell array, WL1 to WLm ... row lines,
WLd ... Dummy row line, BL1 to BLn ... Column line, RD "... Row decoder, DS ... Dummy row line selection circuit (column line reset circuit), CS1 to CSn ... Column selection transistor, CD ... Column Decoder, QS ... N-channel MOS transistor, SA ... Sense amplifier, OB ... Data output buffer.

Claims (1)

[Claims] 1. A memory cell array in which non-volatile memory cells are arranged in a matrix of m rows × n columns, a row decoder for selecting m row lines of the memory cell array, and n columns of the memory cell array. A column selection transistor that selects a line, and a column decoder that controls the column selection transistor,
A sense amplifier that detects and amplifies a read signal from the selected column line that has passed through the column selection transistor, a data output buffer that amplifies the output of the sense amplifier by a buffer, and a selection control signal to select / unselect the storage device. In a semiconductor nonvolatile memory device including a control circuit for controlling, one dummy row line having the same shape as the row line, added to the memory cell array, the dummy row line and the n column lines. N dummy memory cells in one row, each of which has the same shape as the memory cell and is set to be in an ON state when selected, and the dummy row line when the memory device is not selected. A dummy row line selection circuit which is controlled so as not to select the dummy row line when selecting the storage device, and the storage device is in a non-selected state. From the selected state to the selected state of the memory cell array, the dummy row line shifts from the selected state to the unselected state in synchronization with the transition from the unselected state to the selected state. Non-volatile storage device.