JPH07105491B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an offset gate structure of a MIS element.

[Background Art] As a hot carrier countermeasure associated with miniaturization of a metal insulator element (MIS element), for example, IEEE Transaction on
Electron Devices, April 1982, Volume ED-29, Issue 4, LDD
(Lightly Doped Drain) structure is proposed. This L
As shown in FIGS. 1 to 3, the DD structure has a gate electrode 2 made of polycrystalline polysilicon on a P-type silicon semiconductor substrate 1.
Is formed via the gate oxide film 3, and low-concentration N ⁻ ion implantation is performed. Reference numeral 4 is a relatively thick silicon oxide film,
Reference numeral 5 is a thin silicon oxide film. Next, a silicon oxide film is formed on the entire surface by CVD (Chemical Vapor Deposition) and anisotropic dry etching is performed to form sidewalls 6 of the silicon oxide film on the side surfaces of the gate electrode 2. After forming the sidewall 6, high concentration N ⁺ ion implantation is performed again to obtain an offset gate structure (LDD structure). In FIG. 3, reference numeral 7 indicates a high-concentration N ⁺ impurity diffusion region, and reference numeral 8 indicates a low-concentration N ⁻ impurity diffusion region.

According to the study of the present inventor, the following problems occur in manufacturing such a conventional LDD structure. That is,
That is, N ⁻ ion implantation and N ⁺ ion implantation are separately performed in the process before and after the sidewall is formed. This complicates the process, especially for complementary MI.
When this LDD structure is used for the S element (CMIS element), the silicon oxide film formed over the entire surface to form the sidewall is not effectively used as an ion implantation mask for the source / drain formation, and N ^- ion implantation and A mask for each step of N ⁺ ion implantation was required. further,
It has a drawback that it is difficult to controllably leave the silicon oxide film forming the sidewall by anisotropic dry etching.

[Object of the Invention] An object of the present invention is to provide a method of manufacturing a semiconductor device which can simplify both steps of forming a sidewall and ion-implanting a source / drain, and can leave the width of the sidewall well controlled. Is.

The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[Outline of the Invention] The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, a nitride (silicon nitride, Si ₃ N ₄ ) is used to form the sidewall, and N ⁻ ions and N 3
^{Since +} ions are sequentially implanted after the formation of the side wall, a method of manufacturing a MIS device with improved side wall controllability and steps is achieved.

Further, in the CMIS element, a nitride film is used as an ion implantation mask when forming the source / drain of the N-channel MIS element and the P-channel MIS element, and
Since the sidewalls are formed by anisotropic dry etching of the silicon nitride film on which the source and drain ions are to be implanted in the respective regions of the channel and the P channel, the sidewall controllability and The present invention achieves a method for manufacturing a MIS device with improved processes.

[Embodiment] A preferred embodiment of the method for manufacturing a semiconductor device of the present invention will be described in detail below with reference to FIGS. 4 to 8.

FIG. 4 is a sectional view of an embodiment in which the manufacturing method of the present invention is applied to an N-well type CMOS device. In a semiconductor substrate 1, for example, a P-type silicon semiconductor substrate, active regions separated by a relatively thick silicon oxide film 2 are defined, and the region on the left side of the drawing is an N-channel MOS element (FE
T), a P-channel MOS element (FET) is formed in the right region. Reference numeral 3 is a gate oxide film, for example, a silicon oxide film. A gate electrode 4 of polycrystalline silicon is formed in each region on the gate oxide film 3. Reference numeral 5 indicates an N well in the N type impurity region, and reference numeral 6 is a thin silicon oxide film.

In the state of FIG. 4, a silicon nitride film 7 is deposited on the entire surface of the semiconductor substrate 1 as shown in FIG. Next, as shown in FIG. 6, in order to form the source and drain regions of the N-channel MOS device on the left side of the drawing, the right half of the silicon nitride film 7 covering the entire surface, that is, the P-channel MOS device side is selected. Then, a photoresist film is formed, and the left half silicon nitride film is etched. Since this etching employs anisotropic dry etching, the sidewall 8 having a desired thickness can be formed on the sidewall of the gate electrode 4.

In FIG. 7, after removing the photoresist film, ion implantation for forming the source and drain regions is performed. At this time, the P-channel MOS element side is covered with the silicon nitride film 7. That is, the silicon nitride film 7 used for forming the sidewall 8 is effectively used as it is as a mask for ion implantation for forming the source and drain regions.

Here, first, ions having a large diffusion coefficient, for example, phosphorus are used to perform ion implantation for forming the low concentration N ⁻ impurity diffusion layer 9. Subsequently, ions having a small diffusion coefficient, for example, arsenic are used to perform ion implantation for forming the high-concentration N ⁺ impurity diffusion layer 10. By the way, the width of the sidewall made of the conventional silicon oxide film is about 0.3 to 0.4 μm, while the width of the sidewall made of the silicon nitride film can be controlled to about 0.1 to 0.2 μm. Therefore, the short channel effect is improved, and the gate processing dimension and the electrical channel length become closer to each other, and the electrical characteristics are stabilized. Furthermore, since the controllability of the width of the sidewall is good, it is possible to reduce the parasitic capacitance due to the overlap with the gate electrode and reduce the electric field concentration by expressing the N ^- impurity diffusion layer 10 by optimizing the ion implantation. Can be achieved.

After forming the N-channel MOS element, as shown in FIG. 8, a thick silicon oxide film 11 is formed on the N-channel MOS element, and the sidewall 12 is formed as described above using this as a mask. P of the P-channel MOS device ^- type and P ⁺
The source and drain regions of the mold are formed by the same method as shown in FIG. However, boron is used as the impurity, and the ion implantation for forming the semiconductor region 14 having a low impurity concentration and the ion implantation for forming the semiconductor region 13 having a high impurity concentration are sequentially performed. After that, the silicon oxide film 11 is removed and an interlayer insulating film 15 made of phosphosilicate glass is newly added.
To form. After forming contact holes for connecting upper layer wirings to the source and drain regions in this interlayer insulating film, aluminum wirings 16 are formed (FIG. 9).

[Effect] As described above, since anisotropic etching using silicon nitride is performed to form the sidewall, the controllability of the width of the sidewall is improved and various electrical characteristics are improved. The effect of being peeled off is obtained.

Further, since the N-type low-concentration and high-concentration ions for the offset structure are implanted at a time after forming the sidewalls, the process can be simplified.

Further, in the CMIS element, a silicon nitride film is used as an ion implantation mask when forming the source and drain regions of the N-channel and P-channel MIS elements, and a sidewall is formed by this silicon nitride film immediately before the ion implantation. Therefore, there is an effect that the controllability of the sidewall and the simplification of the process can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, P channel
The ion implantation for forming the MIS element may be once. Alternatively, an N type semiconductor substrate and a P type well may be used.

[Field of Use] The present invention is effective when applied to a large-scale integrated circuit, particularly a process having a gate length of 1 to 2 μm. Especially, it can be effectively applied to CMOS devices.

[Brief description of drawings]

1 to 3 are sectional views showing a manufacturing process of a conventional LDD structure, and FIGS. 4 to 9 are sectional views showing a manufacturing process in which the manufacturing method of the present invention is applied to a CMOS device. 1 ... Semiconductor substrate, 3 ... Gate oxide film (insulating film), 4
...... Gate electrode, 7 …… Silicon nitride film, 8,12
…… Sidewall, 9 …… High-concentration impurity diffusion layer, 10…
… Low-concentration impurity diffusion layer, 11 …… Silicon oxide film (insulating film).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/092

Claims (1)

[Claims] 1. A P-type semiconductor region and N on the main surface of a semiconductor substrate.
A gate electrode of the MIS element is formed in each element formation region of the type semiconductor region via a gate insulating film, a silicon nitride film is formed on the entire surface of the main surface of the semiconductor substrate, and a P type semiconductor region and an N type semiconductor region are formed. The silicon nitride film is left so as to cover one region of the element formation region,
The silicon nitride film is etched so that the sidewall of the silicon nitride remains on the side surface of the gate electrode in the other region of the element forming region of the P-type semiconductor region and the N-type semiconductor region, and the gate of the other region is etched. Using the side wall formed on the side surface of the electrode as a mask, an impurity of a conductivity type opposite to that of the semiconductor region is introduced into the semiconductor region on both sides of the gate electrode by ion implantation,
Next, a silicon nitride covering the one region of the P-type semiconductor region and the N-type semiconductor region is formed so as to leave a sidewall of the silicon nitride on the side surface of the gate electrode in the one region. The film is removed by etching, and an impurity having a conductivity type opposite to that of the semiconductor region is introduced into the semiconductor regions on both sides of the gate electrode by ion implantation using the sidewalls formed on the side surfaces of the gate electrode in the one region as a mask. A method for manufacturing a characteristic semiconductor device.