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JPH07105597B2 - Method for manufacturing multilayer ceramic substrate - Google Patents
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JPH07105597B2 - Method for manufacturing multilayer ceramic substrate - Google Patents

Method for manufacturing multilayer ceramic substrate

Info

Publication number
JPH07105597B2
JPH07105597B2 JP6889590A JP6889590A JPH07105597B2 JP H07105597 B2 JPH07105597 B2 JP H07105597B2 JP 6889590 A JP6889590 A JP 6889590A JP 6889590 A JP6889590 A JP 6889590A JP H07105597 B2 JPH07105597 B2 JP H07105597B2
Authority
JP
Japan
Prior art keywords
polishing
ceramic substrate
green sheet
layer
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6889590A
Other languages
Japanese (ja)
Other versions
JPH03268482A (en
Inventor
貞夫 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6889590A priority Critical patent/JPH07105597B2/en
Publication of JPH03268482A publication Critical patent/JPH03268482A/en
Publication of JPH07105597B2 publication Critical patent/JPH07105597B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】 〔概要〕 多層セラミック基板の製造方法に関し、 セラミック基板の表裏両面の平面度調整、表裏両面の平
行度調整及び板厚寸法調整を必要最小限の研磨によって
高精度に行え、しかも、研磨によるパターン層の損傷を
確実に防止できるようにすることを目的とし、 所要の導体パターンを形成した1群のグリーンシートか
らなるパターン層の表面側と裏面側とにそれぞれ別の1
群のグリーンシートからなる研磨層を積層する多層セラ
ミック基板の製造方法において、表裏各研磨層のうちの
一方に厚さ調整代となるグリーンシートを積層すると共
に、表裏各研磨層に平行度調整代となるグリーンシート
と、平面度調整代となるグリーンシートとを順に積層
し、かつ、表裏各研磨層に積層される各グリーンシート
にその積層順位を表示する表示手段を設けた後、各研磨
層のグリーンシートをその積層順位に従って順に積層す
る構成とした。
DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method for manufacturing a multilayer ceramic substrate, which is capable of highly accurately adjusting flatness of both front and back surfaces of a ceramic substrate, parallelism of both front and back surfaces and plate thickness dimension by minimum necessary polishing. In addition, for the purpose of surely preventing the damage of the pattern layer due to polishing, different patterns are formed on the front surface side and the back surface side of the pattern layer formed of a group of green sheets on which the required conductor patterns are formed.
In the method for manufacturing a multilayer ceramic substrate in which a polishing layer composed of a group of green sheets is laminated, a green sheet serving as a thickness adjusting margin is laminated on one of the front and back polishing layers, and a parallelism adjusting margin is formed on each of the front and back polishing layers. After laminating a green sheet that becomes a flatness adjusting margin and a green sheet that becomes a flatness adjusting margin in order, and providing a display means for displaying the stacking order on each green sheet laminated on each front and back polishing layer, each polishing layer The green sheets of No. 2 were laminated in order according to the stacking order.

〔産業上の利用分野〕[Industrial application field]

本発明は、例えば大型電子計算機等に使用される多層セ
ラミック基板の製造方法に関し、特に、強制水冷等の冷
却方式に対応できる程度の精密な表裏両面の平面度調
整、平行度調整及び板厚寸法調整を必要最小限の研磨に
よって行えるようにした多層セラミック基板の製造方法
と、研磨された研磨層の位置を簡単に判別できるように
した、多層セラミック基板の製造方法とに関する。
The present invention relates to a method for manufacturing a multilayer ceramic substrate used in, for example, a large-scale electronic computer, and in particular, it is precise in adjusting the flatness of both front and back surfaces, parallelism adjustment, and plate thickness dimension to the extent that it can support cooling systems such as forced water cooling. The present invention relates to a method for manufacturing a multilayer ceramic substrate, which can be adjusted by polishing to a minimum necessary amount, and a method for manufacturing a multilayer ceramic substrate, which allows the position of a polished polishing layer to be easily determined.

〔従来の技術〕[Conventional technology]

近年、人間社会のあらゆる場面で多量の情報が交換さ
れ、処理されるためになるに連れ、種々の情報を処理す
るために使用される電子計算機の処理速度の高速化及び
処理機能の多様化が著しく急速に促進されている。
2. Description of the Related Art In recent years, as a large amount of information is exchanged and processed in every scene of human society, the processing speed of electronic computers used for processing various information has become faster and the processing functions have become more diverse. It is being promoted extremely rapidly.

このため、回路密度を非常に高くすることができる多層
セラミック基板が採用され、更に、主としてその処理速
度の高速化を図るため、多層セラミック基板の表面に1
層あるいは複数層の導体パターン層及び絶縁層を形成
し、その表面導体パターン層に表面実装部品を実装する
技術が開発されている。
For this reason, a multi-layer ceramic substrate that can make the circuit density extremely high is adopted. Furthermore, in order to increase the processing speed, mainly, a multi-layer ceramic substrate is formed on the surface of the multi-layer ceramic substrate.
A technique has been developed in which a layer or a plurality of layers of conductor pattern layers and insulating layers are formed, and surface-mounted components are mounted on the surface conductor pattern layers.

この段階では、多層セラミック基板の表面に例えばスパ
ッタリング、真空蒸着等の薄膜形成方法によって形成す
る1層あるいは複数層の導体パターン層及び絶縁層(以
下、多層セラミック基板の表面に形成されるこれらの層
を総称して表面薄膜層という)を形成する上で、多層セ
ラミック基板の表面の平面度及び平滑度が問題とされ
た。
At this stage, one or more conductor pattern layers and insulating layers (hereinafter, these layers formed on the surface of the multilayer ceramic substrate are formed on the surface of the multilayer ceramic substrate by a thin film forming method such as sputtering or vacuum deposition. Is collectively referred to as a surface thin film layer), the flatness and smoothness of the surface of the multilayer ceramic substrate have been problems.

即ち、セラミック基板では、焼成工程において基板に反
りやうねりが発生すること、その表面が比較的粗荒であ
ることが、表面薄膜層をセラミック基板の全面にわたっ
て均一形成する上で障害となることが経験された。
That is, in a ceramic substrate, warpage or undulation occurs in the firing process and the surface thereof is relatively rough, which may be an obstacle to forming the surface thin film layer uniformly over the entire surface of the ceramic substrate. Was experienced.

この問題は、所要の導体パターンを形成した1群のグリ
ーンシートからなるパターン層の表面側と裏面側とに、
パターン層の表面あるいは裏面の導体パターンを表面薄
膜層の導体パターンに接続するビア導体を埋設したそれ
ぞれ別の1群のグリーンシートからなる研磨層を積層
し、焼成後に、各研磨層を例えばラップ盤を使用して研
磨する、という方法で解決されている。
This problem is caused on the front surface side and the back surface side of the pattern layer formed of a group of green sheets on which a required conductor pattern is formed,
A polishing layer made of a group of different green sheets in which via conductors for connecting the conductor pattern on the front surface or the back surface of the pattern layer to the conductor pattern of the surface thin film layer are embedded is laminated, and after firing, each polishing layer is lapped, for example. It is solved by the method of polishing using.

積層される研磨層の厚さは経験的に決定され、従って研
磨層として積層されるグリーンシートの層数も経験的に
決定されている。例えば1片の長さが360mm程度で、仕
上がり板厚が14mm程度の多層セラミック基板を製造する
場合にはパターン層の表面側に19層、裏面側に17層のグ
リーンシートをそれぞれ積層している。
The thickness of the polishing layer to be laminated is empirically determined, and therefore the number of layers of the green sheet to be laminated as the polishing layer is also empirically determined. For example, in the case of manufacturing a multilayer ceramic substrate having a length of about 360 mm and a finished thickness of about 14 mm, 19 layers of green sheets are laminated on the front side of the pattern layer and 17 layers of green sheets are laminated on the back side. .

ところで、更に、電子計算機の処理速度の高速化と多機
能化を図るためには、基板密度の高密度化を図るという
対策が採用されている。そして、基板密度を高密度化す
る際に特に問題とされたのが、高密度に組み込まれた基
板をいかにして効率良く冷却するか、という問題であ
る。この基板冷却方法として近年脚光を浴びるようにな
ったのが水、揮発性液体等を冷媒として使用する冷媒冷
却方式である。
By the way, in order to further increase the processing speed and multifunction of the electronic computer, a measure for increasing the substrate density is adopted. A particularly problematic issue in increasing the substrate density is how to efficiently cool the substrates assembled in high density. As a method of cooling the substrate, a coolant cooling method that uses water, a volatile liquid, or the like as a coolant has recently come into the limelight.

この冷媒冷却方式の中でも代表的である水冷方式は、例
えば第3図に示すように、多層セラミック基板101をパ
ッケージ102内に収納し、パッケージ102の一側から冷却
伝達用ピストン103を多層セラミック基板101の表面実装
部品104に接触させ、前記ピストン103内に循環された水
(冷媒)に表面実装部品104の発熱を吸収させてパッケ
ージ102の外部に運び出すように構成している。
A water-cooling method, which is typical among the refrigerant cooling methods, stores a multilayer ceramic substrate 101 in a package 102, for example, as shown in FIG. 3, and installs a cooling transmission piston 103 from one side of the package 102 to the multilayer ceramic substrate. The water (refrigerant) circulated in the piston 103 is brought into contact with the surface mount component 104, and the heat generated by the surface mount component 104 is absorbed to be carried out of the package 102.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

ところで、従来の多層セラミック基板の製造方法におい
ては、セラミック基板の表裏両面を研磨することによっ
て、表裏両面をそれぞれ平坦で平滑に形成することはで
きるが、表裏両面の平行度及びセラミック基板の板厚に
ついては全く顧慮されていなかった。
By the way, in the conventional method for manufacturing a multilayer ceramic substrate, both front and back surfaces can be formed flat and smooth by polishing the front and back surfaces of the ceramic substrate. Was not considered at all.

このため、従来の多層セラミック基板を第3図に示すよ
うなパッケージ102に封入した時に、ピストン103が表面
実装部品104に接触できず、表面実装部品104が冷却でき
なくなったり、ピストン103が表面実装部品104に強く押
しつけられ、表面実装部品104が破損したりすることが
あった。
Therefore, when the conventional multilayer ceramic substrate is enclosed in the package 102 as shown in FIG. 3, the piston 103 cannot contact the surface mount component 104, the surface mount component 104 cannot be cooled, or the piston 103 is surface mount. There was a case where the surface mount component 104 was damaged by being strongly pressed against the component 104.

そこで、従来よりも研磨層を分厚くして、セラミック基
板の研磨時に表裏両面の平面度及び平滑度を高めるのみ
ならず、平行度と板厚寸法精度とを高めることを試みた
のであるが、研磨層をかなり分厚くした場合でもパター
ン層を研磨して損傷させることが少なからずあった。
Therefore, it was attempted not only to increase the flatness and smoothness of the front and back surfaces at the time of polishing the ceramic substrate by increasing the thickness of the polishing layer, but also to improve the parallelism and the plate thickness dimensional accuracy. Even if the layer was made quite thick, it was not uncommon for the patterned layer to be damaged by polishing.

即ち、パターン層が研磨されないようにするためには、
セラミック基板101のどの位置にパターン層があるかを
確認する必要があるが、このためには、従来では、セラ
ミック基板101を切断してその断面を調べる、という方
法しかなく、以後に使用が予定されている研磨中のセラ
ミック基板101のどの位置にパターン層があるかを確認
することはできない。その結果、片面側で磨耗量が過剰
となり、パターン層の内層導体パターンが研磨されて破
壊されるという失敗が頻発していたのである。
That is, in order to prevent the pattern layer from being polished,
It is necessary to confirm at which position on the ceramic substrate 101 the pattern layer is located.For this purpose, conventionally, there is only a method of cutting the ceramic substrate 101 and examining its cross section, which is to be used later. It is not possible to confirm at which position of the ceramic substrate 101 being polished the pattern layer is located. As a result, the amount of wear was excessive on one side, and the inner layer conductor pattern of the pattern layer was frequently polished and destroyed, resulting in frequent failures.

研磨層の厚さを経験的に決定している従来の多層セラミ
ック基板の製造方法では、このような失敗を防止するた
めには、結局、表裏両面に積層する研磨層のグリーンシ
ートの層数を多めに決定せざるを得ず、全体としての研
磨量が多くなって研磨時間が非常に長くなる。しかも、
研磨層を分厚くしても研磨時のパターン層の損傷を確実
に防止できるという保証をえることができなかった。
In the conventional method for manufacturing a multilayer ceramic substrate in which the thickness of the polishing layer is empirically determined, in order to prevent such a failure, the number of green sheets of the polishing layer to be laminated on the front and back surfaces is ultimately determined. Inevitably, the amount of polishing as a whole increases and the polishing time becomes extremely long. Moreover,
Even if the polishing layer is thickened, it cannot be guaranteed that the pattern layer can be reliably prevented from being damaged during polishing.

本発明は、上記の事情を鑑みてなされたものであり、板
厚寸法が大きく、かつ、面積が大きい多層セラミック基
板においても、その全面にわたって精密な平面度調整、
平行度調整及び板厚調整が必要最小限の研磨によって行
え、しかも、研磨によるパターン層の損傷を確実に防止
できるようにした、多層セラミック基板の製造方法を提
供することを目的とする。
The present invention has been made in view of the above circumstances, and has a large plate thickness dimension, and even in a multilayer ceramic substrate having a large area, precise flatness adjustment over the entire surface,
It is an object of the present invention to provide a method for manufacturing a multilayer ceramic substrate, in which the parallelism adjustment and the plate thickness adjustment can be performed by the minimum necessary polishing, and further, the damage of the pattern layer due to the polishing can be surely prevented.

〔課題を解決するための手段〕[Means for Solving the Problems]

本発明は、例えば第1図に示すように、所要の導体パタ
ーンを形成した1群のパターン層2の表面側と裏面側と
にそれぞれ1群の研磨層3a・3bを積層する多層セラミッ
ク基板の製造方法において、上記の目的を達成するた
め、次のような手段を講じている。
For example, as shown in FIG. 1, the present invention provides a multilayer ceramic substrate in which a group of polishing layers 3a and 3b are laminated on the front surface side and the back surface side of a group of pattern layers 2 on which a required conductor pattern is formed. In the manufacturing method, the following measures are taken to achieve the above object.

即ち、表裏の各研磨層3a・3bのうちの一方に厚さ調整代
32積層するとともに、表裏の各研磨層3a・3bに平行度調
整代33a・33bと、平面度調整代34a・34bとを積層し、か
つ、各研磨層3a・3bを構成するグリーンシートGSにその
積層順位を表示する表示手段mを設けた後、各研磨層3a
・3bのグリーンシートGSをその積層順位に従って順に積
層する、という手段を講じている。
That is, one of the front and back polishing layers 3a and 3b has a thickness adjustment allowance.
Along with 32 layers, the parallelism adjustment allowances 33a and 33b and the flatness adjustment allowances 34a and 34b are laminated on each of the front and back polishing layers 3a and 3b, and the green sheet GS that constitutes each polishing layer 3a and 3b is formed. After providing the display means m for displaying the stacking order, each polishing layer 3a
・ Measures are taken to sequentially stack the 3b green sheets GS according to their stacking order.

〔作用〕[Action]

積層されたパターン層2及び両研磨層3a・3bは加熱加圧
されて互いに圧着された後、焼成されてセラミック基板
1となる。焼成されたセラミック基板1は例えばガラス
で作られたパレットに接着されて表面側から研磨され
る。そして、表面側の平面度調整代34aをすべて研磨し
た時に一旦表面側の研磨が終了される。表面側の平面度
調整代34aを全て研磨したか否かは、研磨面にあるグリ
ーンシートGSあるいはその下側のグリーンシートGSの表
示手段mを見ることにより簡単に判定される。この研磨
によって、セラミック基板1の表面は所定の平面度と平
滑度とを有する平面に研磨される。
The laminated pattern layer 2 and both polishing layers 3a and 3b are heated and pressed to be pressure-bonded to each other, and then fired to form the ceramic substrate 1. The fired ceramic substrate 1 is adhered to a pallet made of, for example, glass and polished from the surface side. Then, when all of the flatness adjustment allowance 34a on the front surface side has been polished, the front surface side polishing is temporarily terminated. Whether or not all the flatness adjustment allowances 34a on the front surface side have been polished is easily determined by looking at the display means m of the green sheet GS on the polished surface or the green sheet GS below it. By this polishing, the surface of the ceramic substrate 1 is polished into a flat surface having a predetermined flatness and smoothness.

この後、セラミック基板1をパレットから剥がし、反転
させて再び接着した後、同様にして裏面側の平面度調整
代34bと平行度調整代33bとを研磨する。この場合、研磨
面にあるグリーンシートGSあるいはその下側のグリーン
シートGSの表示手段mを見ることにより、研磨がパター
ン層2あるいは裏側に厚さが調整代がある場合には厚さ
調整代32と平行度調整代33bとの境界に達しているか否
かが判定され、研磨がパターン層2あるいは厚さ調整代
32に達する直前に研磨を終了する。これにより、セラミ
ック基板1の裏面は所定の平面度と平滑度とを有する平
面に仕上げられ、かつ、表面に対する裏面の平行度が確
実に所定の基準値以上に高められる。また、研磨がパタ
ーン層2あるいは厚さ調整代32達する直前に研磨を終了
することにより、研磨が裏面側でパターン層2あるいは
厚さ調整代32まで進むことが防止される。
After that, the ceramic substrate 1 is peeled off from the pallet, inverted and adhered again, and then the flatness adjustment allowance 34b and the parallelism adjustment allowance 33b on the back side are similarly polished. In this case, by looking at the display means m of the green sheet GS on the polishing surface or the green sheet GS below it, when the polishing has a thickness adjustment allowance on the pattern layer 2 or the back side, a thickness adjustment allowance 32 And the parallelism adjustment allowance 33b has been reached, it is judged whether polishing has reached the pattern layer 2 or the thickness adjustment allowance.
Immediately before reaching 32, polishing is completed. As a result, the back surface of the ceramic substrate 1 is finished into a flat surface having a predetermined flatness and smoothness, and the parallelism of the back surface with respect to the front surface is reliably increased to a predetermined reference value or higher. Further, by stopping the polishing immediately before reaching the pattern layer 2 or the thickness adjustment allowance 32, it is possible to prevent the polishing from proceeding to the pattern layer 2 or the thickness adjustment allowance 32 on the back surface side.

更にこの後、セラミック基板1をパレットから剥がし、
再反転させて再び接着した後、表面側の研磨を開始し、
表面側の平行度調整代33aを研磨する。この研磨も、研
磨面にあるグリーンシートGSあるいはその下側のグリー
ンシートGSの表示手段mを見ることにより、研磨がパタ
ーン層2あるいは厚さ調整代32と平行度調整代33aとの
境界に達しているか否かが判定され、研磨がパターン層
2あるいは厚さ調整代32に達する直前に研磨を終了す
る。これにより、セラミック基板1の表裏両面はそれぞ
れ所定の平面度と平滑度に仕上げられ、かつ、表裏両面
の平行度が確実に所定の精度以上になるように仕上げら
れ、また、研磨が表面側でパターン層2あるいは厚さ調
整代32まで進むことが防止される。
Further after this, the ceramic substrate 1 is peeled off from the pallet,
After re-inverting and adhering again, start polishing the surface side,
The surface side parallelism adjustment allowance 33a is polished. In this polishing as well, the polishing reaches the boundary between the pattern layer 2 or the thickness adjustment margin 32 and the parallelism adjustment margin 33a by looking at the display means m of the green sheet GS on the polishing surface or the green sheet GS below it. It is determined whether or not the polishing is performed, and the polishing is finished immediately before the polishing reaches the pattern layer 2 or the thickness adjustment allowance 32. As a result, both the front and back surfaces of the ceramic substrate 1 are finished to have a predetermined flatness and smoothness, respectively, and the parallelism of the front and back surfaces is ensured to be equal to or higher than a predetermined accuracy, and polishing is performed on the front surface side. It is prevented that the pattern layer 2 or the thickness adjustment allowance 32 is reached.

最後に厚さ調整代32を積層した面をパターン層2が研磨
面に現れる直前までの範囲内で研磨して、板厚を所定値
に調整する。
Finally, the surface on which the thickness adjustment margin 32 is laminated is polished within a range until just before the pattern layer 2 appears on the polished surface, and the plate thickness is adjusted to a predetermined value.

かくして、パターン層2を研磨させることなく、表裏両
面が平坦で平滑で、互いに平行に仕上げられ、しかも、
全面にわたって所定の板厚を有するセラミック基板を得
ることができる。
Thus, the front and back surfaces are flat and smooth without polishing the pattern layer 2 and finished parallel to each other.
It is possible to obtain a ceramic substrate having a predetermined plate thickness over the entire surface.

なお、研磨の終了後に研磨面にあるグリーンシートGSあ
るいはその下側のグリーンシートGSの表示手段mを見る
ことにより、研磨がパターン層2と厚さ調整代32との境
界を越えているか否かを判定することができる。
After finishing the polishing, by looking at the display means m of the green sheet GS on the polishing surface or the green sheet GS below it, it is determined whether the polishing exceeds the boundary between the pattern layer 2 and the thickness adjustment allowance 32. Can be determined.

〔実施例〕〔Example〕

以下、本発明の実施例を図面に基づき説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図に示すように、本発明の一実施例に係る多層セラ
ミック基板の製造方法においては、所要の導体パターン
を形成した多数(例えば約70枚)のグリーンシートGSを
所定の順に積層したパターン層2を、それぞれ別の群を
なす2群の研磨層3a・3bの間にサンドイッチ状に積層す
る。そして、この積層体を焼成した後、所定の位置で切
断して一辺が約360mmの板状に形成し、研磨して、所定
の板厚、例えば14mmに調整される。
As shown in FIG. 1, in the method for manufacturing a multilayer ceramic substrate according to one embodiment of the present invention, a pattern in which a large number (for example, about 70 sheets) of green sheets GS on which required conductor patterns are formed are laminated in a predetermined order. Layer 2 is laminated in a sandwich form between two groups of polishing layers 3a, 3b, each group being a separate group. Then, after firing this laminated body, it is cut at a predetermined position to form a plate shape having a side of about 360 mm, and polished to be adjusted to a predetermined plate thickness, for example, 14 mm.

積層工程においては、まず、再研磨代31a・31bを構成す
るグリーンシートGSがパターン層2の表裏両面に積層さ
れる。
In the laminating step, first, the green sheets GS forming the re-polishing margins 31a and 31b are laminated on both front and back surfaces of the pattern layer 2.

この再研磨代31a・31bは、後の薄膜形成工程でセラミッ
ク基板1の表面への導体パターンの形成不良が発生した
り、薄膜形成工程以降の工程でセラミック基板1の表面
に形成された表面導体パターンが損傷した場合に、不良
が生じた表面薄膜層とともにセラミック基板1の表面あ
るいは裏面を、例えば0.1mm程度の極薄い厚さに再研磨
して、セラミック基板1及び損傷のない表面薄膜層を再
使用できるようにするために設けられる。各再研磨代31
a・31bの厚さは、最終的に許容される板厚誤差の範囲
(例えば±0.5mm)内に限定されている。各再研磨代31a
・31bを構成するグリーンシートGSの層数は、再研磨代3
1a・31bの厚さを焼成時にグリーンシートGSが厚さ方向
に収縮する割合、即ち、焼成収縮率(ここでは、約3/
2)で除算し、更に、1層のグリーンシートGSの厚さで
除して得られ、例えば、各再研磨代31a・31bの厚さを0.
5mmとし、グリーンシートGSの焼成前の厚さを約0.3mmと
する場合には2.5層(図上は2層)とされる。
The re-polishing allowances 31a and 31b are used for the surface conductor formed on the surface of the ceramic substrate 1 in the subsequent thin film forming step or in the formation of a conductive pattern on the surface of the ceramic substrate 1 or in the steps after the thin film forming step. When the pattern is damaged, the front surface or the back surface of the ceramic substrate 1 is re-polished to an extremely thin thickness of, for example, about 0.1 mm together with the defective surface thin film layer to remove the ceramic substrate 1 and the undamaged surface thin film layer. It is provided so that it can be reused. Each repolishing fee 31
The thickness of a and 31b is limited within the range of the plate thickness error that is finally allowed (for example, ± 0.5 mm). Each repolishing fee 31a
・ The number of layers of green sheet GS that composes 31b is 3 regrinding allowances.
The rate at which the green sheet GS shrinks in the thickness direction when firing the thickness of 1a and 31b, that is, the firing shrinkage rate (here, about 3 /
It is obtained by dividing by 2) and further dividing by the thickness of one layer of green sheet GS. For example, the thickness of each re-polishing margin 31a and 31b is 0.
When the thickness of the green sheet GS is 5 mm and the thickness of the green sheet GS is about 0.3 mm, the number of layers is 2.5 (two layers in the figure).

ここで、グリーンシートGSの層数は整数とする必要はな
く、後に厚さ調整代32、平行度調整代33a・33bあるいは
平面度調整代34a・34bとして積層されるグリーンシート
GSとの合計層数が整数となればよい。
Here, the number of layers of the green sheet GS does not have to be an integer, and the green sheet to be laminated later as the thickness adjustment allowance 32, the parallelism adjustment allowances 33a and 33b or the flatness adjustment allowances 34a and 34b.
The total number of layers with GS should be an integer.

前記パターン層2の厚さは積層されるグリーンシートGS
の厚さと層数とによって決定され、例えば厚さ約0.3mm
のグリーンシートGSを70層積層すれば、パターン層1の
厚さは約21mmとなる。このパターン層1の場合には、焼
成後にその厚さが約14mm程度に収縮することが経験され
ている。しかし、このパターン層1の焼成時の収縮量
は、形成された導体パターンの面積、膜厚、平面形状、
分布状態等によって異なり、実際には焼成後の仕上がり
板厚である14mmに対して±1mm程度の焼成寸法誤差が生
じることが知られている。
The thickness of the pattern layer 2 is the green sheet GS to be laminated.
Is determined by the thickness and the number of layers, for example, the thickness is about 0.3 mm
If 70 layers of the green sheets GS are laminated, the thickness of the pattern layer 1 becomes about 21 mm. In the case of this pattern layer 1, it has been experienced that the thickness thereof shrinks to about 14 mm after firing. However, the shrinkage amount of the pattern layer 1 during firing depends on the area, film thickness, plane shape of the formed conductor pattern,
It is known that, depending on the distribution state, etc., in reality, there is a dimensional error of approximately ± 1 mm with respect to the finished plate thickness of 14 mm after firing.

そこで、この寸法誤差を調整するため、更に厚さ調整代
32を構成するグリーンシートGSを再研磨代31aの積層す
る。
Therefore, in order to adjust this dimensional error, the thickness adjustment
The green sheets GS forming 32 are laminated with the re-polishing margin 31a.

厚さ調整代32の厚さは、上記の焼成寸法誤差を焼成収縮
率で除算すればよく、厚さ調整代32を構成するグリーン
シートGSの層数は、更にこれをグリーンシートGSの厚さ
で除算すればよい。
The thickness of the thickness adjustment allowance 32 may be obtained by dividing the above firing dimensional error by the firing shrinkage ratio, and the number of layers of the green sheet GS constituting the thickness adjustment allowance 32 is further calculated as the thickness of the green sheet GS. Divide by.

この実施例では、グリーンシートGSの厚さが0.3mmであ
るので、厚さ調整代32を構成するグリーンシートGSの層
数は5層とされる。
In this embodiment, since the thickness of the green sheet GS is 0.3 mm, the number of layers of the green sheet GS forming the thickness adjustment allowance 32 is five.

更に、これらパターン層1、両面の再研磨代31a・31b及
び厚さ調整代32の積層体を焼成した場合に、その両面が
所要の平面度と平滑度を有する表裏1対の平面を形成し
ていると仮定し、表裏両面の平行度を調整するため、表
裏各面に平行度調整代33a・33bを構成するグリーンシー
トGSが積層される。
Further, when the laminate of the pattern layer 1, the repolishing margins 31a and 31b on both sides and the thickness adjusting margin 32 is fired, both sides form a pair of front and back flat surfaces having required flatness and smoothness. In order to adjust the parallelism between the front and back surfaces, the green sheets GS forming the parallelism adjustment margins 33a and 33b are laminated on the front and back surfaces.

この場合には、経験的に±1mmの誤差が発生することが
確かめられているので、平行度調整代33a・33bの厚さは
片面で±0.5mm程度の誤差を解消できるように決定され
る。即ち、片面の平行度調整代33a・33bの厚さは0.5mm
を焼成収縮率で除した0.75mmとされ、そのグリーンシー
トGSの層数は2.5層(図上は3層)とされる。
In this case, it has been empirically confirmed that an error of ± 1 mm occurs, so the thickness of the parallelism adjustment margins 33a and 33b is determined so that an error of ± 0.5 mm can be eliminated on one side. . That is, the thickness of the parallelism adjustment margins 33a and 33b on one side is 0.5 mm.
Is divided by the firing shrinkage to be 0.75 mm, and the number of layers of the green sheet GS is 2.5 (three in the figure).

更に、これらの平行度調整代33a・33bに加え、各面のそ
り、うねり等の変形を解消するため、平面度調整代34a
・34bを構成するグリーンシートGSが積層される。
Furthermore, in addition to these parallelism adjustment allowances 33a and 33b, in order to eliminate deformation such as warpage and undulation of each surface, flatness adjustment allowance 34a
-The green sheets GS that compose 34b are stacked.

各平面度調整代34a・34bの厚さは、焼成に際して生じる
各面の反りやうねりの最大値を焼成収縮率で除して求め
ることができる。この実施例と同種のセラミック基板1
では基準平面に対して最大±3mmの反りやうねりが生じ
ることが確認されているので、ここでは、各平面度調整
代34a・34bの厚さは4.5mmとされ、各平面度調整代34a・
34bを構成するグリーンシートGSの層数は15層とされ
る。
The thickness of each flatness adjustment allowance 34a / 34b can be obtained by dividing the maximum value of the warpage or waviness of each surface generated during firing by the firing shrinkage rate. Ceramic substrate 1 of the same kind as this embodiment
Since it has been confirmed that a maximum of ± 3 mm of warpage or undulation with respect to the reference plane occurs, the thickness of each flatness adjustment allowance 34a ・ 34b is 4.5 mm, and each flatness adjustment allowance 34a ・ 34a ・
The number of layers of the green sheet GS constituting 34b is 15 layers.

結局、この実施例では、パターン層2の上側に25層のグ
リーンシートGSが積層され、下側には20層のグリーンシ
ートGSが積層される。
After all, in this embodiment, 25 layers of green sheets GS are laminated on the upper side of the pattern layer 2 and 20 layers of green sheets GS are laminated on the lower side thereof.

そして、各グリーンシートGSには、第2図に示すよう
に、次のグリーンシートGSを積層する前に、パターン層
2のパターン形成エリア外(このエリア内であってもよ
い)の所定の4箇所に対応する箇所、即ち、各グリーン
シートGSのコーナー部にそのグリーンシートとGSの積層
順位を示す数字mが付される。
Then, as shown in FIG. 2, each green sheet GS has a predetermined area outside the pattern formation area of the pattern layer 2 (may be within this area) before the next green sheet GS is laminated. A number m indicating the stacking order of the green sheet and GS is attached to a portion corresponding to the portion, that is, a corner portion of each green sheet GS.

この数字mの形成方法は特に限定されず、印刷、打抜
き、型押し等の手法が用いられる。ここでは、特に工程
数の増加を避けるとともに、コストダウンを図れるよう
にするため、例えば各グリーンシートGSのビアホールの
一端に金属ペーストを印刷するのと同時にその金属ペー
ストで印刷することにより、数字mが形成されている。
The method of forming the number m is not particularly limited, and a method such as printing, punching, or embossing is used. Here, in order to avoid an increase in the number of steps and to reduce the cost, for example, by printing the metal paste on one end of the via hole of each green sheet GS at the same time as printing the metal paste, the number m Are formed.

なお、この数字mに替えて、プロットマーク、バーコー
ドマーク等をグリーンシートGSに設けてもよい。
Instead of the number m, plot marks, bar code marks, etc. may be provided on the green sheet GS.

この多層セラミック基板の製造方法においては、このよ
うにして、パターン層2の両側に研磨層3a・3bとして必
要最小限の厚さにわたってグリーンシートGSが積層され
ることになる。そして、このようにして作った積層体
は、この後、パターン層2及びこれの両側に積層した研
磨層3a・3bのグリーンシートGSを加熱加圧して互いに圧
着させ、焼成させてセラミック基板1を形成し、更に、
表裏両面に薄膜導体パターン層を形成するために研磨工
程に持ち込まれる。
In this method for manufacturing a multilayer ceramic substrate, the green sheets GS are laminated on both sides of the pattern layer 2 as the polishing layers 3a and 3b in the minimum necessary thickness in this manner. Then, in the laminated body thus manufactured, the green sheets GS of the pattern layer 2 and the polishing layers 3a and 3b laminated on both sides of the pattern layer 2 are heated and pressed to be pressure-bonded to each other and fired to form the ceramic substrate 1. To form,
It is brought into a polishing process to form thin film conductor pattern layers on both front and back surfaces.

研磨工程においては、まず、例えば表面側の研磨層3aの
平面度調整代34aを研磨する。
In the polishing step, first, for example, the flatness adjustment allowance 34a of the polishing layer 3a on the front surface side is polished.

この研磨の途中の任意の時点において、セラミック基板
1の研磨面にあるグリーンシートGSの数字m(あるいは
その下側のグリーンシートGSの数字m)を一目見ること
により、その時点で研磨中のグリーンシートGSが平面度
調整代34aのもであるか否かを簡単に判断することがで
きる。そして、平面度調整代34aの最後の層のグリーン
シートGSの研磨の終了時あるいはその前後に、研磨層3a
の研磨を一端停止する。
At any point during this polishing, by looking at the number m of the green sheet GS (or the number m of the green sheet GS below it) on the polished surface of the ceramic substrate 1, the green being polished at that time can be seen. It is possible to easily determine whether or not the sheet GS is also the flatness adjustment allowance 34a. Then, at the end of or before or after the polishing of the green sheet GS of the last layer of the flatness adjustment allowance 34a, the polishing layer 3a
The polishing of is once stopped.

この後、セラミック基板1を反転させて反対側の研磨層
3bの平面度調整代34bを研磨する。また、これに引き続
いて、この研磨層3bの研磨面が最初に研磨した研磨層3a
の研磨面と平行になるように、平行度調整代33bの厚さ
を研磨する。平行度調整代33bがどの層まで研磨された
かをグリーンシートGSの数字mから判定し、再研磨代31
bが研磨面に現れる直前に裏面側の研磨を停止してセラ
ミック基板1を再反転させる。そして、片面側の平行度
調整代33aと厚さ調整代32とにわたって、その片面(上
面)が反対側の面(下面)に平行で、かつ、セラミック
基板1の板厚が所定の仕上がり寸法の最大値となるまで
研磨する。
After that, the ceramic substrate 1 is turned over and the polishing layer on the other side is reversed.
The flatness adjustment allowance 34b of 3b is polished. In addition, subsequently to this, the polishing surface of the polishing layer 3b is the polishing layer 3a which is first polished.
The thickness of the parallelism adjusting margin 33b is polished so as to be parallel to the polishing surface of. It is judged from the number m on the green sheet GS which layer the parallelism adjustment allowance 33b has been polished, and the re-polishing allowance 31
Immediately before b appears on the polished surface, polishing of the back surface side is stopped and the ceramic substrate 1 is re-inverted. Then, one surface (upper surface) of the parallelism adjustment allowance 33a and the thickness adjustment allowance 32 on the one surface side is parallel to the opposite surface (lower surface), and the plate thickness of the ceramic substrate 1 has a predetermined finish dimension. Polish until the maximum value is reached.

このようにして、研磨層3a・3bを無駄に分厚く研磨する
ことなく、セラミック基板1の板厚の寸法誤差、各面の
平面度及び両面の平行度を水冷用のピストン103の伸縮
幅の±0.5mm程度よりも、はるかに小さい±0.2mm程度以
下にすることができた。
In this way, the dimensional error of the plate thickness of the ceramic substrate 1, the flatness of each surface, and the parallelism of both surfaces can be adjusted within ± the expansion and contraction width of the water-cooling piston 103 without wastefully polishing the polishing layers 3a and 3b. It was possible to make it much smaller than about 0.5 mm and below ± 0.2 mm.

要するに、この多層セラミック基板の製造方法によれ
ば、表裏両面が平坦で、平滑で、かつ、互いに平行に仕
上げられるとともに、板厚が高精度に調整される。その
結果、水冷冷却方式等の冷媒冷却方式のパッケージ1012
に組み込んだ時に、表面に実装された表面実装部品104
に冷却用のピストン103を適切な接触圧で接触させて確
実に冷却させることができ、表面実装部品104の冷却不
足や破損を防止できることになる。
In short, according to this method for manufacturing a multilayer ceramic substrate, both front and back surfaces are finished flat, smooth, and parallel to each other, and the plate thickness is adjusted with high accuracy. As a result, refrigerant cooling package 1012 such as water cooling
Surface mount component 104 mounted on the surface when assembled into
The cooling piston 103 can be contacted with an appropriate contact pressure for reliable cooling, and insufficient cooling or damage to the surface-mounted component 104 can be prevented.

また、研磨層3a・3bの厚さが必要最小限に決定されてい
るので、研磨時間を必要最小限に短くすることができ
る。
Moreover, since the thickness of the polishing layers 3a and 3b is determined to be the minimum necessary, the polishing time can be shortened to the minimum necessary.

なお、グリーンシートGSは積層時の加圧によって中央部
で分厚くなり、セラミック基板1の中央部では周囲部よ
りもパターン層2に近いグリーンシートGSが研磨される
ことになる。しかしながら、この場合には、第2図に示
すように、中央部側で露出していグリーンシートGSとそ
の外側で露出しているグリーンシートGSとの境界線B1・
B2で研磨剤の付着状態が変化し、その境界線B1・B2が木
の年輪のように同心状に見えるので、この境界線B1・B2
の数とグリーンシートGSに付された数字mから露出して
いる最もパターン層2に近いグリーンシートGSの積層順
位を簡単に判定することができる。従って、パターン層
2が研磨される前に研磨を止めることにより、セラミッ
ク基板1の片面のみを過剰研磨することが確実に防止さ
れ、パターン層2の導体パターン破壊による不良品の発
生を確実に防止することができる。
The green sheet GS becomes thicker in the central portion due to the pressure applied during lamination, and the green sheet GS closer to the pattern layer 2 than the peripheral portion is polished in the central portion of the ceramic substrate 1. However, in this case, as shown in FIG. 2, the boundary line B1 between the green sheet GS exposed on the central side and the green sheet GS exposed on the outside thereof is
Since the adhesion state of the abrasive changes at B2 and the boundary lines B1 and B2 look concentric like tree rings, these boundary lines B1 and B2
It is possible to easily determine the stacking order of the green sheet GS closest to the pattern layer 2 that is exposed from the number of the green sheets and the number m attached to the green sheet GS. Therefore, by stopping the polishing before the pattern layer 2 is polished, it is possible to surely prevent excessive polishing of only one surface of the ceramic substrate 1, and it is possible to surely prevent generation of defective products due to destruction of the conductor pattern of the pattern layer 2. can do.

また、この多層セラミック基板の製造方法によれば、再
研磨層31a・31bを積層しているので、後にセラミック基
板1の表面に形成される薄膜導体パターン層の形成不良
や損傷が生じた時に不良の表面薄膜層と共に再研磨層31
a・31bを研磨することにより、セラミック基板1及び良
好な表面薄膜を廃却処分から救うことができる。なお、
再研磨に際しても、グリーンシートGSに設けた数字mを
見て再研磨できるか、廃却すべきかを判定することがで
きる。
Further, according to this method for manufacturing a multilayer ceramic substrate, since the re-polishing layers 31a and 31b are laminated, the thin film conductor pattern layer formed later on the surface of the ceramic substrate 1 is defective when it is formed or damaged. Re-polishing layer 31 with the surface thin film layer of
By polishing a / 31b, the ceramic substrate 1 and a good surface thin film can be saved from disposal. In addition,
Also in the case of re-polishing, it is possible to judge whether the re-polishing can be done or the scrap should be discarded by looking at the number m provided on the green sheet GS.

〔発明の効果〕〔The invention's effect〕

以上に説明したように、本発明によれば、セラミック基
板の研磨層に、表裏両面の平面度及び平滑度を調整する
ための平面度調整代の他に、表裏両面の平行度を調整す
るための平行度調整代と、厚さ調整代とを設けるので、
これらを積層順と逆の順で研磨することにより、高精度
に表裏両面の平面度調整、平行度調整および板厚寸法調
整を行うことができる。この結果、表面実装部品を実装
した後、セラミック基板を冷媒冷却方法のパッケージに
組み込んだ時に表面実装部品を冷却用ピストンに適当な
接触圧で接触させ効率良く冷却することができ、冷却不
足、冷却不能あるいは表面実装部品の損傷が発生するこ
とを防止できる。
As described above, according to the present invention, in the polishing layer of the ceramic substrate, in addition to the flatness adjustment allowance for adjusting the flatness and smoothness of the front and back surfaces, in order to adjust the parallelism of the front and back surfaces. Since the parallelism adjustment allowance and the thickness adjustment allowance are provided,
By polishing these in the order opposite to the stacking order, it is possible to highly accurately adjust the flatness of both the front and back surfaces, the parallelism, and the plate thickness dimension. As a result, after mounting the surface mount component, when the ceramic substrate is installed in the package of the refrigerant cooling method, the surface mount component can be brought into contact with the cooling piston with an appropriate contact pressure for efficient cooling, resulting in insufficient cooling and cooling. Impossible or damage to the surface mount component can be prevented.

また、厚さ調整代、平行度調整代及び平面度調整代の厚
さを厚さ調整、平行度調整あるいは平面度調整というそ
れぞれの目的を達成するために必要最小限の厚さに設定
することができるので、研磨時間を必要最小限に短縮す
ることができる。
In addition, the thickness of the thickness adjustment allowance, parallelism adjustment allowance, and flatness adjustment allowance should be set to the minimum necessary thickness to achieve the respective objectives of thickness adjustment, parallelism adjustment, or flatness adjustment. Therefore, the polishing time can be shortened to the necessary minimum.

更に、本発明によれば、研磨層として積層するグリーン
シートにその積層順位を表示する表示手段を設けた後、
各研磨層のグリーンシートをその積層順位に従って順に
積層するので、研磨時に研磨面上にあるグリーンシート
の表示手段あるいはその下側のグリーンシートの表示手
段を見て研磨中のグリーンシートの積層順位を簡単に判
別することができ、研磨がパターン層に到達する前に研
磨を停止してパターン層が損傷されることを確実に防止
できる。
Furthermore, according to the present invention, after providing a display means for displaying the stacking order on the green sheet to be stacked as the polishing layer,
Since the green sheets of each polishing layer are stacked in order according to the stacking order, the stacking order of the green sheets under polishing can be determined by looking at the display means of the green sheet on the polishing surface or the display means of the lower green sheet during polishing. It can be easily discriminated and it is possible to reliably prevent the pattern layer from being damaged by stopping the polishing before the polishing reaches the pattern layer.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例に係る多層セラミック基板の
製造方法の構成図であり、第2図は研磨中のセラミック
基板の平面図であり、第3図は多層セラミック基板の水
冷方式の構成図である。 図中、 1…セラミック基板、2…パターン層、3a…研磨層、3b
…研磨層、31a…再研磨代、31b…再研磨代、32…厚さ調
整代、33a…平行度調整代、33b…平行度調整代、34a…
平面度調整代、34a…平面度調整代、GS…グリーンシー
ト、m…数字。
FIG. 1 is a configuration diagram of a method for manufacturing a multilayer ceramic substrate according to an embodiment of the present invention, FIG. 2 is a plan view of the ceramic substrate being polished, and FIG. 3 is a water-cooling system for the multilayer ceramic substrate. It is a block diagram. In the figure, 1 ... Ceramic substrate, 2 ... Pattern layer, 3a ... Polishing layer, 3b
... polishing layer, 31a ... repolishing allowance, 31b ... repolishing allowance, 32 ... thickness adjustment allowance, 33a ... parallelism adjusting allowance, 33b ... parallelism adjusting allowance, 34a ...
Flatness adjustment allowance, 34a ... Flatness adjustment allowance, GS ... Green sheet, m ... Number.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】所要の導体パターンを形成した1群のグリ
ーンシート(GS)からなるパターン層(2)の表面側と
裏面側とにそれぞれ別の1群のグリーンシート(GS)か
らなる研磨層(3a)・(3b)を積層する多層セラミック
基板の製造方法において、表裏各研磨層(3a)・(3b)
のうちの一方に厚さ調整代(32)となるグリーンシート
(GS)を積層すると共に、表裏各研磨層(3a)・(3b)
に平行度調整代(33a)・(33b)となるグリーンシート
(GS)と、平面度調整代(34a)・(34b)となるグリー
ンシート(GS)とを積層し、かつ、表裏各研磨層(3a)
・(3b)に積層される各グリーンシート(GS)にはその
積層順位を表示する表示手段(m)を設け、各研磨層
(3a)・(3b)のグリーンシート(GS)をその積層順位
に従って順に積層することを特徴とする多層セラミック
基板の製造方法。
1. A polishing layer composed of a group of green sheets (GS), each of which is provided on the front surface side and the back surface side of a pattern layer (2) composed of a group of green sheets (GS) on which a required conductor pattern is formed. In the method for manufacturing a multilayer ceramic substrate in which (3a) and (3b) are laminated, front and back polishing layers (3a) and (3b)
A green sheet (GS) that serves as a thickness adjustment allowance (32) is laminated on one of the above, and each of the front and back polishing layers (3a) and (3b)
, A green sheet (GS) for adjusting the parallelism (33a) and (33b) and a green sheet (GS) for adjusting the flatness (34a) and (34b) are laminated, and each of the front and back polishing layers is laminated. (3a)
-Each green sheet (GS) stacked on (3b) is provided with a display means (m) for displaying the stacking order, and the green sheet (GS) of each polishing layer (3a) (3b) is stacked on the green sheet (GS). A method for manufacturing a multi-layer ceramic substrate, which comprises laminating the layers in order.
JP6889590A 1990-03-19 1990-03-19 Method for manufacturing multilayer ceramic substrate Expired - Fee Related JPH07105597B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6889590A JPH07105597B2 (en) 1990-03-19 1990-03-19 Method for manufacturing multilayer ceramic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6889590A JPH07105597B2 (en) 1990-03-19 1990-03-19 Method for manufacturing multilayer ceramic substrate

Publications (2)

Publication Number Publication Date
JPH03268482A JPH03268482A (en) 1991-11-29
JPH07105597B2 true JPH07105597B2 (en) 1995-11-13

Family

ID=13386848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6889590A Expired - Fee Related JPH07105597B2 (en) 1990-03-19 1990-03-19 Method for manufacturing multilayer ceramic substrate

Country Status (1)

Country Link
JP (1) JPH07105597B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5719624B2 (en) * 2011-02-15 2015-05-20 株式会社フジクラ Method for manufacturing printed wiring board

Also Published As

Publication number Publication date
JPH03268482A (en) 1991-11-29

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