JPH07105782B2 - Digital data smoothing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data smoothing circuit, and particularly when the phase relationship between a burst clock for writing and a continuous clock for reading is constant, it is relatively simple. The present invention relates to a circuit capable of smoothing digital data with various configurations.

[Conventional technology]

Conventionally, smoothing of digital data is performed using an elastic memory, and this memory is composed of a write sequential counter, a memory section read selection circuit, and a read sequential counter.

An address is given to the elastic memory by incrementing a write sequential counter by a burst clock, and a part of continuous data having a predetermined bit rate is written as burst data in the memory. For the data written in the memory, after the reading selection circuit selects reading of the data from the memory, the read sequential counter is incremented by a continuous clock of a predetermined frequency to give an address to the memory, and the continuous clock is supplied to the memory. Data is read synchronously. That is, burst data is smoothed into continuous data by writing the burst data in the memory in synchronization with the burst clock and then reading the data from the memory in synchronization with the continuous clock of a predetermined frequency.

[Problems to be solved by the invention]

However, in the above-described conventional digital data smoothing circuit, when the average frequencies of the burst clock for writing and the burst clock for reading match, it is difficult to match the phase of the write sequential counter and the read sequential counter. As a result, the circuit was complicated.

An object of the present invention is to solve such problems and to provide a digital data smoothing circuit capable of smoothing digital data with a relatively simple circuit configuration.

[Means for solving problems]

According to the present invention, in continuous N-bit digital data,
The digital data of M bits consecutive in digital data smoothing circuit that smoothes the data of the bit rate obtained by multiplying the M / N to f _n is the bit rate of data, the digital data of the bit rate f _n A first frequency divider circuit that divides a synchronized clock and outputs a predetermined signal only during a period corresponding to the continuous M-bit digital data; and a predetermined output signal of the first frequency divider circuit, A bursting circuit that outputs a clock synchronized with the digital data of the bit rate f _n as a burst clock only during a period corresponding to the continuous M bit digital data; and a bursting circuit that outputs the digital data of the bit rate f _n. The burst clock that is output shifts the captured data, and the captured data is transferred to the M A first shift register for outputting a capital of parallel data, a clock synchronized to the digital data of the bit rate f _n and divides and outputs a continuous clock bit rate is synchronized to the data of f _n × M / N A second frequency divider circuit, M flip-flops operating with the continuous clock, M-bit parallel data of the first shift register is given to a first input, and M number of the M number of parallel flip-flops of the first shift register are given to a second input. A selection circuit that receives the output of the flip-flop, selects one of the first and second inputs by the continuous clock, and uses the selected signal as the input of the M flip-flops; And a second shift register for outputting bit parallel data as serial data at the continuous clock.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the present embodiment, and FIG. 2 is a timing chart showing the time relationship of the signals of the respective parts. Bit rate f _n As an example, here, in the digital data of consecutive 5712 bits (N bits), the digital data of consecutive 17 bits (M bits), the bit rate f _n
The case of smoothing to the data of × 17/5712 will be described.

The frequency divider circuit 117 is used for the digital data 101 of the bit rate f _n.
The clock 102 that is synchronized with the clock is divided, and the clock 107 that becomes a logical “1” only during the period corresponding to continuous 17-bit digital data, the clock 109 that divides the clock 102 into 17/5712, and the rising of the clock 107. When it goes down, it becomes a logical "1"
The clock 108 that becomes logical "0" at the next falling edge of the clock 109 is output to the burst circuit 103, the selection circuit 111, and the shift register 112, which will be described later.

The burst circuit 103 uses the clock from the frequency dividing circuit 117.
The continuous clock 102 is output by 107 only during the period corresponding to continuous 17-bit digital data, and the continuous clock is used as the burst clock 106.

Flip-flop (F / F) 104 uses this burst clock
The data 101 is retimed by 106 and 17-bit burst data 105 synchronized with the burst clock 106 is output.

The shift register 110 is configured by connecting 17 flip-flops in series, shifts the burst data 105 from the flip-flop 104 in synchronization with a burst clock 106 output from the burst circuit 103, and fetches data.
Then, the captured data is output from each tap 116 as 17-bit parallel data.

The selection circuit 111 is composed of 17 selectors (SEL), and each selector outputs from the frequency divider circuit 117 a clock 1 of logic “1”.
When 08 is input, the data from the tap 116 is selected and output. On the other hand, when the clock 108 becomes a logical “0”, the data from each flip-flop that configures the shift register 112 described later is selected. And output.

The shift register 112 includes 17 flip-flops that receive and store the data 115 output by each selector of the selection circuit 111, and the tap 114 that is the output of the flip-flop is connected to one input of the selector.
Then, in synchronization with the clock 109 from the frequency dividing circuit 117, the data taken in by each flip-flop is shifted through the selector and output as serial data 113. The shift register 112 and the selection circuit 111 constitute one shift register that can input data in parallel.

Next, the operation will be described. The frequency divider circuit 117 changes the bit rate f
_When the clock 102 that is synchronized with the _n digital data 101 is divided and the clock 107 that becomes logical “1” is output only during the period corresponding to the continuous 17-bit digital data, the bursting circuit 103 continues with this clock 107. The clock is used only during the period corresponding to 17-bit digital data.
102 is output as the burst clock 106.

The flip-flop 104 retimes the data 101 by the burst clock 106 from the burst circuit 103,
The 17-bit burst data 105 synchronized with the burst clock 106 is output.

The shift register 110 shifts the burst data 105 from the flip-flop 104 in synchronization with the burst clock 106 to fetch the data, and outputs the fetched data as 17-bit parallel data from each tap 116.

At this time, the clock 108 from the frequency dividing circuit 117 has a logic "1", and therefore each selector of the selecting circuit 111 selects and outputs the data from the tap 116. Then, the shift register 112
The flip-flop receives the data from each selector and stores it.

Next, when the clock 108 becomes a logic "0", each selector of the selection circuit 111 selects and outputs the data from each flip-flop that constitutes the shift register 112. Then, the flip-flop of the shift register 112 shifts the data fetched by each flip-flop via each selector in synchronization with the clock 109 from the frequency dividing circuit 117, and outputs serial data 113.

In this way, in the digital data smoothing circuit of the present embodiment, the burst data 105 consisting of 17 pieces of data is smoothed into data having a bit rate of f _n × 17/5712 and output as serial data 113.

〔The invention's effect〕

As described above, the present invention has a bit rate data obtained by multiplying continuous M bit digital data in continuous N bit digital data by the bit rate f _n of these data by M / N. In a digital data smoothing circuit for smoothing to, a first frequency _dividing circuit which divides a clock synchronized with digital data of a bit rate f _n and outputs a predetermined signal only during a period corresponding to continuous M-bit digital data. And a burst circuit for outputting a clock synchronized with the digital data of the bit rate f _n as a burst clock only during a period corresponding to continuous M-bit digital data by the predetermined output signal of the first frequency _dividing circuit, de is shifted by the burst clock output burst circuit is digital data with a bit rate f _n Captures data, a first shift register which outputs the accepted data as M-bit parallel data, divides the clock synchronized to the digital data with a bit rate f _n, the bit rate of f _n × M / N data A second frequency divider circuit that outputs a continuous clock that is synchronized with
A second shift register that fetches M-bit parallel data output from the first shift register, shifts the data in synchronization with a continuous clock output from the second frequency divider, and outputs the fetched data as serial data It has and.

Therefore, according to the present invention, it is possible to realize a digital data smoothing circuit capable of smoothing digital data with a relatively simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing a time relationship of signals of respective parts in the embodiment of FIG. 103 …… Burst circuit 104 …… Flip-flop 110, 112 …… Shift register 111 …… Selection circuit 117 …… Dividing circuit

Claims (1)

[Claims] 1. Smoothing continuous M-bit digital data in continuous N-bit digital data into bit rate data obtained by multiplying the bit rate f _n of these data by M / N. A digital data smoothing circuit, which divides a clock synchronized with the digital data of the bit rate f _n and outputs a predetermined signal only during a period corresponding to the continuous M-bit digital data; A bursting circuit for outputting, as a burst clock, a clock synchronized with the digital data of the bit rate f _n only during a period corresponding to the continuous M-bit digital data by the predetermined output signal of the first frequency _dividing circuit; , the burst clock outputs digital data of the bit rate f _n is the burst circuit It is shifted by capturing data, a first shift register which outputs the accepted data as M-bit parallel data, divides the clock synchronized to the digital data of the bit rate f _n, the bit rate is f _n × M A second frequency divider circuit that outputs a continuous clock that is synchronized with the data of / N, M flip-flops that operate with the continuous clock, and M-bit parallel data of the first shift register at the first input. The output of the M flip-flops is provided to a second input, one of the first and second inputs is selected by the continuous clock, and the selected signal is output from the M flip-flops. A second shift register which has a selection circuit as an input and outputs the M-bit parallel data as serial data at the continuous clock. And a digital data smoothing circuit.