JPH07105802B2 - Signal transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention connects a central processing unit and a plurality of terminals with a pair of transmission lines, and an address signal and a control signal from the central processing unit to the terminals. The present invention relates to a signal transmission system for transmitting a transmission signal such as a voltage signal in a voltage mode and transmitting monitoring data from a terminal device to a central processing unit in a current mode. The present invention relates to a signal transmission system suitable for control.

[Prior Art] Conventionally, as a signal transmission system for remote control, a central processing unit and a plurality of terminals are connected by a pair of transmission lines, and the central processing unit sends the address signals and the control signals to the terminals. Short pulse and long pulse for supervisory signal are transmitted, and a series circuit of current limiting resistor and switch element is connected in parallel to the transmission line in each terminal device as appropriate to monitor during transmission of long pulse for supervisory signal. It is known that a switch element is opened / closed according to the contents and a change in current of a transmission line due to this opening / closing operation is detected by a central processing unit (Japanese Patent Publication No. 61-3155).

[Problems to be Solved by the Invention] By the way, when signal transmission from a terminal unit to a central processing unit is performed in a current mode in which a current sinked in the terminal unit is changed like this conventional signal transmission system, the central processing unit is used. Then, it is possible to detect the current by converting it into a voltage by a detection resistor or the like. However, since this signal current flows only between the source terminal unit and the central processing unit, the monitoring signal and the like cannot be detected at a position other than between the source terminal unit and the central processing unit.

Therefore, this conventional signal transmission system detects the monitoring signals of all the terminals when connecting the monitoring display panel that detects the monitoring signals sent from the terminals and displays the load status monitoring. However, this monitor display panel has to be connected to the preceding stage (closer to the central processing unit) than any terminal device, and the installation position of the monitor display panel is limited, which is not practical.

The central processing unit detects the current mode monitoring data from the terminal, converts it to a signal that controls the display on the monitoring display panel, and sends it to connect the monitoring display unit to any position on the transmission line. It can also be made possible.
However, in this case, there are inconveniences that the transmission speed is reduced by the time for controlling the monitor display panel and the load on the central processing unit is increased.

Further, in this conventional signal transmission system, each terminal device can detect only the signal of the terminal device in the later stage, and it is not possible for each terminal device to detect the signals of all the other terminal devices. For this reason, in this conventional signal transmission system, when the terminal device tries to activate it by random transmission (child activation), the activation terminal device determines whether or not there is a transmission signal from the terminal device in the preceding stage, that is, transmission. There is an inconvenience that it is not suitable for random transmission because it is not possible to discriminate line occupancy and activation collision.

Even in the case of parent activation (central activation), in order to confirm that the returned terminal device (slave device) has correctly received the returned data, the central processing unit (parent device) can receive an answer signal from the central processing unit. Therefore, there is a disadvantage that the transmission speed is reduced by this amount.

The present invention has been made in view of the above problems in the conventional example, and it is possible to connect the monitor display panel to an arbitrary position of the transmission line, realize suitable random transmission, and perform transmission. It is an object to provide a high-speed signal transmission system.

[Means for Solving the Problems] In order to achieve the above object, in the signal transmission system according to claim 1, a voltage mode transmission signal including control information and address information for specifying a control target is transmitted in a time division manner. Transmitting means for sending out via a wire, and current detecting means for detecting a change in a current mode transmission signal input via a transmission line,
And voltage inverting means for inverting the polarity of the transmission signal sent from the transmitting means when the current detecting means detects a change in the current mode transmission signal, and a central processing unit provided therewith; connected to the transmission line and transmitting in the current mode And a plurality of terminals for time-divisionally transmitting the signal to the central processing unit.

The invention according to claim 2 is characterized in that a display board is provided in addition to the signal transmission system according to claim 1.

According to the third aspect of the present invention, the voltage mode transmission signal including the control information, the address information for specifying the control target, the return request signal requesting the return signal from the control target, and the synchronization signal indicating the transmission timing of the return signal is transmitted. Transmitting means for dividing and transmitting through the transmission line, current detecting means for detecting a change in current mode return signal input through the transmission line, and current detecting means detected a change in current mode return signal A central processing unit provided with voltage inverting means for reacting the polarity of a transmission signal sent from the transmitting means; and a central processing unit connected to a transmission line and time-sharing a current mode return signal in response to a return request signal. And a plurality of terminals for sending to the terminal.

According to a fourth aspect of the present invention, in the signal transmission system according to the third aspect, when the voltage detecting means detects a change in the current mode return signal returned from the terminal device in synchronization with the synchronization signal, the voltage detection means detects the change from the synchronization signal. It is characterized in that it is configured such that it is sent for a predetermined time and the polarity of the transmission signal is inverted.

According to a fifth aspect of the present invention, in the signal transmission system according to the third aspect, the voltage inverting means is in the current mode when the change in the current mode return signal returned from the terminal device in synchronization with the synchronization signal is detected. It is characterized in that the polarity of the transmission signal is inverted when the return signal rises.

According to a sixth aspect of the present invention, there is provided a voltage mode transmission signal including control information, address information for specifying a control target, a return request signal requesting a return signal from the control target, and a synchronization signal indicating a transmission timing of the return signal. The transmission means for dividing and sending out via the transmission line, the current detection means for detecting the presence or absence of the current mode return signal input via the transmission line, and the current detection means detected the presence of the current mode carrier signal. And a central processing unit provided with voltage inverting means for inverting the polarity of the transmission signal sent from the transmitting means after the completion of the return signal; and a current mode return signal connected to the transmission line and responding to the return request signal. A plurality of terminal units for dividing and sending to the central processing unit;

[Operation] In the inventions according to claims 1 and 2, the central processing unit time-divisionally transmits a voltage-mode transmission signal including control information and address information for specifying a control target to the terminal device through the transmission line. To do. In addition, the terminal device to be controlled time-divisionally transmits the current mode transmission signal to the central processing unit.
Then, the voltage inverting means of the central processing unit for inputting the current mode transmission signal inverts the polarity of the transmission signal and sends out when the change of the current mode transmission signal is detected.
Therefore, it becomes possible to detect the signal of another terminal regardless of the connection position of the terminal to the transmission line. In addition, since it is not necessary to send and receive a special answer signal corresponding to the transmission signal sent from the terminal device, a decrease in transmission rate is not induced.

Further, in the invention of claim 2, the display panel connected to the transmission line receives the voltage mode transmission signal sent from the central processing unit and displays the transmission contents.

Further, in the inventions according to claims 3 to 6, the central processing unit has control information, address information for specifying a control target, a return request signal for requesting a return signal from the control target, and a synchronization signal indicating a transmission timing of the return signal. The voltage-mode transmission signal including the signal is time-divisionally sent to the terminal device via the transmission line. Also, the terminal device to be controlled sends the current mode return signal in response to the return request signal to the central processing unit via the transmission line at a timing corresponding to the synchronization signal sent from the central processing unit. To do. Then, when the central processing unit inputs this current mode return signal, the voltage inverting means inverts the polarity of the transmission signal according to the change of the current mode return signal or the detection of the presence of the return signal, and sends it out.
Therefore, it becomes possible to detect the signal of another terminal regardless of the connection position of the terminal to the transmission line. Further, since it is not necessary to send and receive a special answer signal corresponding to the transmission signal sent from the terminal device, the transmission speed is not lowered. Furthermore, since the transmission timing of the return signal from the terminal device is determined based on the synchronization signal, the transmission timing can be easily adjusted.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

[First Embodiment] FIG. 1 shows a schematic configuration of a signal transmission system according to a first embodiment of the present invention. The system shown in the figure includes a central processing unit 1 as a master unit and a plurality of terminal units 5 as slave units connected to the central processing unit 1 through a pair of transmission lines 3.
(5-1, 5-2, 5-3, ...) And the monitor display panel 7 and the like. A load (not shown) such as a lighting fixture, a wall switch, an illuminance sensor, etc. is connected to each of the terminals 5-1, 5-2, 5-3 ,.

FIG. 2 shows a block diagram of the central processing unit 1. As shown in the figure, the central processing unit 1 includes a signal processing circuit 11,
It is provided with a current detection circuit 12 which is a means for detecting a current mode signal from the terminal and a drive circuit 13 which constitutes a transmission means for transmitting a transmission signal to the transmission line 3. Further, the central processing unit 1 includes a differentiating circuit that generates a differential output each time the output voltage of the current detection circuit 12 changes, and a flip-flop circuit 19 that inverts the differential output. In addition,
The central processing unit is further provided with a keyboard and switches for data input or sensors, and a display device for various displays, such as a CRT, if necessary.

The signal processing circuit 11 captures data from the keyboard, switch, sensor, etc. according to a predetermined sequence, collects monitoring data of each terminal device, creates a control signal based on these data, and displays in the display device. indicate. In addition, a transmission voltage signal including the control signal and the like is created. In the conventional central processing unit, this voltage signal is directly input to the drive circuit 13 and sent out to the transmission line 3 as a transmission signal. Therefore, the format of this transmission voltage signal is as shown in FIG. 3 (a). It is the same as the transmission signal format from the central processing unit in the system.

Referring to FIG. 3 (a), this transmission voltage signal, that is, the transmission signal in the conventional system, includes a start signal ST consisting of a long pulse signal of "1" level and half the required number of bits.
The number of “1” level short pulse groups and the transmission signal ADR / CNT indicating the transmission data such as the address ADR of the destination terminal and the control signal CNT, and the long pulse signal of “1” level It is composed of a return period signal RTM and the like indicating a return waiting period of the monitoring data and the like from. Transmission signal ADR
In / CNT, each successive "1" level part and "0" level part represents 1-bit data, and a short "1" or "0" level part indicates data "0". ,
The long one indicates "1".

Returning to FIG. 2, the current detection circuit 12 causes the current flowing between the central processing unit 1 and the terminal device via the transmission line 3 (current such as monitoring data as indicated by hatching in FIG. 3A). Mode signal) to voltage.

The drive circuit 13 drives the transmission line 3 with a bipolar signal corresponding to the input signal. For example, if the input signal is "1" level, the transmission line is pulled up to + 24V, and if it is "0" level. Pull down to -22V. In the conventional central processing unit, the signal voltage output of the signal processing circuit 11 is directly input to the drive circuit 13, but in this embodiment, the third
A transmission signal AD including a start signal ST and address information for specifying a control target and control information as shown in FIG.
R / CNT is sent as it is, but during the return period, signal processing circuit 1
The return period signal RTM output from 1 is processed by the flip-flop circuit 19 and sent out. The flip-flop circuit 19 constitutes the transmission circuit 20 which is the transmission means of the central processing unit of this embodiment together with the drive circuit 13 described above.

Further, the differentiating circuit 15 detects a change in the current mode transmission signal sent from the terminal by differentiating the output voltage of the current detecting circuit 12, and the current detecting circuit 12 and the current detecting circuit in the present embodiment. Constitutes a means.

The flip-flop (F / F) circuit 19 constitutes the voltage inverting means in this embodiment, and its voltage output rises at the rising edge of the voltage signal output from the signal processing circuit 11 and falls at the falling edge, The differential output of the differentiating circuit 15 constituting the current detecting means is used as a trigger to perform a steering operation to invert the output. That is, the flop-flop circuit 19 sends a voltage that changes according to the output change of the signal processing circuit 11 to the drive circuit 13, and when the output of the signal processing circuit 11 is constant, the current mode signal detected by the current detection circuit 12 is A voltage that is inverted each time it changes is sent to the drive circuit 13.

The drive circuit 13 drives the transmission line 3 in accordance with the output voltage of the flip-flop circuit 19, so that the start signal ST and the transmission signal ADR / CNT are processed as shown in FIGS. 3 (a) and 3 (b). A voltage mode signal having the same shape as the output waveform from the device 11 is sent to the transmission line 3 and, during the returning period, a current mode returning signal from the terminal device.
The voltage mode signal RPV corresponding to RPI is sent to the transmission line 3.

That is, in the transmission system of FIG. 1, during the return period, the current mode signal from the terminal 5 is converted into the voltage mode signal by the central processing unit 1 and sent to the transmission line 3. For this reason, the monitor display panel 7 is not limited to the terminals 5-3 and the terminals connected after it by the voltage mode signal, but also the terminals 5-1, 5- The contents of the current mode signal from 2 can also be determined. Therefore, in this system, the monitor display panel 7 can be connected to any place of the transmission line 3. Further, any of the terminals can determine the signal transmission state of all the terminals based on this voltage mode signal. That is, each of the terminals can determine the openness of the transmission line 3 and the presence / absence of a signal collision by itself. Therefore, according to this system, it is possible to realize a random transmission system that makes use of the features that there are few collisions and the original transmission speed of the random system is high without increasing the load on the central processing unit. Furthermore, when each terminal sends out the current mode signal, the central processing unit discriminates the voltage mode signal converted from the current mode signal to thereby confirm that the current mode signal is received by the central processing unit. You can check. Therefore,
The answer signal from the central processing unit is unnecessary, and the transmission speed can be increased regardless of the transmission method.

FIG. 4 shows a functional block diagram of the terminal 5 in the transmission system of FIG. This terminal device 5 includes a signal processing circuit 5
1, a receiving circuit 52, a transmitting circuit 53 and the like. A single or a plurality of loads 9 are connected to the signal processing circuit 51.

The receiving circuit 52 receives the voltage mode signal sent from the central processing unit 1 to the transmission line 3. The signal processing circuit 51 operates according to a predetermined sequence, receives a control signal or the like included in the voltage mode signal received by the receiving circuit 52, and supplies the load drive signal based on the control signal or the like to the load 9. If the load 9 is a monitoring load, the monitoring signal is detected to create monitoring data, and this monitoring data is output to the transmission circuit 53 according to the control signal and the like. The transmission circuit 53 connects a resistor between the transmission lines according to the monitoring data output from the signal processing circuit 51, and changes the sink current value in the terminal device 5. As a result, the monitoring data is sent to the transmission line 3 as a current mode signal. When the output impedance of the drive circuit of the central processing unit is low, there is almost no change in the line voltage of the transmission line 3 due to this current mode signal, but the shaded area RPI in FIG. 3 (a) shows this current mode signal as a model. It is shown in the figure.

FIG. 5 shows the monitor display panel 7 in the transmission system shown in FIG.
The functional block diagram of is shown. The monitor display board 7 includes a signal processing circuit 71, a receiving circuit 72, a display unit 73 and the like.

The receiving circuit 72 receives the voltage mode signal sent from the central processing unit 1 to the transmission line 3. The signal processing circuit 71 operates according to a predetermined sequence, and based on the output of the receiving circuit 72, determines monitoring data and the like from the voltage mode signal obtained by converting the current mode signal sent from the terminal device by the central processing unit, A display signal corresponding to the monitoring data is sent to the display unit 73. The display unit 73 is an LED, a lamp, an LED array, or an LCD.
Alternatively, a display element such as a CRT and a drive circuit for driving these display elements are provided, and the state of a load or the like blinks these display elements according to a display signal input from the signal processing circuit 71, or these Display is made by showing lines, figures, characters, etc. on the display element.

FIG. 6 shows a concrete circuit example of the central processing unit 1 in the transmission system of FIG.

The central processing unit circuit in the figure is a microprocessor (CP
U) 21 controls the entire operation, and the functions corresponding to the signal processing circuit 11, the differentiating circuit 15 and the flip-flop circuit 19 in FIG. 2 are realized by the operation program of the CPU 21.

The central processing unit of the same figure further includes an A / D converter 22 for converting the analog output of the current detection circuit 12 into digital data that can be processed by the CPU 21, and supplying the digital data. + 26V and -24V, and a DC power supply 23 that generates a DC voltage of + 5V for circuits other than this output stage, a zero-cross detection circuit 24 that detects the zero-cross of the AC power supply, a zero-cross signal for sending the zero-cross signal to the transmission line It is provided with a sending circuit 25, an oscillating circuit 26 for generating a drive clock for the CPU 21, and a reset circuit 27 for setting the CPU 21 to an initial state.

When sending the transmission signal from the central processing unit to the terminal, CP
U21 is a drive circuit that is similar to the waveform shown in FIG. 3 (b), except that the "0" level is 0V and the "1" level is 5V.
Supply to 13. The drive circuit 13 has a "0" level of -22V and a "1" level of + 24V according to the voltage signal from the CPU 21.
The voltage mode signal having the waveform as shown in FIG. 3B is sent to the transmission line 3.

The zero-cross detection circuit 24 detects the zero-cross of the AC power source and inputs the “1” level zero-cross signal to the CPU 21.
In the detection circuit 24, for example, an AC 100V AC power source is supplied to the diode bridge DB1 via the insulating transformer T1, and the full-wave rectified output from the diode bridge DB1 is applied to the base of the transistor Tr1 for super-C class amplification. Therefore, when this full-wave rectified output is 0V, that is, at the zero-cross timing of the AC power supply, the transistor Tr
Generates a 5V zero-cross signal on the collector of 1.

The CPU 21 supplies this zero-cross signal to the zero-cross signal transmission circuit 25 as it is, when necessary such as at the time of central activation. In the zero-cross signal transmission circuit 25, when the zero-cross signal is input, the analog switch AS1 is turned off to cut off the voltage signal supply from the CPU 21 to the drive circuit 13, thereby cutting off the signal transmission from the central processing unit to the terminal device. , The zero-cross signal from the CPU 21 drives the photocoupler PC1 to short-circuit the AC terminals of the diode bridge DB2, thereby short-circuiting the transmission lines 3. As a result, the zero-cross signal of voltage 0 is transmitted to the terminal.

Conventionally, this zero-cross signal was created in the terminal device, but if it is created in the central processing unit and transmitted to each terminal device in this way, one zero-cross detection circuit is sufficient and each terminal device is In comparison with the case of providing the same in the above, the circuit configuration can be simplified and the cost can be reduced as viewed from the whole system.

FIG. 7 shows a specific circuit example of the terminal 5 in the transmission system of FIG.

In the figure, 61 is a microprocessor (CPU) corresponding to the signal processing circuit 51 of FIG. 4, and 52 and 53 are a receiving circuit and a transmitting circuit common to those shown in FIG. 4, respectively.

Further, 62 is a zero-cross signal receiving circuit, 63 is a self-address setting circuit, 64 is a DC power supply for generating a DC output of 5V from an AC power supply, and 65 is a clock generation circuit. Further, C51 is a capacitor for resetting the CPU 61 when the terminal device is powered on, and DB51 is a transmission line 3 which is a multi-pole (AC) system and a transmission circuit 52 and a zero-cross signal reception circuit 55 which are a single pole (DC) system. It is a diode bridge for matching with.

Various load devices are connected to this terminal device singly or in various combinations, but here, a load device that does not require a zero-cross signal as 91 and a load device that requires a zero-cross signal as 92 are adjusted. Optical device,
A switch that is a monitoring load is illustrated as 93. It should be noted that only the load driving section is shown for each of the load devices 91 and 92.

The receiving circuit 52 determines whether the voltage mode of the transmission line 3 is “0”,
Depending on whether it is "1", 0 and 5V signals are generated and supplied to the CPU 61. The transmission circuit 53 is supplied with a transmission signal from the terminal device created by the CPU 61 to the central processing unit, and the resistor R51 is provided between the transmission lines 3 only when the transmission signal is "1".
Connect. At this time, the resistor R51 serves as a current sink, and the current flowing through the resistor R51 changes the current RPI flowing through the transmission line 3 as shown by the shaded area in FIG. 3 (a), which is the current detection circuit 12 (second circuit) of the central processing unit. The current mode signal transmission from the terminal unit to the central processing unit is carried out by the detection in FIG.

As described above, the line voltage of the transmission line 3 becomes 0 only when the zero-cross signal is transmitted from the central processing unit, and otherwise +.
It is 24V or -22V. That is, the DC end voltage of the diode bridge DB51 becomes 0 only when the zero-cross signal is transmitted, and otherwise becomes about + 24V or + 22V. The zero-cross signal receiving circuit 55 uses this diode bridge DB51.
It is a voltage dividing resistor circuit that divides the DC end voltage of to about 1/5.

When the output of the zero-cross signal receiving circuit 62 changes from about 5V to 0, the CPU 61 detects it as a zero-cross signal.
Then, for each half cycle of the AC power supply, a pulse of 5V is created with a phase angle based on the zero-cross signal and the control signal transmitted from the central processing unit, and the pulse is supplied to the dimmer 92. As a result, in the light control device 92, the triac TZ is turned on at the conduction angle designated by the control signal, and the lamp, which is a load (not shown), is dimmed.

On the other hand, in the monitoring load 93, when the switch SW93 is operated, the CPU 61 detects it and creates monitoring data indicating ON / OFF thereof. This monitoring data is sent to the central processing unit in current mode as described above.

FIG. 8 is a monitor display panel 7 in the transmission system of FIG.
The concrete circuit example of is shown.

In the figure, 71 is a microprocessor (CPU) corresponding to the signal processing circuit 71 of FIG. 5, and 72 and 73 are a receiving circuit and a display unit common to those shown in FIG. 5, respectively.

Further, 75 is a DC power supply that generates a 5V DC output from the AC power supply, 76 is a clock generation circuit, and C71 is a capacitor for resetting the CPU 71 when the power supply of this monitor display device is turned on.

The reception circuit 72 generates reception signals of 0 and 5 V depending on whether the voltage mode of the transmission line 3 is “0” or “1” and supplies the reception signals to the CPU 71. The display unit 73 is composed of display elements (light emitting diodes) LEDs 71 to 7n corresponding to the output terminals OUT71 to 7n of the CPU 71 and transistors Tr71 to 7n for driving the LEDs, etc. Output terminal OUT7x that generated a drive signal of 5V based on
By turning on the transistor Tr7x connected to
LED7x lights up and a display is made.

Next, the operation of the system having the configuration shown in FIGS. 1 and 6 to 8 will be described with reference to the flowcharts of FIGS.

The central processing unit 1, the terminal unit 5 and the monitor display panel 7 start to operate according to the control programs contained in the respective CPUs when their own power supplies are turned on. First, various memories, registers, etc. built in the CPU are initialized, and thereafter, the infinite loop processing shown in the flowcharts of FIGS. 9 to 11 is executed.

A. Operation of central processing unit Referring to FIG.
At 102, the presence or absence of start data is determined. If there is data to be sent to the terminal, that is, activation data, step 104
~ 142 central activation (parent activation) processing is executed, and if there is no activation data, normal mode processing of steps 150 to 180 is executed.

Central start-up processing In the central start-up processing, first, in step 104, the transmission data including the start signal ST, the destination terminal address ADR, the control signal (starting data) CNT, etc. as shown in FIG. 3 (b) is driven. The voltage is sent from the circuit 13 to the transmission line 3 in the voltage mode. This transmission of the transmission data is performed one bit each time the processing of step 104 is passed once. The next step 106 is a step for determining whether or not the process of step 104 has been repeated a predetermined number of times corresponding to the number of bits of transmission data. If the number of processes of step 104 is less than the predetermined number of times, the process is performed. To step 104. When the process of step 104 is repeated a predetermined number of times and a voltage mode signal of a predetermined number of bits is transmitted, step 106 is performed.
Then, it is determined that the transmission is completed, and the process proceeds to the next step 112.

At step 112, the output of the current detection circuit 12 is fetched, and at step 114, the presence or absence of the current mode signal from the terminal is judged. In this embodiment, when the current mode signal is not detected within a predetermined time (for example, 600 μS), it means that 1 bit (return signal) of the return data corresponding to the section to which the predetermined time belongs is “0”, If detected, it means that the bit (return signal) is "1".

If it is determined in step 114 that the return signal is present, the output voltage from the drive circuit 13 is inverted in step 118, the process waits until the return signal is not detected in step 122, and the output voltage is set in step 124. After reversing and returning to the original voltage mode, the process proceeds to step 132. By the processing of these steps 118 to 124, "1" of the current mode return signal is converted to "0" of the voltage mode return signal.

On the other hand, if no return signal is detected, steps 118-124
And skips step 114 and proceeds directly to step 132. In this case, since the current mode signal is “0” and the voltage mode signal remains “1”, it is the same as the current mode signal being converted into the voltage mode signal.

In step 132, it is determined whether the return from the terminal has been completed. If the conversion process from the current mode signal to the voltage mode signal is not completed for all the bits of the return data, the return is not completed, so the process returns from step 132 to step 112, and the processes of steps 112 to 132 are performed. repeat.

On the other hand, when the processes in steps 112 to 132 have been executed the same number of times as the number of bits of the return data, it is determined in step 132 that the return from the terminal device is completed, and the process proceeds to step 140. In step 140, it is determined whether the returned data is normal. This determination can be performed, for example, by returning the same signal as the transmitted control signal CNT as an acknowledgment ACK, and determining whether or not this acknowledgment and the control signal CNT transmitted by itself match.

If the return data is normal, it means that the transmission of the return data has been normally performed, so that the start data is cleared in step 142 to cancel the start, and the process returns to step 102.

On the other hand, if the return data is abnormal, step 142 is skipped and step 140 directly returns to step 102. In this case, the startup data remains as is, so step
At 102, it is determined that there is start data, and the central start process is executed again. That is, this central activation process is repeated until the activation data is normally transmitted.

Normal Mode Processing If it is determined in step 102 that there is no start data, then in step 150 a start signal for terminal start is transmitted, and in step 154 it is determined whether or not a current mode start signal is sent from the terminal device. judge. If there is no response from this terminal activation start signal for a predetermined time (for example, several mS) from any terminal device, there was no terminal activation.
Return to step 102.

On the other hand, when the terminal activation signal is detected in step 154,
When it is determined that the terminal has been activated, the process proceeds to step 158, and the normal mode process of steps 158 to 180 is executed.

During the normal mode processing, first, at step 158, the current mode signal sent from the terminal is received.

In this embodiment, as described above, the predetermined time (for example, 600
No current mode signal in μS) means that one bit of the terminal data corresponding to the section to which the predetermined time belongs is “0”, and that with current mode signal means that bit is “1”. To do. In step 160, the output of the current detection circuit 12 is inspected. Then, if the current mode signal is detected, the bit (transmission signal) corresponding to the current timing of the terminal data is "1", so that the output voltage from the drive circuit 13 is inverted in step 164, and the process proceeds to step 170. Wait until the current mode signal is no longer detected and step
At 172, the output voltage from the drive circuit 13 is inverted again to restore the voltage mode of the transmission line to the original, and then the process proceeds to the next step 180.

On the other hand, in step 160, the predetermined time (for example, 600 μS)
If the return signal is not received even after waiting, since the bit corresponding to the current timing of the terminal data is "0", the process of steps 164-172 is skipped and the process proceeds directly from skip 160 to step 180. In this case, drive circuit 1
The output voltage from 3 to the transmission line 3 is not inverted.

That is, every time the processes of steps 158 to 180 are executed, the terminal data is converted into a voltage mode signal bit by bit.

Step 180 is a determination process for converting the terminal data into the above voltage mode bit by bit. That is, in step 180, it is determined whether or not the reception of the current mode signal corresponding to all the bits of the terminal data from the terminal is completed, that is, whether or not the current mode signal of a predetermined number of bits is converted into the voltage mode signal. judge. If the reception has not been completed, the process returns to step 158 and steps 158 to
The process of 180 is repeated.

When the processes of steps 158 to 180 are repeated by the same number as the number of bits of the terminal data, reception of all bits of the terminal data and conversion from the current mode signal to the voltage mode signal, etc.
The necessary processing for the terminal data ends. In this case, it is determined in step 180 that the reception has ended, and the process returns to the first step 102.

B. Operation of Terminal Device Referring to FIG. 10, the terminal device 5 first determines in step 202 whether or not a central activation signal in the voltage mode is transmitted from the central processing unit. If a central activation signal is sent from the central processing unit (step 104 in FIG. 9), step 202
Perform ~ 230 return processing. On the other hand, if it has not been transmitted, it is determined in step 250 whether or not there is activation data.
If there is data to be sent to the central processing unit, that is, activation data, the terminal activation (child activation) processing consisting of the circulation processing of steps 260 to 280 is executed. If the central activation signal is not transmitted in step 202 and there is no terminal data to be transmitted to the central processing unit from itself, the process directly returns to step 202.

Return processing During the return processing, the voltage mode transmission data sent from the central processing unit based on the output of the receiving circuit 52 in the circulation processing of steps 204 and 210 (steps 104 to 106 in FIG. 9) is subjected to this circulation processing. One bit is received each time. When the reception of the predetermined number of bits is completed, the process proceeds from step 210 to step 224, and in step 224, the first 1 bit (return signal) of the return data is sent from the transmission circuit 53 to the transmission line 3 in the current mode. This current mode return signal is received by the central processing unit (step 9 in FIG. 9).
112) is converted into a voltage mode signal (steps 118 to 12 in the same step)
Four).

In step 228, the voltage mode signal is received from the transmission line 3 and it is determined whether or not the received signal matches the reply signal sent by itself.

If they match, 1 of the return signal sent in step 224
Since the bit was received by the central processing unit and converted from the current mode to the voltage mode, the transmission of the bit was successful. In the next step 230, it is judged whether or not the normal transmission of all the bits of the return signal is completed. If the transmission of all the bits has not been completed, the process returns to step 224, and the processes of steps 224 to 230 are repeated for the next bit (return signal). On the other hand, if the returning of all the bits is completed, the returning process is ended and the process returns to step 202.

If the return signal and the reception signal do not match in step 228, the bit (return signal) of the return data has not been correctly received by the central processing unit, and therefore the process directly returns to step 202. In this case, the central processing unit cannot obtain the returned data of a predetermined number of bits (step 140 in FIG. 9), so the activation canceling (step 142) processing is skipped and the central activation processing is executed again. Therefore,
The terminal device again executes the return process, and eventually the central processing of the central processing unit and the return process of the terminal device to this are repeated until normal return data transmission is performed. .

Terminal Starting Process In this terminal starting process, first, steps 260 to 270 are performed.
Each time the circulating process of 1 is executed once, the start data is sent in 1-bit units in the current mode. This current mode signal is received by the central processing unit (step 158 in FIG. 9) and converted into a voltage mode signal (steps 164-172). At the time of this circulation processing, in step 268, the voltage mode of the transmission line 3 is determined, and the contents of this voltage mode signal and the current mode signal sent by itself are compared. If the contents of these signals match, the current mode signal sent by itself is
There is no doubt that it has been received by the central processing unit and converted into voltage mode. Then, as long as it is determined that the signal is correctly received, the circulation process is stepped.
The process continues until it is determined in 270 that the transmission of the boot data is completed.

When the circulating process is executed the number of times corresponding to the number of bits of the activation data, it is determined in step 270 that the transmission of the activation data has been completed, and the process proceeds to step 280. Step two
At 80, after the start data is cleared to cancel the start, the process returns to step 202.

On the other hand, if the contents of the current mode signal transmitted in step 258 and the received voltage mode signal are different, it is determined that the current mode signal transmitted from the terminal device was not correctly received by the central processing unit, and the circulation is performed. Step 25
Stop at 8 and return to step 202. In this case, since the start-up data of the terminal remains, the central processing unit sends a start signal for starting the terminal (step 15 in FIG. 9).
0), when the process proceeds from step 202 to step 250, it is determined in this step 250 that the start data exists,
This terminal activation process is executed again. That is, this terminal activation process is repeated until the activation data is normally transmitted to the central activation process.

C. Operation of the monitor display board Referring to FIG.
At 2, it is determined whether or not a central activation signal is sent from the central processing unit. If the central activation signal is sent from the central processing unit (step 104 in FIG. 9), the processing is performed in step 3
Go to 04, while if not sent, step 312
Proceed to.

In step 304, the voltage mode transmission signal (central activation data) sent from the central processing unit (steps 104 to 106 in FIG. 9) is detected. Then, in the next step 306, the return signal (return data) of the terminal device with respect to this transmission signal is detected by the voltage mode signal converted by the central processing unit, and in step 308, whether these signals match in content or not. Determine whether or not. This step 308 is similar to step 140 (FIG. 9) in the central processing unit. If the two signals match in step 308, it means that the data transmission between the central processing unit and the terminal has been normally performed. Therefore, in step 310, a display is made based on the contents of the data transmission.

On the other hand, if the two signals do not match in content in step 308, it means that the data transmission between the central processing unit and the terminal unit is abnormal. Return to 302. In this case, since data transmission of the same content is repeated until it is normally executed, the process of step 310 is executed when the data is normally executed. Display based on content.

If it is not the central start in step 302, the process is step 3
Then, in step 312, it is determined whether or not the terminal has been activated. If none of the terminals start up, step 312
Returns directly to step 302.

If it is determined in step 312 that one of the terminals has started up, in step 314 each bit of the terminal data sent from the starting terminal is detected by the voltage mode signal converted by the central processing unit, In step 316, it is determined whether or not the terminal signal is normally transmitted based on whether or not a signal having a predetermined number of bits is detected.

If it is transmitted normally, the load monitoring display based on the terminal data is performed in step 310.

On the other hand, when it is determined in step 312 that the data transmission from the terminal device to the central processing unit is not normally performed, the process returns from step 316 to step 302. Also in this case, the terminal-started data transmission is repeated until it is normally carried out, and when it is carried out normally, the process proceeds to step 310 to be monitored and displayed.

In the above-described first embodiment, the central processing unit causes the return standby signal RTM of "1" level during the return period from the terminal device.
An example in which the present invention is applied to a system for sending a message has been described. However, as shown in FIG.
The present invention can be applied even when M is at the "0" level.
However, the polarity of the voltage mode converted from the current mode signal is opposite to the above case, as can be seen by comparing FIG. 3 (b) and FIG. 3 (b).

[Second Embodiment] FIGS. 13 to 19 show a second embodiment.

In the conventional example and the first embodiment described above, FIG. 15 (a) shows that the central processing unit transmits to the transmission line during the terminal transmission period for transmitting the current mode terminal data from the terminal to the central processing unit.
Sending a positive or negative long pulse voltage such as the return period signal RTM shown in Fig. 2 and sinking a current from this long pulse voltage on the terminal side enables current mode signal transmission from the terminal to the central processing unit. I am doing it.

In the case of these conventional examples and the first embodiment, the current mode terminal signal such as the return signal is transmitted at a relatively free timing within the long pulse section set by the central processing unit. There is. For this reason, the transmission timing may be shifted due to the state of the terminal device or the delay caused by the repeater, which makes it difficult to adjust the timing in the central processing unit.

In the second embodiment, in the signal transmission system configured as shown in FIG. 1, as shown in FIG. 15 (b), transmission of transmission data bit by bit during a terminal transmission period such as a return waiting period. By sending the synchronization signal indicating the timing from the central processing unit 1 to the transmission line 3 in the voltage mode, the terminal device 3
The central processing unit 1 manages the timing of signal transmission from the.

Here, in the first signal transmission system, the hardware shown in FIG. 6 is used as the central processing unit 1, the hardware shown in FIG.
The above functions are realized by appropriately setting the control programs of the U21 and the CPU 61.

13 and 14 show functional block configurations of the central processing unit 1 and the terminal unit 3 according to the second embodiment, respectively.

The central processing unit 1 shown in FIG. 13 is different from the one shown in FIG. 2 in that a synchronizing signal generating circuit 18 for generating a synchronizing signal SYNC at a predetermined cycle is added only during a signal transmission period from the terminal to the central processing unit. The flip-flop circuit 19 is configured to be inverted not only by the differential output of the differentiating circuit 15 but also by the synchronizing signal SYNC. The functions of the differentiating circuit 15, the synchronizing signal generating circuit 18, the flip-flop circuit 19, etc. are
It is realized by the control program of 1.

The terminal device of FIG. 14 is different from that of FIG. 4 in that a sync signal detection circuit 55 for detecting a voltage mode sync signal sent from the central processing unit 1 to the transmission line 3 based on the output of the reception circuit 52.
And a flip-flop circuit 57 for latching the output of the signal processing circuit 51, and when the synchronizing signal detecting circuit 55 detects the synchronizing signal, the latch output of the flip-flop circuit 57 is sent from the transmitting circuit 53 to the transmission line 3 in the current mode. It is designed to be sent out. The functions of the sync signal detection circuit 55 and the flip-flop circuit 57 are also realized by the control program of the CPU 61.

Next, the operation of the system whose configuration is shown in FIGS. 1, 6, 7, 13, and 14 will be described with reference to the flowcharts of FIGS.

The central processing unit 1, the terminal unit 5 and the monitor display panel 7 start to operate according to a control program stored in each CPU when the respective power supplies are turned on. First,
After initializing various memories, flags, registers, etc. built in the CPU, the central processing unit 1 is shown in the flowcharts of FIGS. 16 and 18, and the terminal 5 is shown in the flowcharts of FIGS. 17 and 19. Then, the monitor display board 7 executes each infinite loop process shown in the flowchart of FIG. 11 described above.

A. Operation of central processing unit Referring to FIG.
At 102, it is determined whether or not the data transmission to be performed now is the normal mode. If there is no data to be sent from the central processing unit 1 to the terminal device 5, that is, the activation data, the normal mode is set, and the normal mode flag is set in step 190 described later. On the other hand, if there is startup data,
The normal mode flag is reset in step 188 described later. Therefore, in step 102, the normal mode flag is checked, and if this flag is set, the process proceeds to step 150, and the normal mode process of steps 150 to 180 is executed. On the other hand, if the normal mode flag is reset, the process proceeds to step 104 and steps 104 to 14
Perform the central startup process of 2 (Fig. 18).

Central start-up process Referring to FIG. 18, during the central start-up process, first, step
At 104, a start signal ST, a destination terminal address ADR, and a control signal (start data) C as shown in FIG. 15 (b)
The transmission data composed of NT or the like is sent from the drive circuit 13 to the transmission line 3 in the voltage mode. Subsequently, in step 108, the control variable n is set to 1, and then the return signal receiving process of steps 110 to 132 is executed.

In this reply signal receiving process, the n-th synchronizing signal is sent from the driver circuit 13 in step 110. Here, the synchronization signal is a short pulse of level "1", and then maintains the level "0", and the output of the current detection circuit 12 is inspected by the circulation processing including steps 114 and 126.

When the current mode return signal is sent from the terminal device 5, the output voltage of the current detection circuit 12 changes. When the transmission of the return signal is detected in step 114, it is determined that there is a return signal,
The process proceeds from step 114 to step 118. In step 118, the output voltage from the drive circuit 13 is inverted, and in step 120, it is determined that the nth bit of the return data is “1”, and in step 122. After waiting until the return signal is not detected, the output voltage from the drive circuit 13 is inverted again in step 124 to return the transmission line 3 to the original voltage mode level “0”, and then in step 130. The control variable n is incremented and the process proceeds to step 132. By the processing of these steps 118 to 124, "1" of the current mode return signal is converted into "1" of the voltage mode signal.

In this embodiment, the terminal 5 sends the current mode signal "1" when 1 bit (return signal) of the return data to be sent is "1", but when it is "0", the current mode signal is sent. Is not sent. So step 114 and step 1
When a predetermined time (for example, 600 μS) has passed without detecting the current mode return signal in the circulation process consisting of 26, it is determined in step 126 that there is no return signal and the process proceeds to step 128. At 128, it is determined that the nth bit of the returned data is "0", and at step 130, the control variable n is incremented, and then the process proceeds to step 132. When there is no return signal, the output voltage of the driver circuit 13 remains “0”, and as a result, “0” of the current mode return signal appears on the transmission line 3 as “0” of the voltage mode. Will be done. That is, the current mode return signal is converted into the voltage mode signal on the transmission line 3 regardless of whether the level is “0” or “1”.

In step 132, it is determined whether or not the processing such as detection, level determination and conversion into the voltage mode signal of the current mode return signal from the terminal 5 has been completed for all the bits of the return data. The control variable n indicates the number of processed bits. If the control variable n has not reached the number of bits N of the return data, there is still a return signal that has not been received. Then, the return signal receiving process of steps 110 to 132 is repeated.

On the other hand, if the control variable n has reached the number of bits N of the return data, it means that all the bits of the return data have been received.
In step 132, it is determined that the return from the terminal is completed, the return signal receiving process is canceled, and the process proceeds to step 182 in FIG.

In step 182, a sync signal is output, and in the following step 184, it is determined whether or not there is data to be transmitted to the terminal device 5. If there is data to be transmitted, new data is set as transmission data in step 186, and further step 188
After resetting the normal mode flag at, on the other hand, if there is no data to be transmitted to the terminal device 5, the normal mode flag is set at step 190, and then the process proceeds to the first step 10.
Return to 2.

Normal Mode Processing Referring to FIG. 16, as described above, when there is no data to be transmitted from the central processing unit 1 to the terminal 5, step 19 is performed.
At 0, the normal mode flag is reset, this is judged at step 102, the process proceeds to step 150, and the normal mode process of steps 150 to 180 is executed.

In this normal mode processing, first, at step 150, a start signal for the normal mode is sent to the transmission line 3. Then, after setting the control variable m to 1 in step 152, the terminal signal receiving process of steps 156-180 is performed.

In this terminal signal reception processing, first, step 156
Then, the driver circuit 13 sends the m-th synchronizing signal. Next, the output of the current detection circuit 12 is inspected by a circulation process including steps 160 and 174. Here, the synchronization signal is a short pulse of level "1", and this synchronization signal is followed by a terminal standby period of level "0" for detecting 1 bit (terminal signal) of terminal data.

In the terminal signal receiving process, the output voltage of the voltage detecting circuit 12 changes when the current mode terminal signal is sent from the terminal device 5 as in the return signal receiving process. In step 160, when the output voltage change of the current detection circuit 12, that is, the sending of the terminal signal is detected, it is determined that the terminal signal is present, the process proceeds from step 160 to step 164, and the sending from the drive circuit 13 is performed in this step 164. Invert the voltage. Then, in step 168, it is determined that the m-th bit of the terminal data is "1", and in step 170, it waits until the terminal signal in the current mode changes to "0" again. After reversing the output voltage from the circuit 13 and returning the voltage mode of the transmission line 3 to the level "0",
The process proceeds to step 178. These steps 164-17
By the processing of 2, the current mode terminal signal “1” is converted into the voltage mode signal “1”.

As described in the above-mentioned return signal reception processing, in this embodiment, when the terminal signal which is 1 bit of the transmission data from the terminal 5 to the central processing unit 1 is "1", it is transmitted from the terminal 5. The current mode signal to be output is "1", but the current mode signal when it is "0" is "0", which is the same as the no signal state.

Therefore, when a predetermined time (for example, 600 μS) has elapsed without detecting the current mode terminal signal in the circulation process including steps 160 and 174, step 174
To step 176, and after determining in step 176 that the m-th bit of the terminal data is "0", the process proceeds to step 178. When the current mode terminal signal is “0”, the output voltage of the driver circuit 13 remains “0” and does not change, but in this case as well, it may be considered that the current mode terminal signal is converted to the voltage mode signal. Absent. That is, the current mode terminal signal is converted into the voltage mode signal by the processing of steps 156 to 176 and sent out on the transmission line 3 regardless of whether the level is “0” or “1”. .

In step 178, the control variable m is incremented. In the next step 180, it is determined whether or not all bits of the terminal data have been received. The control variable m indicates the number of processed bits. If the control variable m does not reach the number M of bits of the terminal data, all the bits of the terminal data have not been received yet. In this case, the process is returned from step 180 to step 156, and the terminal signal receiving process of steps 156 to 180 is repeated.

On the other hand, if the control variable m is equal to the number of bits M of the terminal data, it means that all the bits of the terminal data have been received. In this case, it is determined that the reception of the terminal data has been completed in step 180, the process proceeds from step 180 to step 182, and after the processes of steps 182 to 190 described above and other necessary processes are completed, Returning to step 102, the above processing is repeated.

B. Operation of Terminal Device Referring to FIG. 17, in the terminal device 5, first, the voltage mode signal sent from the central processing unit 1 based on the output of the receiving circuit 52 in step 202 is a start signal in the normal mode. Or not. If the start signal in the normal mode sent from the central processing unit 1 by the processing of step 150 in FIG. 16 is received, it proceeds to step 250 and it is determined whether the load monitoring input has changed. When the monitoring input is changed, the terminal starting process consisting of the circulation process of steps 260 to 280 is executed in order to transmit the monitoring input to the central processing unit 1 as the monitoring data (terminal data). On the other hand, if there is no monitoring input in step 250, there is no data to be transmitted in response to this start signal in the normal mode, so after executing other processing not shown, step 202
Return to and wait for the next start signal.

If the start signal received in step 202 is not the normal mode start signal but the central start-up start signal sent from the central processing unit 1 by the process of step 104 of FIG. 18, step 204 of FIG. Then, the process goes to the central processing unit 1 to receive the transmission data such as the destination address ADR and the control signal CNT which are transmitted subsequently to the start signal at the time of central activation. In the following step 208, it is determined whether or not the destination address ADR matches the self address. If the destination address ADR does not match the self-address, the subsequent control signal CNT is sent to the other terminal device 5, so after executing the other processing, the process returns to step 202 and the next start is performed. Wait for the signal.

On the other hand, when the destination address ADR and the self address match in step 208, the return processing of steps 214 to 230 is executed.

Return processing At the time of return processing, first, in step 214, the control variable n is set to 1
, And then waits until a sync signal is received in step 216. If the synchronization signal is received in step 216, after waiting for a predetermined time (eg, 50 μS) in step 218, it is checked in step 220 whether the nth bit (return signal) of the return data is “1”. judge. If it is "1", in step 224, the current mode return signal of "1" is sent from the transmission circuit 53 to the transmission line 3, and then the process proceeds to step 226. The current mode return signal is received by the central processing unit 1 (step 114 in FIG. 18) and converted into a voltage mode signal (steps 118 to 124). On the other hand, if the nth bit of the return data is "0" in step 220, the current mode return signal of "0" is the same as no signal, so the current mode signal transmission process of step 224 is skipped and the step 220
To go directly to step 226.

In step 226, the control variable n is incremented, and the subsequent step 230
At, it is determined whether transmission of all the bits of the return data has been completed. If the transmission of all the bits has not been completed, the process returns to step 216, and the processes of steps 216 to 230 are repeated for the next bit (return signal). on the other hand,
If the transmission of all the bits is completed, the return processing is terminated and the process returns to step 202.

Terminal Activation Processing As described above, when the start signal in the normal mode is received in step 202 and it is determined in step 250 that the monitoring input is present, the monitoring data is processed by the central processing unit 1 by the terminal activation processing in steps 250 to 270. To transmit.

In this terminal starting process, first, in step 252, the self address and the monitoring data are set as the terminal data. Further, after the control variable m is set to 1, the terminal data transmission process consisting of the cyclic process of steps 256 to 270 is executed, and the terminal data is converted into a terminal signal by 1 bit in each current cycle of the terminal data transmission process in the current mode. To send.

That is, it waits until the synchronization signal is received in step 256, and if the synchronization signal is received, it is determined in step 260 whether or not the m-th bit (terminal signal) of the terminal data is "1". . If it is "1", it waits for a further predetermined time (for example, 50 µS) in step 262, sends the current mode terminal signal of "1" from the transmission circuit 53 to the transmission line 3 in step 264, and then the process proceeds to step 266. Proceed. The terminal signal in the current mode is received by the central processing unit 1 (step 160 in FIG. 16) and converted into a voltage mode signal (steps 164-172). On the other hand, if the m-th bit of the terminal data is “0” in step 260, the current mode signal of “0” is the same as no signal, so the current mode signal transmission processing of step 264 is skipped and the processing is performed. From step 260 to step 266 directly.

In step 266, the control variable m is incremented, and the following step 270
At, it is determined whether transmission of all bits of the terminal data has been completed. If the signal transmission has not been completed for all the bits, the process returns to step 256 and the processes of steps 256 to 270 are repeated for the next bit (terminal signal).
On the other hand, if the signal transmission for all the bits is completed, the terminal start-up process is completed and the process returns to step 202.

In the above description, an example of sending a synchronization signal in a 1: 1 correspondence with each bit of return data or terminal data, that is, a return signal or a terminal signal has been described, but one synchronization signal is sent for every multiple bits. You may try
Alternatively, only one synchronization signal may be transmitted, for example, only the first bit.

In this way, the central processing unit sends one or a plurality of synchronization signals during the signal waiting period from the terminal device, and the terminal device side sends a return signal or a terminal signal at a timing according to the synchronization signal. As a result, the following effects can be obtained.

Since the central processing unit manages the signal transmission timing from the terminal device, the timing adjustment becomes easy.

Since the number of synchronization pulses can be limited on the side of the central processing unit, redundancy can be provided in the terminal transmission waiting period. In addition, the number of bits transmitted from the terminal can be made redundant.

As described above, if the transmission period and the number of transmission bits are the same time and the same number of bits as in the conventional case, the condition becomes redundant, and as a result, the transmission speed can be improved by the margin.

[Third Embodiment] FIGS. 20 to 23 are for explaining a third embodiment.

In the above-described second embodiment, the central processing unit sends a synchronization signal to the terminal device, and the terminal device sends a return signal or a current mode signal if the terminal signal is "1" in synchronization with the synchronization signal. . However, the return signal or terminal signal is "0"
In this case, the current is not applied, so it is indistinguishable from no signal. Therefore, when the signal of the return or terminal data is all "0", when it is not transmitting, error, failure, etc. However, there is a problem in that the central processing unit cannot distinguish from the case where the transmission is cut off midway.

In the third embodiment, a status bit which becomes "1" only when the transmission is normally completed is added to the final portion of the transmission signal, and the central processing unit receives the status bit by checking the status bit. It is determined whether the data is legitimate. Then, the central processing unit cannot determine whether the transmission from the terminal unit to the central processing unit has been completed without any abnormalities, or whether the transmission has been interrupted midway due to an error or a failure, thereby preventing erroneous control.

Next, the operation of the signal transmission system according to the third embodiment will be described with reference to the flowcharts of FIGS.

In this third embodiment, the operation at the time of starting the terminal is exactly the same as that of the second embodiment, so only the operation at the time of central starting will be described.

A. Operation of central processing unit 1 In the central processing unit 1, when data to be sent to the terminal device 5, that is, activation data is generated, the central activation process of FIG. 20 is executed.

Central start processing Referring to FIG. 20, at the time of central start processing, first,
At 104, transmission data including a start signal ST, a mode signal MOD, a destination terminal address ADR, a control signal (starting data) CNT, etc. is sent to the transmission line 3 in the voltage mode. Then, after setting the control variable n to 1 in step 108,
The return signal reception process of steps 110 to 132 is executed.

In this return signal receiving process, the n-th synchronizing signal is sent in step 110, and the output of the current detection circuit 12 is inspected by the circulating process consisting of steps 114 and 126.

When the return signal transmitted from the terminal 5 by the processing of step 224 of FIG. 21 is detected at step 114, the processing proceeds from step 114 to step 118, and at step 118, the voltage mode output to the transmission line 3 is performed. Is inverted, it is determined in step 120 that the nth bit of the return data is "1", the process waits in step 122 until the return signal being received is no longer detected, and in step 124 the transmission line After reversing the sending voltage mode and returning it to the original value, the control variable n is incremented in step 130 and the process proceeds to step 132. By the processing of these steps 118 to 124, "1" of the current mode return signal is converted into "1" of the voltage mode signal.

On the other hand, when a predetermined time (for example, 600 μS) has passed without the current mode return signal being detected in the circulation process including steps 114 and 126, it is determined in step 126 that there is no return signal and the process is performed. To step 128,
In step 128, it is determined that the nth bit of the returned data is “0”, and in step 130, the control variable n is incremented,
The process proceeds to step 132.

In step 132, it is determined whether or not the return signal in the current mode from the terminal 5 has been received for all the bits of the return data, that is, whether or not the reception of all the bits has been completed. If not completed, the process returns to step 110 and repeats the return signal reception processing of steps 110-132. on the other hand,
If the processing is completed, after sending the synchronization signal in step 134, the processing in steps 136 to 146 is executed, and then the processing is performed in the 16th step.
Proceed to step 182 of the figure.

In the third embodiment, steps 136 to 146 are added to the second embodiment.

In FIG. 20, in step 136, it is determined whether or not the nth bit of the returned data is "1". The n-th bit, that is, the last bit, is the central processing unit 1 and the terminal unit 5.
It is the transmission data from the terminal device 5 that indicates whether or not the communication with the device is normally performed.

If the determination in step 136 is “0”, there is an error in the data transmission from the central processing unit 1 to the terminal unit 5 or from the terminal unit 5 to the central processing unit 1, so the retransmission flag is set in step 137. Set. On the other hand, if the value is "1", it means that the communication has been normally performed, and thus the retransmission flag is reset in step 138.

In the following step 140, the retransmission flag is checked. Then, if it is reset, new data is set in step 144, while if it is set, the current transmission data is left as it is in step 146, and the process proceeds to step 180.

B. Operation of Terminal Unit In the terminal unit 5, the start signal of the voltage mode sent from the central processing unit 1 in step 202 of FIG. 17 is sent by the processing of step 104 of FIG. 20 of the central processing unit 1. If it is a start signal at the time of central activation, the process proceeds to step 204 in FIG. 21 to receive transmission data such as destination address ADR and control signal CNT sent from the central processing unit 1 following the start signal at central activation. To do. And step 2
At 06, it is judged whether there is an abnormality in the received data. If there is any abnormality, the process proceeds to step 232. If there is no abnormality, step 2
Proceed to 08.

In step 208, it is determined whether the destination address ADR matches its own address. If the destination address ADR does not match the self-address, the subsequent control signal CNT is sent to another terminal device 5. In this case, proceed to step 232.

In step 232, "0" is set to the last bit of the returned data, and then the process returns to step 202. In this step 202, the next start signal is awaited.

On the other hand, when the destination address ADR and the self address match in step 208, "1" is set to the last bit of the return signal in step 212, and then steps 214 to 230
Execute the return processing of.

Return processing At the time of return processing, first, in step 214, the control variable n is set to 1
And waits until a sync signal is received in step 216. If the synchronization signal is received in step 216, after waiting for a predetermined time (eg, 50 μS) in step 218, it is checked in step 220 whether the nth bit (return signal) of the return data is “1”. judge. If it is "1", a current mode return signal of level "1" is sent from the transmitting circuit 53 to the transmission line 3 in step 224, and then the process is step 226.
Proceed to. The return signal in this current mode is sent to the central processing unit 1
Is received (step 114 in FIG. 20) and converted into a voltage mode signal (steps 118 to 124). On the other hand, if the nth bit of the return data is “0” in step 220, the current mode return signal of “0” is the same as no signal.
The current mode signal transmission process of step 224 is skipped, and the process proceeds directly from step 220 to step 226.

In step 226, the control variable n is incremented, and the subsequent step 230
At, it is determined whether transmission of all the bits of the return data has been completed. If the transmission of all the bits has not been completed, the process returns to step 216, and the processes of steps 216 to 230 are repeated for the next bit (return signal). on the other hand,
If the transmission of all the bits is completed, the return processing is terminated and the process returns to step 202.

In this embodiment, as shown in FIG. 22, one bit is added to the end of the return data, and the last bit, that is, the nth bit is used as a status bit for reception and return of the terminal device 5, and during normal communication. Sets the last bit to "1". Therefore, the central processing unit 1 receives the current mode of the level "1" as the last bit,
It can be determined that the transmission was successful.

In the above description, the status bit added to the final part of the transmission signal is set to "1" when the transmission ends normally, but this status bit is set to "1" when a transmission error occurs. Set and in the central processing unit,
The status bit “1” may be used to detect the occurrence of an error.

As described above, according to the third embodiment, the central processing unit can determine whether the transmission is terminated midway due to a transmission error, a failure, or the like, and when the regular transmission is completed.
Erroneous control can be prevented.

Furthermore, according to the system of this embodiment, collision processing in the case of random transmission can be suitably implemented. That is, when the central processing unit 1 detects that a plurality of terminal activations collide, first, the start signal ST and the mode signal MO
D, Poll all activation terminals consisting of dummy address ADR specified by all terminals. At this time, each terminal 5 is divided into several groups, and the central processing unit 1 sends back the return signal RPI having the same number of bits as the number of groups.
The sync signal SYNC is sent out in the voltage mode so that is sent back. The collision detection in the central processing unit 1 can be performed based on, for example, the status signal or by detecting the disturbance of the received signal.

FIG. 23 (a) shows the polling signal from the central processing unit 1 for the first time after the collision detection. In the figure, the return signal RP
I is the signal RPV converted to voltage mode by the central processing unit 1.
Is displayed. Here, the terminal device 5 is divided into eight according to the value x of the upper 3 bits of its own address, and the synchronization signal SYNC is also sent so as to send back an 8-bit return signal.

That is, in response to the first polling, each activation terminal device 5 responds to the group to which it belongs, for example, if it is the xth group, the current mode return signal RPI of the "1" level only at the xth bit. To occur. As a result, the central processing unit 1 can detect which group of the terminal devices 5 has been activated. Here, an example is shown in which the terminals of the third group (the upper 3 bits are 010) and the fourth group (the upper 3 bits are 011) are activated.

From the second time onward, polling is performed by specifying the detected group. That is, in the above example, the address signal AD
First, 010 (or 011) is set in the upper address of R, a dummy address is set in the lower address, and the second polling is performed. On the other hand, in the terminal device, only the upper address 010 (or 011) generates the "1" level current mode return signal RPI at the timing according to the value of the 4th to 6th bits of the self address. . By performing the polling twice, the central processing unit 1 can detect the upper 6 bits of one address of the activation terminal.

FIG. 23 (b) shows a polling signal from the central processing unit 1 after the second time after the collision detection. According to the figure, the second
The 3rd group (the value of 3 bits to be detected is 001) is generating the return signal. Therefore, if this is the second polling, it can be detected that the address is 010001 ... For one (or a plurality) of the activation terminals. Similarly, one of 512 (9-bit) addresses can be detected by polling three times.

[Fourth Embodiment] FIGS. 24 to 29 are for explaining a fourth embodiment.

In the fourth embodiment, in the signal transmission system of FIG. 1, the central processing unit 1 of FIG.
It is replaced with the central processing unit 1 shown in the figure.

FIG. 24 shows a functional block configuration of the central processing unit 1 according to the fourth embodiment. When the current mode signal is sent from the terminal to the central processing unit, the central processing unit 1 in FIG. 2 inverts the output of the flip-flop circuit 19 twice for the rising and the falling of one signal. It converted one current mode signal into one voltage panel. On the other hand, the central processing unit 1 of FIG. 24 uses the rising edge detection circuit 16 instead of the differentiating circuit 15 to invert the output of the flip-flop circuit 19 only at the rising edge.
Further, as shown in FIG. 25, a synchronization signal is generated for each bit of the returned data from the terminal or the terminal data, and the flip-flop circuit 19 is reset at the falling edge of this synchronization signal. FIG. 25 (a) is a line voltage waveform diagram of the transmission line 3 when the flip-flop circuit 19 is not provided.
FIG. 25 (b) is a voltage waveform diagram in the fourth embodiment. The rise detection circuit 16 and the flip-flop circuit described above.
The functions such as 19 are all realized by the control program of the CPU 21.

Next, the operation of the system whose configuration is shown in FIGS. 1, 6, 7, and 24 will be described with reference to the flowcharts in FIGS. 26 and 27.

The central processing unit 1, the terminal unit 5 and the monitor display panel 7 start to operate according to a control program stored in each CPU when the respective power supplies are turned on. First,
After initializing the various memories and registers etc. built in the CPU, the central processing unit 1 is shown in the flowchart of FIG. 26, the terminal device 5 is shown in the flowchart of FIG. 27, and the monitoring display panel 7 is explained previously. Each infinite loop process shown in the flowchart of FIG. 11 is executed.

A. Operation of central processing unit Referring to FIG.
At 102, the presence or absence of start data is determined. If there is data to be sent to the terminal, that is, activation data, step 104
~ 142 central activation (parent activation) processing is executed, and if there is no activation data, normal mode processing of steps 150 to 180 is executed.

Central start-up processing In the central start-up processing, first, in step 104, a start signal ST, a signal destination terminal address ADR, and a control signal (start-up data) as shown in FIG. The transmission data composed of CNT or the like is sent from the drive circuit 13 to the transmission line 3 in the voltage mode. This transmission of the transmission data is performed one bit each time the processing of step 104 is passed once. The next step 106 is a step for determining whether or not the process of step 104 is repeated a predetermined number of times corresponding to the number of bits of transmission data. If the number of processes of step 104 is less than the predetermined number of times, the process is performed. Return to step 104. When the process of step 104 is repeated a predetermined number of times and a voltage mode signal of a predetermined number of bits is transmitted, it is determined in step 106 that the transmission has ended, and the process proceeds to the next step 110.

In step 110, a synchronization signal composed of voltage pulses of level "1" is generated. Then, in step 112, the output of the current detection circuit 12 is fetched, and in step 114, the presence or absence of the current mode signal from the terminal is determined. Similar to each of the above-described embodiments, also in this embodiment, the terminal 5 sends a current mode signal if one bit (return signal or terminal signal) of data to be sent is "0", but "0"", The current mode signal is not sent. Therefore, here, when the current mode signal is not detected within a predetermined time (for example, 600 μS), it is confirmed that 1 bit (return signal) corresponding to the section to which the predetermined time of the data to be transmitted belongs is “0”. If it is detected, it means that the bit (return signal) is “1”.

If it is determined that there is a return signal in step 114, after the output voltage from the drive circuit 13 is inverted in step 118, if no return signal is detected, step 118 is skipped, that is, The process proceeds directly to step 132 without inverting the output voltage.

In step 132, it is determined whether the return from the terminal has been completed. If the process of generating the synchronization signal (step 110) and receiving the return signal (step 112) has not been completed for all the bits of the return data, the return has not yet been completed, so return from step 132 to step 110, The processing of steps 110 to 132 is repeated.

On the other hand, when the processing of steps 110 to 132 has been executed the same number of times as the number of bits of the returned data, it is determined in step 132 that the return from the terminal device has been completed, and the processing proceeds to step 140. In step 140, it is determined whether the returned data is normal. This determination can be performed, for example, by returning the same signal as the transmitted control signal CNT as an acknowledgment ACK and determining whether or not this acknowledgment ACK and the control signal CNT transmitted by itself match.
Alternatively, as shown in the third embodiment, at the end of the return data from the terminal device, the normal transmission / reception of the terminal device /
It is also possible to add a status signal indicating the abnormality detection result and make the determination in step 140 depending on whether or not the status signal is received.

If the returned data is normal, the start data is cleared in step 142 to cancel the start, and then step 102
Return to.

On the other hand, if the return data is abnormal, step 142 is skipped and step 140 directly returns to step 102. In this case, the startup data remains as is, so step
At 102, it is determined that there is start data, and the central start process is executed again. That is, this central activation process is repeated until the activation data is normally transmitted.

Normal Mode Processing If it is determined in step 102 that there is no startup data, then in step 150, the first synchronization signal with the start signal for starting the terminal as shown in FIG. 28 (1) is transmitted, and then in step 154. Then, it is determined whether or not the current mode activation signal is transmitted from the terminal device. If there is no response from any of the terminals for the predetermined time (for example, 600 μS) to the synchronization signal following the first start signal, it means that the terminal has not been activated, and the process returns to step 102.

On the other hand, when the terminal activation signal as shown in FIG. 28 (3) is detected in step 154, it is determined that the terminal has been activated, the process proceeds to step 156, and the normal mode process of steps 156 to 180 is executed. .

In the normal mode processing, first, the first synchronizing signal is sent in step 156, and then the output of the current detection circuit 12 is fetched in step 158.

As described above, in this embodiment, a predetermined time (for example,
No current mode signal within 600 μS means that one bit of the terminal data corresponding to the section to which the predetermined time belongs is “0”, and if there is a current mode signal, that bit is “1”.
Means that. In step 160, the output of the fetched current detection circuit 12 is inspected. If the current mode signal is detected, the bit (terminal signal) corresponding to the current timing of the terminal data is "1". Therefore, the output voltage from the drive circuit 13 is inverted in step 164, and then the process is performed. Proceed to step 180 of.

On the other hand, if the terminal signal is not received even after the lapse of the predetermined time in step 160, the bit corresponding to the current timing of the terminal data is “0”, and thus the processing of step 164 is skipped and the processing from step 160 is started. As it is, step 180
Proceed to. In this case, the output voltage from the drive circuit 13 to the transmission line 3 is not inverted.

In step 180, a synchronization signal transmission process (step 156) and a reception process (step 1) for all bits of the terminal data.
58) and signal presence / absence determination processing (step 160) and the like are determined. If these processes are not completed, the process is returned to step 156 and the processes of steps 156 to 180 are repeated.

When the processes of steps 156 to 180 are repeated by the same number as the number of bits of the terminal data, it is determined that the reception is completed in step 180,
The process is returned to step 102.

B. Operation of Terminal Device Referring to FIG. 27, the terminal device 5 first determines in step 202 whether or not a central activation signal in the voltage mode is transmitted from the central processing unit. Figure 26 Step from central processing unit
If the central activation signal by the process of 104 is transmitted, the process proceeds to step 204 and the return process of steps 204 to 230 is executed. On the other hand, if not sent, step 25
At 0, the presence or absence of startup data is determined. If there is data to be sent to the central processing unit, that is, activation data, step
Execute the terminal activation (internal activation) processing consisting of the circulation processing of 256 to 280. If the central activation signal has not been transmitted in step 202 and there is no terminal data to be transmitted from the central processing unit itself, the process returns to the first step 202.

Return processing At the time of return processing, voltage mode transmission data sent from the central processing unit based on the output of the receiving circuit 52 in the circulation processing of steps 204 and 210 (steps 104 to 106 in FIG. 26) is subjected to this circulation processing. One bit is received each time. When the reception of the predetermined number of bits is completed, the process proceeds from step 210 to step 216 and waits until the synchronization signal is received in step 216. When the synchronization signal is received, after waiting for a predetermined time (for example, 50 μS) in the following step 222, 1 bit (return signal) of the return data is sent from the transmitting circuit 53 to the transmission line 3 in the current mode in step 224. This return signal in the current mode is received by the central processing unit (step 112 in FIG. 26), which reverses the output voltage mode from the central processing unit (step 11 in the same figure).
8).

In step 228, the voltage mode signal of the transmission line 3 is received, and it is determined whether or not the received signal matches the return signal transmitted immediately before.

If they match, it means that the return signal sent in step 224 is received by the central processing unit and the voltage mode of the transmission line is inverted, so that the transmission of the bit is normally performed. In the next step 230, it is judged whether or not the normal transmission of all the bits of the return signal is completed. If all bits have not been returned, the process returns to step 216, and the above steps are performed for the next bit (return signal).
Repeat steps 216-230. On the other hand, if all bits have been returned, the return processing is terminated and the step
Return to 202.

If the return signal and the reception signal do not match in content in step 228, the bit of the return data (return signal) has not been correctly received by the central processing unit.
The process directly returns from step 228 to step 202. In this case, the central processing unit cannot obtain the return data of a predetermined number of bits (step 140 in FIG. 26). For this reason, the activation canceling process (step 142 in the same step) is skipped, and the central activation process is executed again. Therefore, the terminal device again executes the return processing, and the central processing of the central processing unit and the return processing of the terminal device in response thereto are repeated until the return data is normally transmitted. It will be.

Terminal Start-up Processing During this terminal start-up processing, in step 256, the central processing unit waits for reception of the synchronization signal transmitted in step 150 or step 156 in FIG. When this synchronization signal is received, the following step 258 is performed for a predetermined time (for example, 50 μ).
S) After waiting, in step 260, 1 bit (terminal signal) of the terminal data is sent from the transmission circuit 53 to the transmission line 3 in the current mode. This current mode terminal signal is received by the central processing unit (FIG. 26, step 160), and the output voltage mode from the central processing unit to the transmission line is reversed (step 164).

In step 268, the voltage mode signal of the transmission line 3 is received and it is determined whether or not the received signal matches the terminal signal transmitted immediately before. If they match, step 260
Since the voltage mode of the transmission line in which the terminal signal sent in step 2 is received by the central processing unit is inverted, it means that the transmission of that bit of the terminal data has been normally performed.

In the next step 270, it is determined whether or not the normal transmission of all bits of the terminal signal is completed. If the transmission of the terminal signal for all the bits has not been completed, the process returns to step 256, and the processes of steps 256 to 270 are repeated for the next bit (terminal signal) of the terminal data. On the other hand, if the signal transmission for all the bits is completed, this terminal start-up process is completed and the process returns to step 202.

On the other hand, if the contents of the current mode signal transmitted in step 260 and the voltage mode signal checked in step 268 are different, it is determined that the current mode signal transmitted from the terminal device was not correctly received by the central processing unit. Then, the circulation process is interrupted in step 268 and the process returns to step 202. In this case, the activation data of the terminal remains,
When the start signal for starting the terminal is sent from the central processing unit (step 150 in FIG. 26) and the process proceeds from step 202 to step 250, it is determined in this step 250 that there is starting data, and this terminal starting process is executed. Will be executed again. That is, this terminal activation process is repeated until the activation data is normally transmitted to the central activation process.

FIG. 29 shows the synchronization signal SYNC sent from the central processing unit.
And an example of the timing relationship between the current mode signal RPI sent from the terminal and the voltage mode signal PRV sent from the central processing unit in response to receiving the current mode signal RPI.

In the example of the figure, the time from the fall of the synchronous clock SYNC to the sending of the current mode signal RPI in the terminal device is 50 μS at maximum.
And. The time from the detection of the current mode signal RPI to the reversal of the voltage polarity (transmission of the voltage mode signal PRV) in the central processing unit is 50 μS at maximum, and the maximum signal delay time by the repeater or the like is 300 μS.

[Fifth Embodiment] FIGS. 30 to 33 are for explaining a fifth embodiment.

The fifth embodiment is the same as the signal transmission system of FIG. 1 except that the central processing unit 1 of the configuration shown in FIG. 24 according to the fourth embodiment is replaced with the central processing unit 1 of the configuration shown in FIG. is there.

FIG. 30 shows a functional block configuration of the central processing unit 1 according to the fifth embodiment. In the central processing unit 1 of FIG. 24, when the current processing mode signal from the terminal is detected in the central processing unit, the output of the flip-flop circuit 19 is immediately inverted at the rise of this detection signal. On the other hand,
The central processing unit 1 shown in FIG. 30 additionally includes an AND circuit 17,
The flip-flop circuit is a logical component output from the AND circuit 17 according to the output of the rising detection circuit 16 and the pulse signal generated in the signal processing device 11 with a certain time delay from the synchronization signal.
The output of 19 is inverted. FIG. 31 (a) is a line voltage waveform diagram of the transmission line 3 when the flip-flop circuit 19 is not provided,
FIG. 31 (b) is a voltage waveform diagram in the fifth embodiment. The functions of the rising edge detection circuit 16, the AND circuit 17, the flip-flop circuit 19, etc. are all realized by the control program of the CPU 21.

Next, the operation of the system whose configuration is shown in FIG. 1, FIG. 6, FIG. 7 and FIG. 30 will be described with reference to the flowcharts of FIG. 32 and FIG.

The central processing unit 1, the terminal unit 5 and the monitor display panel 7 start to operate according to a control program stored in each CPU when the respective power supplies are turned on. First,
After initializing the various memories and registers built in the CPU, the central processing unit 1 is shown in the flow chart of FIG. 32, the terminal 5 is shown in the flow chart of FIG. 33, and the monitor display panel 7 is explained previously. Each infinite loop process shown in the flowchart of FIG. 11 is executed.

A. Operation of central processing unit Referring to FIG. 33, the central processing unit 1 starts with step
At 102, the presence or absence of start data is determined. If there is data to be sent to the terminal, that is, activation data, step 104
~ 142 central activation (parent activation) processing is executed, and if there is no activation data, normal mode processing of steps 150 to 180 is executed.

Central start-up processing In the central start-up processing, first, in step 104, a start signal ST, a destination terminal address ADR and a control signal (start-up data) as shown in FIG. ) The transmission data composed of CNT or the like is sent from the drive circuit 13 to the transmission line 3 in the voltage mode. This transmission of the transmission data is performed one bit each time the processing of step 104 is passed once. The next step 106 is a step for determining whether or not the process of step 104 is repeated a predetermined number of times corresponding to the number of bits of transmission data. If the number of processes of step 104 is less than the predetermined number of times, the process is performed. Return to step 104. When the process of step 104 is repeated a predetermined number of times and a voltage mode signal of a predetermined number of bits is transmitted, it is determined that the transmission is completed in step 106,
The process proceeds to the next step 110.

In step 110, a synchronization signal composed of voltage pulses of level "1" is generated. Then, in step 112, the output of the current detection circuit 12 is fetched, and in step 114, the presence or absence of the current mode signal from the terminal is determined. Similar to each of the above-described embodiments, also in this embodiment, the terminal 5 sends a current mode signal if one bit (return signal or terminal signal) of data to be sent is "0", but "0"", The current mode signal is not sent. Therefore, here, when the current mode signal is not detected within a predetermined time (for example, 600 μS), it is confirmed that 1 bit (return signal) corresponding to the section to which the predetermined time of the data to be transmitted belongs is “0”. If it is detected, it means that the bit (return signal) is “1”.

If it is determined in step 114 that the return signal is present, after waiting for a predetermined time τ (eg, τ = 100 μS) in step 116, the output voltage from the drive circuit 13 is inverted in step 118 to perform the process in step 132. Proceed to. As a result, when the current mode signal is detected, the voltage mode signal is inverted with a delay of a fixed time τ from the synchronization signal. Meanwhile, step
If the return signal is not detected in 114, step 118 is skipped, that is, the process directly proceeds to step 132 without inverting the output voltage from the drive circuit 13.

In step 132, it is determined whether the return from the terminal has been completed. If processing such as synchronization signal generation (step 110) and return signal reception (step 112) has not been completed for all bits of the return data, step 132 to step 1
Returning to 10, the processing of steps 110 to 132 is repeated.

On the other hand, when the processing of steps 110 to 132 has been executed the same number of times as the number of bits of the returned data, it is determined in step 132 that the return from the terminal device has been completed, and the processing proceeds to step 140. In step 140, it is determined whether the returned data is normal. This determination can be performed, for example, by returning the same signal as the transmitted control signal CNT as an acknowledgment ACK and determining whether or not this acknowledgment ACK and the control signal CNT transmitted by itself match.
Alternatively, as shown in the third embodiment, at the end of the return data from the terminal device, the normal transmission / reception of the terminal device /
It is also possible to add a status signal indicating the abnormality detection result and make the determination in step 140 depending on whether or not the status signal is received.

If the returned data is normal, the start data is cleared in step 142 to cancel the start, and then step 102
Return to.

On the other hand, if the return data is abnormal, step 142 is skipped and step 140 directly returns to step 102. In this case, the startup data remains as is, so step
At 102, it is determined that there is start data, and the central start process is executed again. That is, this central activation process is repeated until the activation data is normally transmitted.

Normal Mode Processing If it is determined in step 102 that there is no startup data, then in step 150, the start signal for starting the terminal and the first synchronization signal as shown in FIG. 28 (1) are transmitted, and step
At 154, it is determined whether or not a current mode activation signal is transmitted from the terminal device. If there is no response from any of the terminals for the predetermined time (for example, 600 μS) to the synchronization signal following the first start signal, it means that the terminal has not been activated, and the process returns to step 102.

On the other hand, when the terminal activation signal as shown in FIG. 28 (3) is detected in step 154, it is determined that the terminal has been activated, the process proceeds to step 156, and the normal mode process of steps 156 to 180 is executed. .

In the normal mode processing, first, the first synchronizing signal is sent in step 156, and then the output of the current detection circuit 12 is fetched in step 158.

As described above, in this embodiment, a predetermined time (for example,
No current mode signal within 600 μS means that one bit of the terminal data corresponding to the section to which the predetermined time belongs is “0”, and if there is a current mode signal, that bit is “1”.
Means that. In step 160, the output of the fetched current detection circuit 12 is inspected. Then, if the current mode signal is detected, the bit (terminal signal) corresponding to the current timing of the terminal data is "1".
At a predetermined time τ (for example, τ = 100 μS), the output voltage from the drive circuit 13 is inverted at step 164, and then the process proceeds to step 180. These steps 160
By the processing of ~ 164, when the current mode signal is detected,
The voltage mode signal is inverted with a delay of τ from the synchronizing signal.

On the other hand, if the terminal signal is not received even after the lapse of the predetermined time in step 160, the bit corresponding to the current timing of the terminal data is “0”, and thus the processing of step 164 is skipped and the processing from step 160 is started. As it is, step 180
Proceed to. In this case, the output voltage from the drive circuit 13 to the transmission line 3 is not inverted.

In step 180, a synchronization signal transmission process (step 156) and a reception process (step 1) for all bits of the terminal data.
58) and signal presence / absence determination processing (step 160) and the like are determined. If these processes have not been completed, the process returns to step 156 and the above step 1
Repeat the process from 56 to 180.

When the processes of steps 156 to 180 are repeated by the same number as the number of bits of the terminal data, it is determined that the reception is completed in step 180,
The process is returned to step 102.

B. Operation of Terminal Device Referring to FIG. 33, the terminal device 5 first determines in step 202 whether or not the central start signal in the voltage mode is transmitted from the central processing unit. Figure 32 step from central processing unit
If the central activation signal by the process of 104 is transmitted, the process proceeds to step 204 and the return process of steps 204 to 230 is executed. On the other hand, if not sent, step 25
At 0, the presence or absence of startup data is determined. If there is data to be sent to the central processing unit, that is, activation data, step
Execute the terminal start (child start) process consisting of 256 to 280 cyclic processes. If the central activation signal has not been transmitted in step 202 and there is no terminal data to be transmitted from the central processing unit itself, the process returns to the first step 202.

Return processing At the time of the return processing, the 32nd processing from the central processing unit is performed based on the output of the receiving circuit 52 in the circulation processing of step 204 and step 210.
The voltage mode transmission data sent by the process of step 104 in the figure is received one bit at each time of this cyclic process. When the reception of the predetermined number of bits is completed, the process proceeds from step 210 to step 216 and waits until the synchronization signal is received in step 216. When the synchronization signal is received, 1 bit (return signal) of the return data is sent from the transmitting circuit 53 to the transmission line 3 in the current mode in the following step 224. This return signal in the current mode is received by the central processing unit (step 112 in FIG. 32), which reverses the output voltage mode from the central processing unit (step 11 in the same figure).
8).

In step 228, the voltage mode signal of the transmission line 3 is received, and it is determined whether or not the received signal matches the return signal transmitted immediately before.

If they match, it means that the return signal sent in step 224 is received by the central processing unit and the voltage mode of the transmission line is inverted, so that the transmission of the bit is normally performed. In the next step 230, it is judged whether or not the normal transmission of all the bits of the return signal is completed. If all bits have not been returned, the process returns to step 216, and the above steps are performed for the next bit (return signal).
Repeat steps 216-230. On the other hand, if all bits have been returned, the return processing is terminated and the step
Return to 202.

If the return signal and the reception signal do not match in content in step 228, the bit of the return data (return signal) has not been correctly received by the central processing unit.
The process directly returns from step 228 to step 202. In this case, the central processing unit cannot obtain return data of a predetermined number of bits (step 140 in FIG. 32). For this reason, the activation canceling process (step 142 in the same step) is skipped, and the central activation process is executed again. Therefore, the terminal device again executes the return processing, and the central processing of the central processing unit and the return processing of the terminal corresponding thereto are repeated until the return data is normally transmitted. It will be.

Terminal Start-up Processing During this terminal start-up processing, in step 256, the central processing unit waits for reception of the synchronization signal sent out in step 150 or step 156 in FIG. When this synchronizing signal is received, in the following step 260, 1 bit (terminal signal) of the terminal data is sent from the transmission circuit 53 to the transmission line 3 in the current mode. This current-mode terminal signal is received by the central processing unit (step 160 in FIG. 32), and the output voltage mode from the central processing unit to the transmission line is reversed (step 16 in the same step 16).
Four).

In step 268, the voltage mode signal of the transmission line 3 is received and it is determined whether or not the received signal matches the terminal signal transmitted immediately before. If they match, step 260
Since the central processing unit received the terminal signal sent in step 1 and the voltage mode of the transmission line was inverted, it means that the transmission of that bit of the terminal data was performed normally. In the next step 270, it is determined whether or not the normal transmission of all bits of the terminal signal is completed. If the transmission of the terminal signal has not been completed for all bits, the process returns to step 256, and the processes of steps 256 to 270 are repeated for the next bit (terminal signal) of the terminal data. On the other hand, if the normal signal transmission for all the bits is completed, the terminal starting process is canceled in step 280 and the process returns to step 202.

On the other hand, if the contents of the current mode signal transmitted in step 260 and the voltage mode signal checked in step 268 are different, it is determined that the current mode signal transmitted from the terminal device was not correctly received by the central processing unit. Then, the circulation process is interrupted in step 268 and the process returns to step 202. In this case, the activation data of the terminal remains,
When the start signal for starting the terminal is sent from the central processing unit (step 150 in FIG. 26) and the process proceeds from step 202 to step 250, it is determined in this step 250 that there is starting data, and this terminal starting process is executed. Will be executed again. That is, this terminal activation process is repeated until the activation data is normally transmitted to the central activation process.

[Sixth Embodiment] FIGS. 34 to 36 are for explaining the embodiment of FIG.

The sixth embodiment is the same as the signal transmission system of FIG. 1, except that the central processing unit 1 of the configuration shown in FIG. 13 according to the second embodiment is replaced with the central processing unit 1 of the configuration shown in FIG. is there.

FIG. 34 shows the functional blocks of the central processing unit 1 according to the sixth embodiment. The central processing unit 1 shown in FIG. 34 is provided with a fall detection circuit 16 'instead of the differentiating circuit 15 in the central processing unit shown in FIG. With this configuration, the central processing unit 1 sends the synchronization signal SYNC, and the synchronization signal SYNC
When a current mode return signal (or terminal signal) RPI is sent from the terminal 5 in response to SYNC, in the central processing unit 1, the current detection circuit 12 outputs an H level voltage in accordance with the current RPI. Furthermore, the return signal RPI from the terminal device 5
When is finished, the output of the current detection circuit 12 becomes L level. The fall detection circuit 16 'detects a fall when the output of the current detection circuit 12 changes from H level to L level. The flip-flop circuit 19 is triggered by this falling detection signal to invert the output.

FIG. 35 (b) shows the line voltage waveform of the transmission line 3 in the sixth embodiment. It should be noted that FIG. 15A shows a line voltage waveform of the transmission line in the conventional example similar to that shown in FIG. Further, FIG. 35 (c) shows the current waveform of the return signal from the terminal 5 in the sixth embodiment.

In the sixth embodiment, when the current mode signal RPI is output from the terminal device 5, the voltage mode of the transmission line 3 is switched only when the current mode signal RPI ends. On the other hand, in the second embodiment, the voltage mode of the transmission line 3 is switched every time a change in the current mode signal RPI output from the terminal 5 is detected. In this case, the current mode signal RPI is changed. May be distorted.

Returning to FIG. 34, the flip-flop circuit 19 has its output reset by the fall of the synchronizing signal output from the synchronizing signal generating circuit 18, and is also set to a predetermined output state by the signal processing circuit 11 if necessary. Or it is reset.

Flip-flop circuit 19 and fall detection circuit of FIG. 34
The functions such as 16 'are all realized by the control program of the CPU 21. FIG. 36 is a flowchart showing a control program for realizing the above functions. This flowchart is obtained by removing the processing in step 118 from that of FIG. Therefore, in the sixth embodiment, the central processing unit 1 and the terminal 5 have been described above with reference to FIGS. 16 to 19 except that the central processing unit 1 does not perform the output voltage inverting operation of step 118. Works exactly the same as.

In this way, the central processing unit 1 sends one or a plurality of synchronization signals during the signal waiting period from the terminal device 5,
On the side, the current mode return signal or the terminal signal is sent at the timing according to the synchronizing signal, and the central processing unit detects the fall of the return signal or the terminal signal to invert the voltage mode of the transmission line. As a result, the synchronization pulse is sent from the central processing unit side, so the timing is easy to take.

Since the central processing unit inverts the voltage mode of the transmission line after detecting the current mode signal, it can be confirmed at any position of the transmission line whether the data was correctly received by the predetermined terminal device, that is, which terminal device and monitoring display panel. You can also check.

In addition to the same advantages as those of the second embodiment, since the polarity reversal timing and the current mode signal do not overlap, distortion of the current mode signal does not occur.

The effect is obtained.

[Advantages of the Invention] According to the inventions of claims 1 and 2, the central processing unit inverts the polarity of the transmission signal when detecting a change in the transmission signal in the current mode and sends it out. It becomes possible to detect the signal of another terminal regardless of the connection position of the terminal. In addition, since it is not necessary to send and receive a special answer signal corresponding to the transmission signal sent from the terminal device, a decrease in transmission rate is not induced.

Further, according to the invention described in claim 2, in addition to the above-mentioned effect, there is an effect that the display board can be connected to an arbitrary position of the transmission line, so that suitable random transmission can be performed.

Further, according to the invention described in claims 3 to 6, the central processing unit inverts the polarity of the transmission signal in accordance with the change of the return signal in the current mode or the detection of the presence of the return signal, and transmits the signal. Therefore, it becomes possible to detect the signal of another terminal regardless of the connection position of the terminal to the transmission line. In addition, since it is not necessary to send and receive a special answer signal corresponding to the transmission signal sent from the terminal device, a decrease in transmission rate is not induced. Furthermore, since the transmission timing of the return signal from the terminal is determined based on the synchronization signal,
This has the effect of facilitating transmission timing adjustment.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a signal transmission system according to a first embodiment of the present invention, FIG. 2 is a functional block diagram of a central processing unit in the system of FIG. 1, and FIG. FIG. 4 is an explanatory view of a transmission signal format of the system of FIG. 1, FIG. 4 is a functional block diagram of a terminal in the system of FIG. 1, and FIG. 5 is a functional block diagram of a monitor display panel in the system of FIG. 6 is a circuit diagram showing a concrete example of the central processing unit of FIG. 2, FIG. 7 is a circuit diagram showing a concrete example of the terminal unit of FIG. 4, and FIG. 8 is a monitoring display panel of FIG. FIG. 9 is a flow chart showing the operation of the central processing unit of FIG. 6, FIG. 10 is a flow chart showing the operation of the terminal unit of FIG. 7, and FIG. FIG. 12 is a flow chart showing the operation of the monitor display panel shown in FIG. FIG. 13 is a functional block diagram of a central processing unit according to a second embodiment of the present invention, and FIG. 14 is a terminal device according to the second embodiment of the present invention. 15 is a functional block diagram, FIG. 15 is an explanatory diagram of a transmission signal format according to the second embodiment of the present invention, FIGS. 16 and 18 are flowcharts showing the operation of the central processing unit of FIG. 13, 17 and FIG. 19 is a flowchart showing the operation of the terminal device of FIG. 14, FIG. 20 is a flowchart for explaining the operation of the central processing unit according to the third embodiment of the present invention, and FIG. 21 is of the present invention. 22 is a flow chart for explaining the operation of the terminal according to the third embodiment, FIGS. 22 and 23 are explanatory diagrams of a transmission signal format for explaining the operation of detecting a terminal activated at the time of collision in the third embodiment of the present invention, FIG. 24 shows a fourth embodiment of the present invention. FIG. 25 is a functional block diagram of the central processing unit, FIG. 25 is an explanatory view of a transmission signal format according to the fourth embodiment of the present invention, and FIG. 26 is an operation explanation of the central processing unit according to the fourth embodiment of the present invention. 27 is a flowchart for explaining the operation of the terminal according to the fourth embodiment of the present invention, and FIG. 28 is an operation mode of the transmission signal according to the fourth embodiment of the present invention. Another detailed format FIG. 29 is a timing chart for explaining a signal transmission delay in the fourth embodiment of the invention, and FIG. 30 is a functional block diagram of a central processing unit according to the fifth embodiment of the invention. , FIG. 31 is an explanatory diagram of a transmission signal format according to the fifth embodiment of the present invention, FIG. 32 is a flowchart showing the operation of the central processing unit according to the fifth embodiment of the present invention, and FIG. According to the fifth embodiment of the present invention FIG. 34 is a functional block diagram of a central processing unit according to the sixth embodiment of the present invention, and FIG. 35 is a description of a transmission signal format according to the sixth embodiment of the present invention. FIG. 36 and FIG. 36 are flowcharts showing the operation of the central processing unit according to the sixth embodiment of the present invention. 1: Central processing unit 3: Transmission line 5 (5-1, 5-2, 5-3, ...): Terminal device 7: Monitor display panel 9: Load device 11,51: Signal processing circuit 12: Current detection circuit 15 : Differentiation circuit 16: Rise detection circuit 16 ': Fall detection circuit 18,55: Synchronous signal generation circuit 19,57: Flip-flop circuit 20,53: Transmission circuit 21,61,71: CPU 55: Synchronous signal detection circuit RPI : Current mode signal RPV: Voltage mode signal SYNC: Synchronization signal

Claims (6)

[Claims] 1. Transmission means for time-divisionally transmitting a voltage mode transmission signal containing control information and address information for specifying a control target through a transmission line, and a current mode transmission signal input via the transmission line. Current detection means for detecting a change in
And a central processing unit provided with voltage inverting means for inverting the polarity of the transmission signal sent from the transmitting means when the current detection means detects a change in the current mode transmission signal; and a current mode transmission connected to the transmission line. A signal transmission system comprising: a plurality of terminals for time-divisionally transmitting signals to a central processing unit; 2. Transmitting means for time-divisionally transmitting a voltage mode transmission signal including control information and address information for specifying a control target through a transmission line, and a current mode transmission signal input through the transmission line. Current detection means for detecting a change in
And a central processing unit provided with voltage inverting means for inverting the polarity of the transmission signal sent from the transmitting means when the current detection means detects a change in the current mode transmission signal; and a current mode transmission connected to the transmission line. A plurality of terminals for time-divisionally transmitting signals to the central processing unit; a display panel connected to the transmission line for receiving voltage mode transmission signals transmitted from the central processing unit and displaying the transmission contents; A signal transmission system characterized by being provided. 3. A voltage mode transmission signal including control information, address information for specifying a control target, a return request signal for requesting a return signal from the control target, and a synchronization signal indicating the timing of sending back the return signal in a time division manner. Transmitting means for transmitting via the transmission line, current detecting means for detecting a change in the current mode return signal input via the transmission line, and transmitting when the current detecting means detects a change in the current mode return signal A central processing unit provided with voltage inverting means for inverting the polarity of the transmission signal sent from the means; a synchronization signal detecting means for detecting the synchronization signal, and a return request signal when the synchronization signal detecting means detects the synchronization signal A plurality of terminal devices provided with transmitting means for time-divisionally transmitting the responded current mode return signal to the central processing unit via a transmission line; Transmission system. 4. The voltage detecting means, when detecting a change in the return signal in the current mode returned from the terminal in synchronization with the synchronization signal, delays the synchronization signal by a predetermined time and inverts the polarity of the transmission signal. The signal transmission system according to claim 3, wherein the signal transmission system is configured. 5. The voltage reversing means reverses the polarity of the transmission signal at the rising edge of the current mode return signal when detecting a change in the current mode return signal returned from the terminal device in synchronization with the synchronization signal. The signal transmission system according to claim 3, wherein the signal transmission system is configured as follows. 6. A voltage mode transmission signal including control information, address information for specifying a control target, a return request signal for requesting a return signal from the control target, and a synchronization signal indicating the timing of sending back the return signal in a time division manner. Transmitting means for sending out via the transmission line, current detecting means for detecting the presence or absence of the current mode return signal input via the transmission line, and when the current detecting means detects the presence of the current mode return signal,
A central processing unit provided with voltage inverting means for inverting the polarity of the transmission signal sent from the transmitting means after the completion of the reply signal; a synchronizing signal detecting means for detecting the synchronizing signal, and a synchronizing signal detecting means for detecting the synchronizing signal And a plurality of terminals provided with a transmission means for time-sharing the current mode return signal in response to the return request signal and transmitting the current mode return signal to the central processing unit via the transmission line; Transmission system.