JPH07105932B2 - TV synchronization controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TV synchronization controller for compensating for vertical synchronization, and more particularly, to prevent vertical counter reset malfunction due to external noise. The present invention relates to a TV sync controller that resets a vertical counter by a sync pulse.

[Conventional technology]

Conventionally, this type of TV sync controller is configured with only one programmable logic matrix (hereinafter referred to as PLA) that determines the input range (window width) of the vertical sync pulse that resets the vertical counter.

FIG. 2 is a block diagram of a conventional TV synchronization controller showing such an example.

As shown in FIG. 2, the conventional TV synchronization controller is
A sync separation circuit 1 for separating horizontal and vertical sync pulses from a video signal, a phase comparator 2, an LPF 3, a voltage controlled oscillator (hereinafter referred to as a VCO circuit) 4, and a horizontal counter for counting a basic clock generated by a VCO 4. A counter 5, a 1/2 divider 6 that divides the output of the horizontal counter 5 by 1/2, and a vertical counter 9 that counts the horizontal pulse (a signal of 1/2 cycle) that is the output of the horizontal counter 5. , Horizontal and vertical PLA7,10 that specify the rising and falling positions of the output signal
And horizontal and vertical JK flip-flops 8 and 11 for producing horizontal and vertical output signals, respectively, and a window value setting PLA 12 for setting a window value based on a vertical address from a vertical counter 9, NOR gates 15 and 16 that receive the outputs of PLA 12 and delay circuit 14
It has an AND gate 17 which takes the logical product of the output of the NOR gate 15 and the vertical synchronizing pulse which is the output of the sync separation circuit 1. In such a synchronous controller, the phase comparator 2, LP
F3, VCO4, horizontal counter 5, and 1/2 frequency divider 6 constitute a phase locked loop (PLL) 21, and NOR gates 15 and 16 and AND gate 17 constitute a reset signal generation circuit 22.

[Problems to be Solved by the Invention]

The conventional TV sync controller described above has only one PLA12 that determines the input range (window width) of the vertical sync pulse that resets the vertical counter 9. Therefore, if the vertical sync signal comes in before the setting value of the window width setting PLA, the vertical sync signal cannot be fetched and the vertical counter 9 is not reset. Therefore, the vertical synchronization of the TV screen becomes large. It has the drawback of being disturbed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a TV synchronization controller that prevents a synchronization disturbance in the vertical direction of a TV screen due to the vertical counter not being reset.

[Means for Solving the Problems]

The sync controller for TV of the present invention, in order to create a signal of one horizontal cycle and a sync separation circuit that separates horizontal and vertical sync pulses from a video signal input from the outside,
Phase comparator for synchronizing the horizontal sync pulse separated by the sync separation circuit and the signal of one horizontal period, LPF and VCO that oscillates a basic clock by the output of the LPF, and counts the basic clock 1/2 A horizontal counter for producing a signal of a horizontal period, a PLL circuit comprising a 1/2 divider for producing a signal of the one horizontal period from the signal of the half horizontal period of the horizontal counter, and an output from the horizontal counter A vertical counter that counts the signal of the 1/2 horizontal cycle, a horizontal system that outputs the setting pulse indicating the rising position and the falling position for each specified address by using the outputs of the horizontal counter and the vertical counter as an address, and By controlling the rising position and the falling position in accordance with the vertical system PLA and the setting pulses output from the horizontal system and the vertical system PLA, respectively. A horizontal and vertical output JK flip-flop for generating a vertical output signal and a vertical output signal, and a normal window value for outputting a pulse for resetting the vertical counter at an address designated by the output of the vertical counter For setting
A pulse for resetting the vertical counter output from the normal window value setting PLA is output as a reset signal to the vertical counter when the vertical synchronizing pulse separated by the PLA and the synchronous separation circuit is not input. In a TV synchronous controller having a reset signal generating circuit, which is different from the normal window value setting PLA, and as a range for inputting the vertical synchronizing pulse that resets the vertical counter when the vertical cycle becomes short. Another PLA for setting the window value for determining the window value, and the output of the PLA for setting the normal window value and the PLA for setting the other window value between the TV, VTR standard playback and VTR special playback A switch is provided so that even if the vertical cycle of the video signal fluctuates during fast forward playback, Switching the pulse capture width configured to prevent a synchronization disturbance of the vertical system output signal. That is, in the present invention, two window value setting PLs that determine the window width (vertical sync pulse capture range) so that the vertical sync pulse can be captured even when the vertical cycle becomes fast due to fast-forward playback of the VTR or the like.
A and a switch for selecting the output (window width) of the PLA.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a TV synchronization controller showing an embodiment of the present invention.

As shown in FIG. 1, the sync separation circuit 1 inputs a video signal from the outside and outputs a horizontal sync pulse and a vertical sync pulse. The phase comparator 2 and the reduction filter (LPF) 3 and the VCO 4 for inputting the horizontal sync pulse and the signal of one horizontal period from the sync separation circuit 1 include the horizontal counter 5 and the 1/2 divider 6. Phase lock loop circuit (PLL
Circuit) 21 to synchronize the external video signal with the output signal. The VCO 4 of the PLL circuit 21 oscillates a basic clock corresponding to the resolution of the horizontal output signal. The horizontal counter 5 counts the oscillation output of the VCO 4, gives the address of the horizontal PLA 7, and creates the clock of the vertical counter 9 (a signal whose period is 1/2 of that of the horizontal pulse). The horizontal PLA 7 generates pulses corresponding to the rising and falling addresses of the horizontal output signal, that is, a rising setting pulse and a falling setting pulse, and the horizontal output JK flip-flop 8 rises from these rising pulses. It outputs a horizontal output signal whose position up to the down pulse becomes high level.

On the other hand, the vertical counter 9 is the horizontal counter 5 as in the horizontal system.
Output (signal whose period is 1/2 of the horizontal pulse) is counted, and the vertical address is given to the vertical PLA 10. The vertical PLA 10 outputs a pulse corresponding to the rising address and falling address of the vertical output signal, that is, a rising setting pulse and a falling setting pulse, and the vertical output JK flip-flop 11 outputs a rising pulse to a falling pulse. Outputs the vertical output signal in which the positions up to are high level.

Here, the first window value setting PLA12 is a value obtained by subtracting about 10 from the count number (525 for NTSC) corresponding to one vertical cycle, and the second window value setting PLA13 is the vertical cycle advance rate N The number of counts that corresponds to one vertical cycle when% Set the value of each. This allows TV and VTR standard
When the / VTR special playback switching signal is "L" (when receiving a normal TV broadcast or performing VTR standard playback), the switch circuit composed of AND gates 18 and 19 and the inverter 20 R consisting of NOR gates 15 and 16 that pass the output pulse from the first window value setting PLA 12
-S flip-flop is set, only the vertical synchronizing pulse input before and after the count number corresponding to one vertical cycle (525 in NTSC) is fetched through the AND gate 17 which constitutes the reset signal generating circuit 22, and the vertical counter 9 is reset,
The signal input before that is removed as external noise.

On the other hand, when the TV / VTR standard / VTR special playback switching signal is "H" (during VTR fast-forward playback), AND gate 1
With a switch circuit consisting of 8, 19 and inverter 20,
The output pulse from the second window value setting PLA 13 is passed, the RS flip-flop composed of the NOR gates 15 and 16 is set, and it is AND gate 17 even if the cycle of the input vertical synchronizing pulse becomes short. Can be taken out as a reset signal of the vertical counter 9. The RS flip-flop composed of the NOR gates 15 and 16 resets the vertical synchronizing pulse by the signal delayed by the delay circuit 14,
The pulses input until the count number specified by the window value setting PLA again is removed as noise to stabilize synchronization.

〔The invention's effect〕

As described above, the TV synchronization controller of the present invention has a single window value setting PLA and a switch for switching the window width so that the vertical cycle can be shortened even when the vertical cycle is shortened by VTR special playback or the like. Since the capture width of the vertical synchronizing pulse for resetting the counter can be switched, it is possible to prevent the problem that the vertical counter is not reset, that is, the synchronization in the vertical direction is disturbed.

[Brief description of drawings]

FIG. 1 is a block diagram of a TV sync controller showing an embodiment of the present invention, and FIG. 2 is a block diagram of a TV sync controller showing an example of the prior art. 1 ... Synchronous separation circuit, 2 ... Phase comparator, 3 ... LPF,
4 ... VCO, 5 ... Horizontal counter, 6 ... 1/2 divider, 7
...... Horizontal PLA, 8 ...... JK flip-flop for horizontal output, 9 ...... Vertical counter, 10 ...... Vertical PLA, 11 ......
JK flip-flop for vertical output, 12 …… PLA for setting the first window value, 13 …… P for setting the second window value
LA, 14 …… delay circuit, 15, 16 …… NOR gate, 17〜19 ……
AND gate, 20 …… Inverter, 21 …… PLL circuit, 22 ……
Reset signal generation circuit.

Claims (1)

[Claims] 1. A sync separation circuit that separates horizontal and vertical sync pulses from an externally input video signal, and a horizontal sync pulse that is separated by the sync separation circuit to create a signal of one horizontal period. A phase comparator for synchronizing the signal of one horizontal period, an LPF and a VCO that oscillates a basic clock by the output of the LPF, a horizontal counter that counts the basic clock and creates a signal of 1/2 horizontal period, the horizontal A PLL circuit including a 1/2 divider that generates the signal of one horizontal period from the signal of the 1/2 horizontal period of the counter, and a vertical circuit that counts the signal of the 1/2 horizontal period output from the horizontal counter. The output of the counter, the horizontal counter and the vertical counter is used as an address, and a horizontal system and a vertical system that output setting pulses indicating a rising position and a falling position for each designated address. System PLA and horizontal and vertical output J for respectively generating horizontal and vertical output signals by controlling the rising and falling positions in accordance with the set pulses output from the horizontal and vertical PLAs, respectively. A K flip-flop, a normal window value setting PLA that outputs a pulse for resetting the vertical counter at a specified address by using the output of the vertical counter as an address, and the vertical synchronization that is separated by the synchronization separation circuit In a TV synchronous controller having a reset signal generating circuit that outputs a pulse for resetting the vertical counter output from the normal window value setting PLA as a reset signal to the vertical counter when no pulse is input , Different from the normal window value setting PLA and vertical Another window value for setting to determine the window value as a range for inputting the vertical synchronization pulse for resetting the vertical counter when the period becomes shorter
The PLA and the output of the normal window value setting PLA and the other window value setting PLA are TV, VTR standard playback and VTR.
A changeover switch for changing over between special reproduction is provided, and the capturing width of the vertical synchronization pulse is changed over even when the vertical cycle of the video signal fluctuates during fast-forward reproduction, etc., to prevent disturbance of synchronization of the vertical output signal. Synchronous controller for TV characterized by.