JPH07108013B2 - Image enlargement / reduction device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image enlarging / reducing device capable of enlarging or reducing an image.

[0002]

2. Description of the Related Art As an image enlarging / reducing method for enlarging or reducing an image by a pixel density conversion method, SPC has been conventionally used.
Law, logical sum method, nine division method, projection method, etc. are known.

[0003]

As a problem of these conventional methods, there is a noticeable blurring or missing of a line portion, but the biggest problem is a binarized image expressed by the systematic dither method. That is, when enlarging / reducing a halftone image having a periodic structure such as the above, moire fringes are generated. Images that have been binarized using a dither matrix have different characteristics depending on the dither matrix used. Depending on the type of dither matrix used, the image may not be suitable for image enlargement / reduction. There is also. For example, image quality can be obtained by performing binarization processing using a Bayer type dither matrix, or performing enlargement processing on an image obtained by reducing a binarized image using a centralized dither matrix. Will be noticeable.

The present invention has been made in view of this point,
The purpose is to solve the problem at the time of enlarging / reducing a dither image without causing moire fringes even for a binarized image with a periodic structure, and enlarging / reducing easily, and enlarging a high quality image. An object of the present invention is to provide a method for enlarging / reducing a reduced image.

Further, the present invention provides an image enlarging / reducing device which enables an image to be enlarged / reduced and an image quality such as gradation processing can be adjusted for a binarized image by an external operation. To do.

[0006]

An image enlarging / reducing device of the present invention which solves the above problems divides an operation panel and a binary image to be enlarged / reduced into blocks each having a plurality of pixels. Calculation means for obtaining the number of black pixels in a block and outputting the number of pixels as an average density value of each block, and density indicating means for outputting various density conversion signals corresponding to external signals input from the operation panel. , An image processing means for processing the output from the arithmetic means by using the output of the density instructing means to perform density conversion processing, and outputting a new average density value for each block; On the other hand, an image creating means for performing threshold processing by a density pattern to create a matrix pattern, an enlarging / reducing instruction means for outputting an enlarging / reducing magnification signal corresponding to an external signal, and the image Against matrix pattern output from the creating means and is characterized with scaling means for performing scaling processing, in that it consists of.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is a binarization circuit for binarizing an input image signal, and 2 is a memory in which an already binarized image matrix is stored. As the binarizing circuit 1, for example, a binarizing system using a dither matrix is used. 3 is an operation for dividing the binarized image output from the binarization circuit 1 or the memory 2 into blocks composed of a plurality of pixels, obtaining the number of black pixels in each block, and outputting this as the average density value of each block. The circuits (arithmetic means) 4 receive the output of the arithmetic circuit 3 and perform the density conversion processing selected by the output signal of the first instruction circuit 5 on the average density value of each block, for each block. An image processing circuit (image processing means) for obtaining a new average density value. An operation panel 6 gives the first instruction circuit 5 instructions regarding density conversion, gradation pattern, magnification, and the like. The operation panel 6 is composed of, for example, a keyboard and a CRT display section. Reference numeral 7 indicates the first instruction circuit 5 from the new average density value of each block output from the image processing circuit 4.
An image creating circuit (image creating means) that creates and outputs a matrix pattern for each block using the gradation pattern selected by the output signal of An image reconstruction circuit (image reconstruction means) for reconstructing a magnified / reduced image by repeatedly or thinning out a pattern of each block on the magnified / reduced image according to an instruction from the instruction circuit 9 of FIG. is there. The first instruction circuit 5
(A signal for causing the image processing circuit 4 to select a specific density conversion and a signal for causing the image creating circuit 7 to select a specific gradation pattern are output), and an instruction circuit 9 (to the image reconstruction circuit 8). The output of the signal for selecting the repetition of the matrix pattern or the thinning-out process according to the enlargement / reduction ratio constitutes the instructing means.

The image data reconstructed by the image reconstructing circuit 8 is stored in the image memory 10. The operation of the apparatus thus configured will be described below.

The binarization circuit 1 converts an original image A composed of a matrix for each pixel as shown in FIG. 2B into a 4 × 4 dither matrix as shown in FIG. Perform value conversion processing. As a result, a binarized image matrix B as shown in FIG. 2C is obtained. The shaded areas in the figure are black pixels.

The arithmetic circuit 3 receives the binary image matrix data stored in the binary circuit 1 or the memory 2 as shown in FIG. 2C, and calculates the number of black pixels for each block. Ask by. Here, the block is shown in FIG.
The area surrounded by the thick solid line in (c) means 4 in the example in the figure.
One block consists of × 4. In order to reduce the block structure at the time of image enlargement, it is preferable that the block is small, and as shown in the figure, about 4 × 4 is a preferable size. FIG. 3B is a diagram showing the number of black pixels thus obtained.

The image processing circuit 4 includes the arithmetic circuit 3 to FIG.
The calculation processing for receiving the black pixel number data for each block as shown in (b) and converting it to another numerical value is performed. As a calculation method, for example, digital calculation is performed by regarding the data indicating the number of black pixels in each block shown in FIG. 3B as the average density.

In the density conversion in the image processing circuit 4, the operation circuit 6 indicates from the operation panel 6 which density curve to select.
The instruction circuit 5 causes the image processing circuit 4 to select the density curve. In the density conversion itself, the output of the arithmetic circuit 3 and the output of the instruction circuit 5 are addressed (input).
The new density value is obtained by using a look-up table or the like configured with a memory (ROM) that uses the data stored in the address as a new density value (output). As the density curve, for example, the density curves F1 and F in FIG.
If a value such as 2 is used, a large number of gradations can be assigned to the high density side or the low density side. In addition, the above RO
If a density curve is created using a function generator instead of M, various density conversions can be selected.

Density conversion (gradation conversion) in the image processing circuit 4
Is to be instructed from the operation panel 6 when the operator judges that it is necessary, and is not always performed. If a density curve with the same input data and output data is selected, the density conversion is not substantially performed.

The image forming circuit 7 receives the output (new average density value of each block) thus obtained from the image processing circuit 4, and the gradation pattern selected by the output signal from the instruction circuit 5. Is used to create and output a matrix pattern for each block. The specific processing of the image creating circuit 7 is as follows. Here, a case will be described in which the first instruction circuit 5 gives an instruction to the image processing circuit 4 that density conversion is unnecessary, and the output of the arithmetic circuit 3 is output from the image processing circuit 4 as it is. The image forming circuit 7 regards the output of the image processing circuit 4 sent for each block, that is, each numerical value shown in FIG. 3B as an average density value, and 4 × as shown in FIG. Binarization processing is performed using a dither matrix of 4. Taking the first block B ₁ as an example, the average density value is 7. Therefore, the image forming circuit 7 sets only black pixels that are equal to or smaller than 7 of the dither matrix 7 shown in FIG.
Performs binarization conversion and outputs the result. The image processing process shown in FIG. 3 is an example of a gradation pattern.
Using the 4 × 4 dither matrix shown in FIG.
The new average density value threshold processing shown in FIG.
This is a process for obtaining a matrix pattern as shown in (c). The above operation is performed for all blocks. Figure 3
(C) shows the matrix pattern obtained by the image processing process described above. This image creation circuit 7
Specifically, when the Y address is sequentially scanned using the output data of the image processing circuit 4 as the X address, a pattern for one column or one row of the matrix is output every time the address is incremented by 1. Is configured to be.

The image reconstructing circuit 8 reconstructs the image for one screen from the pattern for one column or one row sent from the image forming circuit 7 according to an instruction from the second instruction circuit 9. For example, when obtaining a magnified image, the same column pattern (or row pattern) is repeated as many times as necessary, and when obtaining a reduced image, part of the column pattern (or row pattern) is thinned to re-create the image. Make the configuration. At this time, the repeat start position and end position of the column pattern (or row pattern) on the screen at the time of image enlargement and the allocation position of the column pattern (or row pattern) at the time of image reduction are the second instruction circuit 9
To the image reconstruction circuit 8. Image reconstruction circuit 8
The image pattern for one screen reconstructed by
Stored in 10. The stored enlarged image or reduced image is extracted and image-processed as needed.

FIG. 4 is an electric circuit diagram showing a specific configuration of an image processing circuit section composed of the image processing circuit 4, the image creating circuit 7, the image reconstructing circuit 8 and the second instruction circuit 9. The number of black pixels counted by the arithmetic circuit 3 (see FIG. 1) is input to the threshold value storage ROM 11. This threshold storage R
The OM 11 also has the functions of the image processing circuit 4 and the image creating circuit 7 described above, and is controlled by a threshold value selection signal (output from the instruction circuit 5) which is an address signal to the OM 11.
Both the specific density curve and the gradation pattern are selected, and the density-converted matrix pattern data is sequentially output by the separately input clock CLK.
(Corresponding to the image reconstruction circuit 8). The RA
An address is given to M12 from the address setting ROM 13 (corresponding to the instruction circuit 9). Address setting ROM 13
Are supplied with a magnification signal, a row counter 14 output and a column counter 15 output, and the address setting ROM 13 receives these signals and gives the RAM 12 an address corresponding to the input signal. The row counter 14 has a first clock CLK1.
Is given to the column counter 15 and the second clock CLK2
Are given, and the outputs of these counters are given to the address setting ROM 13 as addresses.

The address setting ROM 13 receives a magnification signal and determines whether to perform image enlargement processing or image reduction processing. Data corresponding to the image enlargement mode and the image reduction mode are stored in advance in the address setting ROM 13. When the address setting ROM 13 confirms which one, the address setting ROM 13 stores the corresponding numerical data. Is output as an address and given to the RAM 12.

On the other hand, the RAM 12 has n × n (n is an integer)
The memory has an address corresponding to the pattern, stores the output of the threshold value storage ROM 11, and outputs the stored data according to the output of the address setting memory 13.
That is, as described above, when the image is enlarged, the same data is output a plurality of times, and when the image is reduced, some addresses are skipped or some data are ignored and output. The image data output in this manner is sequentially stored in the image memory 10 and is configured as an enlarged image or reduced image for one screen.

FIG. 5 is an explanatory diagram of image reconstruction when the original image is reduced to 3/4 times. The pattern shown in the drawing is a pattern created by the image creating circuit 7. FIG. 6 is a diagram showing an example of an image reconstructed from the matrix shown in FIG. FIG. 6A is a diagram showing an example of an enlarged image at 5/4 times, and FIG. 6B is a diagram showing an example of a reduced image at 3/4 times. As is clear from FIGS. 5 and 6, 3/4
At the time of double reduction, the first pattern has pixels in the first, second, and third columns, the second pattern has pixels in the fourth, first, and second columns, and the third pattern has third, fourth, and first columns. Each pixel of the eye. In this example, from the first pattern, in the fourth column,
The columns for the respective patterns are assigned so that the pixels in the third and second columns are thinned out. Further, during the enlargement process, the first pattern is composed of pixels in the first, second, third, fourth, and first columns, and the second pattern is composed of pixels in the second, third, fourth, first, and second columns. It In this case, the repetition start position of each pattern upon reconstruction is the first row in the first pattern, the second row in the second pattern. ． ． In this way, the pixels are reconstructed by shifting them by one pixel.

[0021]

As described in detail above, according to the present invention, no matter what dither matrix the binarized image to be scaled up or down is, The instructing means gives an instruction relating to desired density conversion and selection of a gradation pattern, and even if the binarized image having the optimum characteristics for enlargement or reduction of a target is converted into a binarized image having an appropriate density, Can be enlarged or reduced, so that a high-quality enlarged / reduced image can be easily obtained without generating moire fringes even in a binarized image having a periodic structure.

Further, according to the present invention, by an external operation,
It is possible to obtain an image enlargement / reduction device that enables density adjustment and image quality adjustment such as gradation processing and image enhancement to a binarized image at the same time as enlargement / reduction.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of binarization.

FIG. 3 is an explanatory diagram of numerical conversion.

FIG. 4 is a diagram showing a specific configuration example of an image processing circuit unit.

FIG. 5 is an explanatory diagram of image reconstruction at the time of image reduction.

FIG. 6 is a diagram showing an example of a reconstructed image.

FIG. 7 is a diagram showing an example of a concentration curve.

[Explanation of symbols]

 1 binarization circuit 2 memory 3 arithmetic circuit 4 image processing circuit 5, 9 instruction circuit 6 operation panel 7 image creation circuit 8 image reconstruction circuit 10 image memory 11 threshold value storage ROM 12 RAM 13 address setting ROM 14 row counter 15 column counter

Claims (1)

[Claims] 1. An operation panel and an object of enlargement / reduction 2
The value image is divided into blocks each having a plurality of pixels, the number of black pixels in each block is calculated, and the calculating unit outputs the number of pixels as an average density value of each block, and corresponds to an external signal input from the operation panel. The density instructing means for outputting various density conversion signals described above, and the output of the density instructing means are used to process the output from the arithmetic means to perform density conversion processing, and output a new average density value for each block. Image processing means for performing threshold processing on the new average density value by a gradation pattern to create a matrix pattern, and outputting an enlargement / reduction magnification signal corresponding to an external signal. And an enlarging / reducing means for enlarging / reducing the matrix pattern output from the image creating means. Scaling device of an image.