JPH07109555B2 - Performance information input device and performance device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a performance information input device for automatic performance and a performance device, and more particularly to a technique for searching performance information.

SUMMARY OF THE INVENTION In the present invention, performance information for automatic performance including symbol information indicating a repeat section is stored in a memory, desired symbol information is designated, and symbol information matching the symbol information is stored in the memory. A search is performed from the inside, and information writing or automatic performance is performed from the storage position of the searched symbol information.

[Prior Art] Conventionally, as an automatic performance device having a search function, as shown in, for example, Japanese Patent Application Laid-Open No. 1-180596, the time ratio of a desired performance position to the total performance time (for example, 1 /
(10, 1/20, etc.) and jump (high speed movement) to a storage position corresponding to the ratio, or a stop command is given as shown in, for example, Japanese Patent Laid-Open No. 62-175796. It is known that performance data is read at a audible speed to monitor performance sounds.

[Problems to be Solved by the Invention] Among the above-mentioned conventional techniques, in the one that jumps to a storage position corresponding to a specified ratio, although the data can be quickly moved to the jump destination, the data of the jump destination is any data. It is impossible to know in advance, and it is not possible to perform a search mainly on data.

Further, in the case of reading performance data at an audible speed, the operator can search for the desired performance data by giving a stop command at the timing of the desired performance sound while listening to the performance sound accompanying the data read. However, procedural complexity is inevitable. Moreover, since the read speed is limited to an audible level, it is not swift, and it takes a considerable time to search for data that is distant in terms of address.

An object of the present invention is to make it possible to easily and quickly modify information or start playing the desired performance information.

[Means for Solving the Problem] A performance information input device according to the present invention is: writing means for writing performance information for automatic performance, which includes storage means and symbol information indicating a repeat section, in the storage means in accordance with the progression of music. Means, information designating means for designating the symbol information to be searched among the symbol information written in the storing means, and playing information read from the storing means and compared with the symbol information designated by the information designating means. The writing means writes the performance information from the storage location of the symbol information searched by the searching means. It is what

Further, the performance device according to the present invention specifies storage means for storing performance information for automatic performance including symbol information indicating a repeat section, and symbol information to be searched among the symbol information stored in the storage means. Information designating means, a search means for searching the symbol information matching the symbol information by reading the performance information from the storage means and comparing it with the symbol information designated by the information designating means; And a performance means for automatically performing a performance from the storage position of the stored symbol information according to the performance information of the storage means.

[Operation] According to the performance information input device described above, after designating desired symbol information to search for symbol information matching the symbol information, the performance information is written from the storage position of the searched symbol information. You can Therefore, desired performance information can be corrected easily and quickly.

Further, according to the above-described performance device, after designating desired symbol information and searching for symbol information matching the symbol information,
The automatic performance can be started from the storage position of the searched symbol information. Therefore, the performance can be started easily and quickly from the desired performance information.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to an automatic performance device. In this automatic performance device, performance information input, automatic performance, performance information search, etc. are controlled by a microcomputer. It is like this.

Structure of automatic performance device (FIG. 1) The data bus 10 includes a central processing unit (CPU) 12, a program memory 14, a register group 16, a song memory 18, a pattern memory 20, a tempo clock generator 22, a switch group 24, A display 26, a tone generator (TG) 28, etc. are connected.

The CPU 12 executes various processes in accordance with the programs stored in the memory 14, and these processes will be described later with reference to FIGS. 7 to 15.

The register group 16 includes a large number of registers used in various processes by the CPU 12, and among these registers, those related to the implementation of the present invention will be described later.

The song memory 18 can store 8-bit data for each address, and its data format is as shown in FIG. 2 as an example. In Figure 2, SGP
Is a song address pointer, and as the data SONG (SGP) of the address indicated by this pointer SGP,
Pattern number data as shown in (A), repeat section start symbol data as shown in (B), repeat section end symbol data as shown in (C), song end code data as shown in (D), etc. is there.

The pattern number data of (A) is the most significant bit (MS
B) is 1, and the lower 7 bits represent any of the pattern numbers 01 to 99. The pattern number is predetermined for each performance pattern representing the performance content for one measure, for example.

The repeat section start symbol data in (B) represents the start of the repeat section by setting the upper 2 bits to 1 and the lower 6 bits to 0.
The data content corresponds to "CO _H " in hexadecimal notation.

In the repeat section end symbol data in (C), the upper 2 bits represent the end of the repeat section with 1s and 0s, and the lower 6 bits represent the number of repetitions of 01 to 63.

Song end code data (D) is intended to represent the end of a song by a 1 none of the 8-bit, the data content corresponds to "FF _H" in hexadecimal notation.

In the writing mode, the memory 18 sequentially stores data such as (A) to (C) according to a desired music progression as shown in FIG. 4, and finally stores data (D). . Then, in the play mode, every time the pattern number data is read from the memory 18, the performance pattern corresponding to the pattern number indicated by the pattern number data is designated in the memory 20, and the data constituting the performance pattern is sequentially read. Thus, for example, an automatic performance for one bar is performed, and when the performance for one bar is completed, the next data is read from the memory 18. If the data read at this time is pattern number data, the automatic performance is performed in the same manner as the last time.
If it is the repeat section end symbol data, it returns to the address corresponding to the previously read repeat section start symbol data, and repeats the automatic performance by the number of repetitions indicated by the repeat section end symbol data.

The pattern memory 20 includes pattern storage units 20 (01) to 20 corresponding to pattern numbers 01 to 99 as illustrated in FIG.
(99), and each pattern storage unit has, for example, 1
Performance patterns for each measure are stored. As a representative, the pattern storage unit 20 (01) will be described. In this storage unit, 3-byte event data is sequentially stored as the address indicated by the pattern address pointer PTP progresses, and finally 1-byte pattern end code data PEND is stored.
Is memorized.

In each event data, the first byte is an on / off identifier (key on / off data), the second byte is key code data, and the third byte is timing data. If the on / off identifier is 1, it represents a key-on event,
A value of 0 indicates a key-off event. The key code data represents a key code corresponding to the pitch of a musical sound to be sounded or muted. Timing data is 0 within 1 bar
Represents any of the timing values of ~ 31.

The tempo clock generator 22 generates the tempo clock signal TCL according to the given tempo.
Is supplied to CPU 12 as an interrupt instruction and is used to start the routine of FIG.

The switch group 24 includes various kinds of control switches, and those relevant to the implementation of the present invention are listed below.

(1) Mode switch S1 ... This is for designating a writing mode or a play mode.

(2) Start / stop (ST / SP) switch S2 ... This is for instructing start or stop in the write mode or play mode.

(3) Increment (INC) switch S3 and decrement (DEC) switch S4 ... These switches are for changing and controlling the value of the address pointer SGP described above, and the SGP value is set to 1 each time the switch S3 is operated. Increased,
It is decremented by 1 each time the switch S4 is operated.

(4) Pattern (PAT) designation allowance switch S5 ... This is
This is for enabling the designation of the pattern number.

(5) Numeric keypad S6 ... These keys can individually specify the numbers 0 to 9 and are used to specify the pattern number when the pattern number can be specified by the switch S5, and will be described later. The switch S8 is used to specify the number of repetitions when the end of the repeat section is specified.

(6) Repeat section designating switches S7 and S8 ... Of these switches, S7 is for designating the beginning of the repeat section, and S8 is for designating the end of the repeat section.

(7) Execution (EXE) switch S9 ... This is for instructing execution of writing or reading or execution of search.

(8) Search direction designating switch S10 ... This is for designating a search direction which is either an address value increasing direction (rightward arrow) or an address value decreasing direction (leftward arrow).

(9) Search switch S11 ... This is for designating the search mode, and the designation of the search mode is possible in either the write mode or the play mode. Therefore, it is possible to search for desired performance information in the write mode and correct the performance information, or to search for desired performance information in the play mode and start performance from that performance information.

The display 26 is provided on the switch panel provided with the switch group 24, and has four display parts A to D.

The value of the address pointer SGP is displayed on the display unit A,
The displayed value can be increased or decreased by the switch S3 or S4, respectively.

The display section B displays the pattern number designated by the numeric keypad 6 when the pattern can be designated by the switch S5, and the repeat section start symbol is displayed when the start of the repeat section is designated by the switch S7. When the end of the repeat section is designated by S8, the repeat section end symbol and the number of repeats designated by the numeric keypad S6 are displayed.

The characters "Search" are displayed on the display section C when the search mode is designated by the switch S11.

On the display section D, the search direction designated by the switch S10 is displayed by the letters "F" or "B". Where "F"
And "B" correspond to the address value increasing direction and the address value decreasing direction, respectively.

The TG28 controls the tone signal formation in accordance with the key data (key on / off data and key code data) read from the memory 20, and the tone signal formed by the TG28 is supplied to the sound system 30. Converted to sound.

Example of Performance Progression (FIG. 4) FIG. 4 shows an example of performance data storage in the memory 18 and shows a performance progress situation based on such storage data.

In the memory 18, among the addresses 1 to 16 indicated by SGP, at the addresses 1 to 15, the pattern number data, the repeat section start symbol data, and the repeat section end symbol data are stored as shown in the figure. Song end code data “FF _H ” is stored. The number in parentheses immediately below the symbol data at the end of the repeat section indicates the number of repetitions. Note that it is not necessary to store the pattern number data in the memory 18 in the numerical order as shown in the figure, and the user can freely combine the patterns.

When the performance data is stored in the memory 18 as shown in FIG. 4, in the play mode, the performances are performed in the order of performance patterns 1, 2, ... 5, When the data at the end of the repeat section of the address 8 is read, the performance is returned to the address 5. Repeat performance patterns 4 and 5 twice. When the performance pattern 6 is played, the program returns to the address 3 to play the performance patterns 3, 4 and 5, and the performances of the performance patterns 4 and 5 are repeated twice. Next, play performance patterns 6, 7, and 8 and then
When the end symbol of the repeat section is read, the program returns to address 12 and the performance of performance pattern 8 is repeated three times. After that, the performance pattern 9 is played, and when the performance ends, the song end code data "FF _H " at address 16 is read and the performance ends.

In FIG. 4, circled numbers indicate the read timing of the start or end symbol data of the repeat section in numerical order, and are cited in FIGS. 5 and 6.

Changes in Register Contents (FIG. 5) FIG. 5 shows changes in the contents of the registers JPNO and JPCNT used for enabling the performance progression as described with reference to FIG.

In FIG. 5, JPNO is an address number register, JPCNT, in which the address number of the return destination of the repeat is set.
Is a performance counter for counting the number of performances in the repeat section, and JPP is a register address pointer common to the registers JPNO and JPCNT.

In the performance progress of FIG. 4, when the repeat section start symbol data of the memory address 3 is read at the timing 1, JP
For NO, the address 1 indicated by JPP has the address number 3 and JPC
Address 0 indicated by JPP is set to 0 in NT. Then, the JPP value is incremented by 1. Next, at timing 2, when the repeat section start symbol data of the memory address 5 is read, the address number 5 is set to the address 2 indicated by JPP in JPNO and the address 2 indicated by JPP is set to 0 in JPCNT.
Is set. Then, the JPP value is incremented by 1.
In this way, the JPP indicates the register address next to the register address in which the address number of the repeat return destination is set. In other words, the memory address set in the register address immediately before the register address indicated by JPP is the return destination of the repeat.

Next, when the repeat section end symbol data of the memory address 8 is read at the timing 3, the performance of the repeat section performance patterns 4 and 5 is completed once.
The count value of the address 1 is incremented by 1. And JP
In NO, the program returns to the return address 5 set at the address of JPP-1 and plays the performance patterns 4 and 5 from the memory address 6 next to the return address. After that, since the data of the memory address 8 is read again at the timing 4, the count value of JPCNT is increased from 1 to 2 similarly to the previous time.
Then, when the performance patterns 4 and 5 are played again and the data at the memory address 8 is read at the timing 5, the repeat count 2 indicated by this data and the count value 2 of the JPCNT match, so that the required repeat count. Reached JP,
Decrement the value of P by 1. As a result, the next return destination is the memory address 3 set in the register address 1.

Next, after the performance pattern 6 is played, the repeat interval end symbol data of the memory address 10 is read at the timing 6, the memory address 3 is returned according to the instruction of the JPP, and the performance pattern 3 from the next memory address 4 is read. Play 4, 5 At this time, since the repeat section start symbol data is read at the timing 7 after the performance pattern 3 is played, the memory address 5 is set to the address 2 indicated by the JPP in JPNO, and 0 is set to the address 2 indicated by the JPP in JPCNT. It is set and the value of JPP is incremented by 1.

After that, the operation after the timing 8 can be easily inferred from the above operation, and thus the description thereof will be omitted.

Change of Repeat Hierarchy (FIG. 6) FIG. 6 shows a change of the repeat hierarchy as the performance progresses as described above. Here, the repeat hierarchy is a concept introduced in order to explain the change in the value of JPP in an easy-to-understand manner when there is another repeat section within a certain repeat section. The repeat section is assumed to have a hierarchical level higher by one. According to such an assumption, it is considered that the hierarchy level is increased by 1 each time the repeat section is entered, and the hierarchy level is decreased by 1 each time the repeat section is exited. The value of JPP is controlled.

That is, at timing 1, the memory address 3 is set in the address JPNO (1) indicated by the JPP in the JPNO. Then, the value of JPP changes from 1 to 2 in response to the change of the hierarchical level from 0 to 1.

Next, at timing 2, the memory address 5 is set in the address JPNO (2) indicated by JPP in JPNO, and the value of JPP changes from 2 to 3 in response to the change from 1 to 2 in the hierarchical level.

Thereafter, at timing 3, the count value of the address JPCNT (2) of JPP-1 is incremented by 1 in JPCNT. Then, when returning to the memory address 5 and repeating the performances of the performance patterns 4 and 5 twice, the hierarchical level changes from 2 to 1, and accordingly, the value of the JPP changes from 3 to 2 (corresponding to this change). (See timing 5 in FIG. 5).

Next, at the timing 6 after playing the performance pattern 6, the count value of the address JPCNT (1) of JPP-1 is incremented by 1 in JPCNT. When the performance patterns 3, 4, and 5 are played as described in FIG. 5, the hierarchy level changes from 1 to 2 at timing 7, and the value of JPP changes from 2 to 3 correspondingly. After that, when the performances of the performance patterns 4 and 5 are repeated twice, the hierarchical level changes from 2 to 1, and the value of the JPP correspondingly changes from 3 to 2 (see timing 10 in FIG. 5). Then, at the timing 11 in FIG. 5 after playing the performance pattern 6, the hierarchical level changes from 1 to 0, and the value of the JPP changes from 2 to 1 correspondingly.

The JPP value control and the JPNO and JPCNT value control as described above with reference to FIGS. 3 to 6 may be performed not only in the play mode but also in the search mode or when the switches S3 and S4 are operated (described later). See the routine in FIG. 13).

Register Group 16 Of the registers belonging to the register group 16, those relevant to the implementation of the present invention are listed below.

(1) Address number register JPNO ... This is the memory 18
The address number of the return destination of the repeat is set.

(2) Performance counter JPCNT ... This is for counting the number of performances in the repeat section.

(3) Register address pointer JPP ... This is for designating a register address common to JPNO and JPCNT.

(4) Song address pointer SGP ... This is memory 18
For specifying the address of.

(5) Pattern address pointer PTP ... This is memory 2
It is used to specify an address of 0.

(6) Run flag RUN ... This is a 1-bit register, and if 1 indicates that automatic performance is in progress,
A value of 0 indicates that the automatic performance is stopped.

(7) Mode flag REC ... This is a 1-bit register, where 1 represents the write mode and 0 represents the play mode.

(8) Tempo clock counter CLK ... This is for counting the tempo clock signal TCL. It takes a count value of 0 to 31 within one bar and becomes 0 at the timing of 32.
Is reset to.

(9) Performance data register DT This stores the data to be written in the memory 18 or the data read from the memory 18.

(10) Search target register REF ... This stores the data to be searched (for example, pattern number data, repeat section start symbol data, repeat section end symbol data, etc.).

(11) Search direction register FB ... This is a register in which 1 or -1 is set, where 1 indicates the address value increasing direction as the search direction, and -1 indicates the address value decreasing direction as the search direction.

(12) Old search direction register OFB ... The value of SGP is 1
Each time it changes, the FB value immediately before the change is set.

(13) Pattern number register PTNO ... This is the memory 18
When the pattern number data is read from to DT, the pattern number data of DT is set. The performance pattern to be read from the memory 20 is designated based on the pattern number data of PTNO.

Main Routine (FIG. 7) FIG. 7 shows the flow of processing of the main routine.
This routine starts when the power is turned on.

First, in step 40, initial setting processing is performed, for example,
Set 0 for RUN, REC, CLK, etc. Then, the process proceeds to step 42.

In step 42, it is determined whether or not the ST / SP switch S2 has an ON event. If YES (Y), the process proceeds to step 44, and the value obtained by subtracting 1 from the RUN value is set in RUN. As a result, the value of RUN is inverted to 0 when it is 1, to 1 when it is 0, and so on.

Next, at step 46, it is judged whether the value of RUN is 1, and if this judgment result is affirmative (Y), the routine proceeds to step 48 to start the automatic performance. At step 48, 1 is set to both SGP and JPP. Then, the routine proceeds to step 50, where a song reading subroutine is executed as described later with reference to FIG. In this song reading subroutine, data is read from the memory 18 at the address 1 indicated by the SGP.

If the determination result of step 46 is negative (N),
In order to stop the automatic performance, the process proceeds to step 52, and the tone generation all-off process of TG28 is performed. This pronunciation all-off process is a process for eliminating all the musical tones being generated.

When the determination result of step 42 is negative (N), or when the processing of step 50 or 52 is completed, it moves to step 54 and it is determined whether the value of RUN is 1 (whether the automatic performance is in progress). If the determination result is affirmative (Y), step 78.
Then, other processing (for example, setting processing of tone color, volume, tempo, etc., display processing, etc.) is executed. Then, the process returns to step 42, and the subsequent processes are repeated as described above. As a result, the automatic performance proceeds, but the performance process is
This is performed according to the clock interrupt routine shown in the figure.

If the determination result of step 54 is negative (N),
Since the automatic performance has been stopped, the process moves to step 56. In step 56, it is determined whether or not there is an on event in the search switch S11. If yes (Y), a search mode subroutine is executed in step 58 as will be described later with reference to FIG.

When the determination result of step 56 is negative (N) or when the process of step 58 ends, the process moves to step 60,
It is determined whether the INC switch S3 has an on event. If the determination result is affirmative (Y), the process proceeds to step 62 and the eleventh
The INC ON subroutine is executed as described later in the figure.

When the determination result of step 60 is negative (N) or when the process of step 62 ends, the process moves to step 64,
It is determined whether the DEC switch S4 has an on event. If the determination result is affirmative (Y), the process proceeds to step 66 and the twelfth
The DEC ON subroutine is executed as described later in the figure.

According to the processes of steps 56 to 66, it is possible to specify a search mode to search for desired performance data while the automatic performance is stopped, or to operate switches S3 and S4 to select the desired performance data. it can.

When the determination result of step 64 is negative (N) or when the process of step 66 is completed, the process proceeds to step 68.
In step 68, it is determined whether or not the EXE switch S9 has an on event, and if there is (Y), the process proceeds to step 70.

In step 70, the head address of the pattern storage section indicated by PTNO in the memory 20 is set in PTP. Then, in step 72, RUN is set to 1. Since the pattern number data relating to the search or selection is set in PTNO in step 58, 62 or 66, it is possible to start the automatic performance from the pattern number data relating to the search or selection by turning on the switch S9. it can.

When the determination result of step 68 is negative (N) or when the process of step 72 ends, the process moves to step 74,
It is determined whether the mode switch S1 has an on event. If the result of this determination is negative (N), the process returns to step 42 through step 78 in the same manner as described above, and the subsequent processing is repeated.

When the mode switch S1 is turned on while the automatic performance is stopped, the determination result of step 74 becomes affirmative (Y), and the routine proceeds to step 80. In step 80, 1 is set in REC (change to write mode). As a result, the progress of automatic performance is stopped. After that, the tone generation all-off process of the TG 28 is performed in step 82, and then the process shifts to the write mode routine of FIG.

Write Mode Routine (FIG. 8) FIG. 8 shows the write mode routine. In step 90, SGP, JPP, and OFB are all set to 1, and DT is set.
Is set to 0. Then, the process proceeds to step 92.

In step 92, it is determined whether or not there is an on event in the PAT designation permission switch S5, and if the determination result is affirmative (Y), the process proceeds to step 94. In step 94, the input of a two-digit number (pattern number) by the ten keys S6 is waited for. And
In step 96, the pattern number data indicating the input two-digit number is set in DT.

When the determination result of step 92 is negative (N), or when the processing of step 96 ends, the process proceeds to step 98.
In step 98, it is determined whether the repeat section designating switch S7 has an on event. If the determination result is affirmative (Y), the process proceeds to step 100, and the repeat section start symbol data (CO _H ) is set in DT.

When the determination result of step 98 is negative (N) or when the processing of step 100 is completed, the process proceeds to step 102, and it is determined whether the repeat section designating switch S8 has an on event. If the result of this determination is affirmative (Y), the routine proceeds to step 104, and waits for the input of a two-digit number (the number of repetitions) with the ten keys S6. In this case, the maximum value that can be entered is limited to 63. Then, in step 106, 8 indicating the input value
The bit data and the data of 80 _H in hexadecimal notation (data of 1 for MSB and 0 for others), that is, repeat interval end symbol data is set in DT.

When the determination result of step 102 is negative (N) or when the process of step 106 is completed, the process proceeds to step 108, and it is determined whether the EXE switch S9 has an on event. If this determination result is affirmative (Y), the process proceeds to step 110, and the address SONG (SGP) indicated by SGP in the memory 18 is set.
Write the DT data. Then, in step 112, the SGP value is incremented by 1.

According to the above steps 92 to 112, the EXE switch S9 is used to specify the pattern number, the repeat section start symbol or the repeat section end symbol (including the repeat count).
By turning on, desired performance data can be written in the memory 18.

When the determination result of step 108 is negative (N) or when the process of step 112 is completed, the process proceeds to step 114. Steps 114, 116, 118, 120, 122, 124 are the same as steps 56, 58, 60, 62, 64, 66 described in FIG. 7, and detailed description thereof will be omitted. According to the processing of steps 114 to 124, it is possible to specify a search mode in the writing mode to search for desired performance data, or to operate switches S3 and S4 to select desired performance data. it can.

When the determination result of step 122 is negative (N) or when the process of step 124 is completed, the process proceeds to step 126, and it is determined whether the mode switch S1 has an on event.
If the determination result is negative (N), other processing (for example, display processing) is executed in step 128, and then step
Returning to 92, the subsequent processing is repeated as described above.
In steps 116, 120, and 124, since the data related to the search or selection is set in the DT, after returning to step 92, the data in the DT is corrected using the switches S5 to S8 and then EX.
By turning on the E switch S9, desired data in the memory 18 can be rewritten.

When the mode switch S1 is turned on while the writing mode process is being performed as described above, the determination result of step 126 becomes affirmative (Y), and the routine proceeds to step 130.
In step 130, the address indicated by SGP in the memory 18
Writes song end code data (FF _H) the Book of SONG (SGP). Then, the routine proceeds to the play mode routine shown in FIG.

In step 132 in FIG. 7, both REC and DT are set to 0, and SGP, JPP, and OFB are set to 1. Then, the process proceeds to step 42, and the subsequent processes are all executed in the same manner as the above-mentioned main routine.

Song reading subroutine (Fig. 9) Fig. 9 shows a song reading subroutine.
In step 140, the address indicated by SGP in memory 18
Read SONG (SGP) data and set in DT. Then, the process proceeds to step 142.

In step 142, it is determined whether the value of DT is 01 to 99 (pattern number). This judgment result is positive (Y)
If so, the process proceeds to step 144, the SGP value is incremented by 1, and the DT pattern number data is set in PTNO.
Then, the process proceeds to step 146.

In step 146, the head address of the pattern storage section indicated by PTNO in the memory 20 is set in PTP. After this, the process returns to the original routine (the routine of FIG. 7 or 10). In addition, in FIG. 9 to FIG.
"T" represents a return.

When the determination result of step 142 is negative (N), the process proceeds to step 148, and it is determined whether the value of DT is CO _H (whether it is a repeat section start symbol). This judgment result is positive (Y)
If so, the process proceeds to step 150, where the SJP value (memory address to which the repeat returns) is set to the address JPNO (JPP) indicated by JPP in JPNO, and the address JPCNT (JPP) indicated by JPP is set to 0 in JPCNT. Set.
Then, the process proceeds to step 152.

In step 152, as the repeat hierarchy level increases, the JPP
The value of is increased by 1 and the value of SGP is also increased by 1.
The processing of steps 150 and 152 corresponds to the operation of timing 1 or 2 in FIG. 5, for example.

After step 152, the process returns to step 140, and the subsequent processes are repeated as described above. At this time, if the pattern number data is read to DT, the process returns to the original routine through steps 144 and 146.

If the determination result in step 148 is negative (N), the process moves to step 154, and it is determined whether the upper 2 bits of DT are "10" (whether the repeat section end symbol). If the result of this determination is affirmative (Y), the routine proceeds to step 156, where the count value of the address JPCNT (JPP-1) of JPP-1 and D
It is determined whether the value of the lower 6 bits of T is equal (whether the desired number of repetitions has been reached). If this determination result is affirmative (Y), the process proceeds to step 158.

In step 158, as the repeat hierarchy level descends, JPP
The value of is decreased by 1 and the value of SGP is increased by 1.
The processing of steps 156 and 158 corresponds to, for example, the operation at timing 5 in FIG. After step 158, the process returns to step 140, and if the pattern number data is read, the process returns to the original routine through steps 144 and 146.

If the determination result of step 156 is negative (N), the process proceeds to step 160, and the count value of JPCNT (JPP-1) is incremented by 1. Then, move to step 162, JPNO
At 1, the address of JPP-1 JPNO (JPP-1) plus 1 (the memory address next to the repeat return destination) is set in the SGP. Steps 160 and 162
5 corresponds to the operation of timing 3 or 4 in FIG. After step 162, return to step 140, and if the pattern number data is read,
It returns to the original routine through 144,146.

If the determination result in step 154 is negative (N), the process moves to step 164 and it is determined whether the value of DT is FF _H (song end code). If the determination result is negative (N), the value of SGP is incremented by 1 in step 166 and step 140
Return to. Further, the determination result of step 164 is positive (Y).
If so, RUN is set to 0 in step 168 and the process returns to the original routine. As a result, the automatic performance is stopped.

Clock Interrupt Routine (FIG. 10) FIG. 10 shows the clock interrupt routine, which starts at each clock pulse of the tempo clock signal TCL.

First, in step 170, the REC value is 0 (play mode).
And the RUN value is 1 (automatic performance is in progress). If the determination result is negative (N), the process returns to the routine of FIG.

If the determination result of step 170 is affirmative (Y), the process proceeds to step 172, and it is determined whether the timing value of the event data indicated by PTP in the memory 20 is equal to the value of CLK (whether the timing should be read). . If the determination result is negative (N), the process proceeds to step 188 and the value of CLK is incremented by 1. Then, in step 190, the value of CLK is
If 32 is judged, and this judgment result is affirmative (Y), 0 is set to CLK in step 192.

When the determination result of step 190 is negative (N) or when the process of step 192 ends, the routine returns to the routine of FIG.

If the determination result of step 172 is affirmative (Y), the process proceeds to step 174, and the key data of the first and second bytes of the event data indicated by PTP is read from the memory 20. Then, the process proceeds to step 176, and the tone generation or mute control of the TG 28 is performed according to the read key data. That is, if the read key data indicates key-on, a tone signal having a pitch corresponding to the key code in the key data is started to be generated. Attenuation of a musical tone signal having a pitch corresponding to the key code is started.

Next, in step 178, the value of PTP is increased by 3. As a result, PTP comes to instruct the next event data. After this, the process proceeds to step 180.

In step 180, it is determined whether the data indicated by PTP is pattern end code data PEND. If the determination result is negative (N), the process proceeds to step 188, the subsequent processes are executed in the same manner as described above, and then the process returns to the routine of FIG.

If the determination result of step 180 is affirmative (Y), the process proceeds to step 182, and the SGP value is incremented by 1. Then, the routine proceeds to step 184, where the song reading subroutine is executed as described above with reference to FIG. In the routine of FIG. 9, since the SGP value is incremented by 1 in step 182, the performance data at the new address indicated by SGP is stored in the memory 18.
Read from.

After step 184, CLK is set to 0 in step 186, and then the process returns to the routine of FIG.

INC ON and DEC ON subroutines (Figs. 11 and 12
(FIG. 11) FIG. 11 shows a subroutine for turning on the INC. In step 200, FB is set to 1 (corresponding to the increasing address value). Then, the routine proceeds to step 202, where a pointer movement subroutine is executed as will be described later with reference to FIG. After this, the original routine (FIG. 7, FIG. 8 or FIG.
Return to the routine shown in Fig. 14).

Fig. 12 shows the DEC ON subroutine, and in step 210, -1 is added to FB (corresponding to decreasing address value).
Set. Then, the routine proceeds to step 212, where the pointer moving subroutine of FIG. 13 is executed. After this, the process returns to the original routine (the routine of FIG. 7, FIG. 8 or FIG. 14).

Pointer movement subroutine (Fig. 13) Fig. 13 shows the pointer movement subroutine.
At step 220, whether the FB value is 1 and the SONG (SGP) data value is FF _H (in the direction of increasing address value and song end code), or whether the FB value is -1 and the SGP value is 1 (Whether the address value is decreasing and the start address of the memory 18). If this determination result is negative (N),
Move to step 222.

In step 222, it is determined whether the value of DT is CO _H and the values of OFB and FB are both −1 (whether the repeat interval start symbol is encountered by moving in the address value decreasing direction). If the result of this determination is affirmative (Y), the routine moves to step 224, and the value of JPP is decremented by 1 as the repeat hierarchy level drops.

If the determination result of step 222 is negative (N), the process moves to step 226, and the upper 2 bits of the DT data are “10” and both OFB and FB are +1 (in the direction of increasing the address value). To the end of the repeat section) to determine. If this determination result is affirmative (Y), the value of JPP is decremented by 1 in step 224.

If the determination result in step 226 is negative (N), the process moves to step 228, and the upper 2 bits of the DT data are “10” and both OFB and FB are −1 (decrease address value). It moves in the direction, and it judges whether it encounters the end symbol of the repeat section. If the determination result is affirmative (Y), the process moves to step 230, and the JPP increases as the repeat hierarchy level increases.
Increase the value of by 1.

If the determination result in step 228 is negative (N), the process moves to step 232, where the value of DT is CO _H and OFB and FB.
Is +1 (whether the repeat interval start symbol is encountered by moving in the address value increasing direction). If the determination result is affirmative (Y), the process moves to step 234,
Similar to step 150 in FIG. 9, the SGP value (memory address of the repeat return destination) is set in JPNO (SGP), and 0 is set in JPCNT (SGP). Then, in step 230, the JPP value is incremented by 1.

When the determination result of step 232 is negative (N),
Alternatively, when the process of step 224 or 230 is completed, the process proceeds to step 236, and the sum of the SGP value and the FB value is added to SG.
Set it to P and set the value of FB to OFB. In this case, if the FB value is +1 then the SGP value is incremented by 1
If the value of -1 is -1, the value of SGP is decreased by 1. That is, only one address indicated by SGP in the memory 18 is changed.

When the determination result of step 220 is affirmative (Y) or when the process of step 236 ends, the process moves to step 238, the data of SONG (SGP) is read and set in DT.
At this time, what is set in DT is SONG (S
When GP) = FF _H , FF _H data (song end code)
If SGP = 1 in step 220, it is SONG (1) data, and if it goes through step 236, it is step 236.
It is the data of the new address set in. Step
After 238, the process proceeds to step 240.

In step 240, it is determined whether the DT value is 01 to 99 (pattern number). This judgment result is positive (Y)
If so, the process proceeds to step 242, and the pattern number data of DT is set in PTNO.

When the determination result of step 240 is negative (N) or when the process of step 242 ends, the process returns to the original routine (the routine of FIG. 11, FIG. 12 or FIG. 15).

Search mode subroutine (Fig. 14) Fig. 14 shows the search mode subroutine.
In step 250, it is determined whether or not there is an on event in the PAT designation permission switch S5, and if the determination result is affirmative (Y), the process proceeds to step 252. In step 252, the input of a two-digit number (pattern number) by the ten keys S6 is waited for. Then, the process proceeds to step 254, and the pattern number data indicating the inputted two-digit number is set in REF.

When the determination result of step 250 is negative (N) or when the process of step 254 ends, the process proceeds to step 256. In step 256, it is determined whether the repeat section designating switch S7 has an on event. If the result of this judgment is affirmative (Y), the routine proceeds to step 258, where the repeat section start symbol data (CO _H ) is set to REF.

When the determination result of step 256 is negative (N) or when the process of step 258 ends, the process proceeds to step 260, and it is determined whether the repeat section designating switch S8 has an on event. If this determination result is affirmative (Y), the process proceeds to step 262, and the repeat section end symbol data of 80 _H in hexadecimal notation is set in REF. In this case, the number of repetitions is not considered.

When the determination result of step 260 is negative (N) or when the process of step 262 ends, the process proceeds to step 264, and it is determined whether the EXE switch S9 has an on event. If the result of this determination is affirmative (Y), the routine proceeds to step 266, where a search execution subroutine is executed as described later with reference to FIG.

When the determination result of the switch 264 is negative (N) or when the process of step 266 is completed, the process proceeds to step 268 and it is determined whether the search direction designating switch S10 has an on event. If the determination result is affirmative (Y), the process proceeds to step 270. In step 270, the sign given to the value of FB is inverted. That is, when the value of FB is +1
If -1 is set in FB and the value of FB is -1, FB
Set +1 to. As a result, the search direction is reversed every time the switch S10 is turned on.

According to the processing of steps 250 to 270 described above, the desired performance data is searched at high speed by turning on the EXE switch S9 by designating the pattern number, the repeat section start symbol or the repeat section end symbol and the search direction. be able to.

When the determination result of step 268 is negative (N) or when the process of step 270 is completed, the process proceeds to step 272. Steps 272, 274, 276, and 278 are similar to steps 60, 62, 64, and 66 described in FIG. 7, and detailed description thereof will be omitted. According to the processing of steps 272 to 278, the desired performance data can be selected by operating the switches S3 and S4 in the search mode, and particularly, the performance data near the performance data searched in step 266 is selected. It is convenient for

When the determination result of step 276 is negative (N) or when the process of step 278 ends, the process proceeds to step 280, and it is determined whether the ST / SP switch S2 has an on event.
If the determination result is negative (N), the process proceeds to step 282 and other processing (for example, display processing) is performed. After that, the process returns to step 250, and the subsequent processes are repeated as described above.

If the determination result of step 280 is affirmative (Y), the process returns to the original routine (the routine of FIG. 7 or 8). That is, when it is desired to return from the search mode to the play mode or the write mode, the switch S2 may be turned on.

Search Execution Subroutine (FIG. 15) FIG. 15 shows a search execution subroutine. In step 290, the pointer movement subroutine shown in FIG. 13 is executed. Then, the process proceeds to step 292.

In step 292, the value of REF and the value of DT are equal and REF
Whether the most significant bit of the data of "0" is "0" (whether the data of REF and DT is pattern number data and the pattern number matches) is determined. Now, the data of REF and DT are both pattern number data, but if the pattern numbers do not match, the determination result of step 292 is negative (N), and steps 290 to 290 via steps 294 to 298.
Return to. Then, the processing from step 290 is repeated until the pattern numbers match.

If the pattern numbers match, the determination result of step 292 becomes affirmative (Y), and the process returns to the routine of FIG. As a result, the pattern number data indicating the desired pattern number is searched.

The determination result of step 292 is negative (N) when the pattern numbers do not match or the REF data is not the pattern number data as described above. In such a case, the process proceeds to step 294, and it is determined whether the value of REF is equal to the value of DT and the upper 2 bits of REF are "11" (whether it is a repeat section start symbol).

Now, assuming that the REF data is the repeat section start symbol data, but the DT data is not the repeat section start symbol data, the determination result of step 294 is negative (N), and the procedure advances to step 290 via steps 296 and 298. Return. Then, the processing from step 290 is repeated until the repeat interval start symbol is set in DT.

When the repeat section start symbol is set in DT, the determination result of step 294 becomes affirmative (Y), and the process returns to the routine of FIG. As a result, the repeat section start symbol is searched.

The determination result of step 294 is negative (N) when the REF data is the repeat section start symbol data and the DT data is other data as described above, or when the REF data is the repeat section. This is the case when it is not the beginning symbol. In such a case, the process proceeds to step 296, and it is determined whether the upper 2 bits of REF and the upper 2 bits of DT are both "10" (a repeat section end symbol).

Now, if the REF data is the repeat section end symbol data, but the DT data is not the repeat section end symbol data, the determination result of step 296 is negative (N).
Then, the process returns to step 290 via step 298. Then, the processing from step 290 is repeated until the repeat interval end symbol data is set in DT.

When the repeat interval end symbol data is set in DT, the determination result of step 296 becomes affirmative (Y), and the process returns to the routine of FIG. As a result, the repeat section end symbol is searched.

The determination result of step 296 is negative (N) when the REF data is the repeat section end symbol data and the DT data is other data as described above, or
This is the case where the REF data is not the repeat interval end symbol data. In such a case, the process proceeds to step 298.

In step 298, whether the value of DT is FF _H (or song end code) it determines. If the result of this judgment is affirmative (Y), whether or not the search target indicated by REF does not exist even if the end of the performance data array is searched, or DT
Since FF _H has been set to, the routine returns to the routine shown in FIG.

The determination result of step 298 is negative (N) when all the determination results of steps 292 to 296 are negative (N) and data other than FF _H is set in DT. Is.

Modifications The present invention is not limited to the above embodiments, but can be implemented in various modified forms. For example, the following changes are possible.

(1) The pattern data may be rewritten.

(2) The data format is not limited to that of the embodiment,
You may use a well-known thing.

(3) The processing of the repeat symbol is not limited to that of the embodiment,
Paired repeat symbols may be searched and processed.

(4) In the search of the repeat section end symbol, the search may be performed in consideration of the number of repetitions.

(5) The processing in the search mode may be performed only in either the write mode or the play mode.

[Effects of the Invention] As described above, according to the present invention, the symbol information designating a desired repeat section is designated and the symbol information matching the symbol information is searched from the memory. It is possible to obtain the effect that the information can be corrected or the performance can be started easily and quickly. Moreover, since the symbol information that indicates the repeat section is a kind of performance information,
Compared with storing the information dedicated to the search in addition to the performance information, the memory utilization efficiency is improved and the processing is simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an automatic performance device according to an embodiment of the present invention, FIG. 2 is a diagram showing a data format of a song memory 18, and FIG. 3 is a data format of a pattern memory 20. 4 and 5 are diagrams showing an example of performance progress, and FIG. 5 is a register JPNO and JP associated with the performance progress of FIG.
FIG. 6 is a diagram showing changes in the contents of the CNT, FIG. 6 is a diagram showing changes in the repeat hierarchy as the performance of FIG. 4 progresses, FIG. 7 is a flowchart showing a main routine, and FIG. 8 is a write mode routine. 9 is a flowchart showing a song reading subroutine, FIG. 10 is a flowchart showing a clock interrupt routine, and FIGS. 11 and 12 are flowcharts showing subroutines of INC ON and DEC ON, respectively. 13 is a flowchart showing a pointer movement subroutine, FIG. 14 is a flowchart showing a search mode subroutine, and FIG. 15 is a flowchart showing a search execution subroutine. 10 ... Data bus, 12 ... Central processing unit, 14 ... Program memory, 16 ... Register group, 18 ... Song memory, 20 ... Pattern memory, 22 ... Tempo clock generator, 24 ... Switch group, 26 ... Display unit, 28 ... Tone generator, 30… Sound system.

Claims (2)

[Claims] 1. A storage means; (b) a writing means for writing performance information for automatic performance including symbol information indicating a repeat section in the storage means in accordance with the progress of a music piece; and (c) the storage. Information designating means for designating the symbol information to be searched among the symbol information written in the means, and (d) reading the performance information from the storage means and comparing it with the symbol information designated by the information designating means. Search means for searching the symbol information matching the symbol information, wherein the writing means writes the performance information from a storage position of the symbol information searched by the searching means. Performance information input device. 2. A storage means for storing performance information for automatic performance including symbol information indicating a repeat section, and (b) symbol information to be searched out of the symbol information stored in the storage means. (C) search means for searching the symbol information that matches the symbol information by reading the performance information from the storage means and comparing it with the symbol information designated by the information designating means; d) a performance device which performs automatic performance from the storage position of the symbol information searched by the search device in accordance with the performance information of the storage device.