JPH07109863B2 - Active layer 2-layer stacked memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a CMOS / SRAM (static RAM, static RA) having an active layer stack structure using SOI (Semiconductor on Insulator).
M).

(Prior Art) Conventionally, a CMOS / SRAM having a two-layer structure of an active layer uses the 6-transistor configuration shown in FIG. At this time, among the 6-transistor configuration, four are nMOSFETs, two are pMOSFETs, and nMOSFET22 and pMOSFET21 form a first inverter, and nMOSFET24 and pMOSFET23 form a second inverter.
The nMOSFETs 20 and 28 form two transfer gates.

The layout of these nMOSFETs and pMOSFETs will be described below in the order of manufacturing steps. First, nMOSFE is formed on the silicon substrate 1.
T20,22,24,28 are arranged, and this layer is used as the lower active layer. An SOI layer is formed thereon with an interlayer insulating film 6 interposed therebetween, and this layer is used as an upper active layer, and pMOSFETs 21 and 23 are arranged therein. Next, after forming the insulating film 10 on the sample surface, the aluminum wiring 12 to each MOSFET is formed.

Of the wirings of the MOSFETs arranged in this way, the nodes of the drains of the nMOSFET 22 and pMOSFET 21 that form the first inverter
25, and nMOSFET 24 and pMOSFET that form the second inverter
The node 27 of the gate of 23 and the node 26 connecting the node 25 and the node 27 are conventionally formed by the structure shown in FIG. That is, the drain contact holes of the nMOSFET 22 and pMOSFET 21, and the nMOSFET 24 and pMOSF, respectively.
The contact holes to the respective gates of ET23 were independently opened, the contact holes were filled with aluminum 12, and the wiring was formed.

The above is the nMOSFET 24, pMOSF that constitutes the second inverter.
The drain node 30 of the ET 23 and the gate node 29 of the gates of the nMOSFET 22 and the pMOSFET 21 forming the first inverter and the node 31 connecting the node 29 and the node 30 are similarly formed.

(Problems to be solved by the invention) However, when the above-mentioned wiring system is used, the contact holes corresponding to the drains 3 and 7 and the gates 5 and 9 are opened, and the aluminum 12 is wired. Point 25,26,27,2
A large occupied area is required to form 9,30,31.
Therefore, the degree of integration of the active layer double-layered SRAM decreases.

Also, since the connection of the nodes 25, 26, 27 and the nodes 29, 30, 31 is executed by aluminum wiring, the wiring length becomes long and the first,
The wiring capacitance added to the second inverter and the transfer gate increases. As a result, it becomes difficult to improve the circuit characteristics of SRAM.

The object of the present invention is to improve the degree of integration by reducing the area occupied by the nodes 25, 26, 27, 29, 30, 31 and the active layer two layers for improving the circuit characteristics of the SRAM by reducing the wiring capacitance. It is to provide stacked CMOS / SRAM.

(Means for Solving the Problem) According to the present invention, in a 6-transistor type static memory element formed by laminating two active layers, a MOSFET of the first conductivity type is arranged in the lower active layer, and the upper active layer is formed. A second conductivity type MOSFET is disposed therein, and a drain of the first conductivity type MOSFET and a drain of the second conductivity type MOSFET that form the first inverter, and a first conductivity type MOSF that forms the second inverter.
An active layer two-layer stacked memory device characterized in that the gate of the ET and the gate of the second conductivity type MOSFET are connected by a columnar metal embedded in only one contact hole.

(Example) Hereinafter, the present invention will be described using examples. In this embodiment, a silicon film is used as a semiconductor film, a silicon oxide film is used as an insulating film, a silicon substrate is used as a semiconductor substrate, aluminum is used as a wiring material, and tungsten is used as a columnar metal embedded in a kottan hole.

FIGS. 1 (a) and 1 (b) show an active layer 2 produced by the present invention.
FIG. 6 is a schematic cross-sectional view of a portion corresponding to the node points 25, 26, and 27 in the layer-stacked CMOS / SRAM before and after the wiring process. First, an nMOSFET is formed in the silicon substrate 1. Further, a silicon oxide film 6 is formed as an interlayer insulating film. After that, a polycrystalline silicon film is formed and single crystallized by a method such as laser annealing to form an SOI film, and a pMOSFET is formed there. At this time, nMOS
Drain 3 of FET 22, drain 7 of pMOSFET 21, and nMOS
The gate 5 of the FET 24 and the gate 9 of the pMOSFET 23 are arranged so as to be in contact with each other when viewed from the sample surface (Fig. 1 (a)).

Next, contact holes are formed so as to include all of the drains 3 and 7 and the gates 5 and 9 partially when viewed from the surface. That is, first, the resist is patterned to dry-etch the exposed silicon oxide film 10, and then the gate 9, drain 7, silicon oxide film 6, gate 5 and silicon oxide film 2 are etched to open contact holes.

A polysilicon thin film 13 having a film thickness of 500 Å is deposited on the surface of the sample processed in this way, and the polysilicon thin film 13 at a place other than the contact hole portion is removed by anisotropic dry etching. Due to the anisotropy of dry etching and the large aspect ratio of the contact hole, the polysilicon thin film 13 remains only in the contact hole.

Finally, the mixing ratio of H ₂ as a carrier gas on the sample surface
Using a 1: 1 mixed gas of WF ₆ and SiH ₄ , CVD growth of tungsten is performed in an environment at a temperature of 300 ° C. In this condition,
Tungsten is deposited only on the silicon film, not on the silicon oxide film. As a result, columnar tungsten 11 is formed only in the contact hole (FIG. 1 (b)). The columnar tungsten 11 is in contact with all of the drains 3 and 7 of the nMOSFET 22 and pMOSFET 21 forming the first inverter and the gates 5 and 9 of the nMOSFET 24 and pMOSFET 23 forming the second inverter. That is, the node 25,
26 and 27 can be formed only by tungsten 11.

The nodes 29, 30, 31 can likewise be formed by tungsten embedded in only one contact hole.

In this embodiment, a silicon film is used as a semiconductor film, a silicon oxide film is used as an insulating film, a silicon substrate is used as a semiconductor substrate, aluminum is used as a wiring material, and tungsten is used as a columnar metal embedded in a contact hole.
Other types of semiconductor films, other types of insulating films, other types of semiconductor substrates, other types of wiring materials, and other types of metals may be used.

(Effects of the Invention) As described above, according to the present invention, a CMOS with two active layers stacked is used.
· Nodes 25, 26, 27 and 2 of the circuit forming the SRAM
Since 9,30 and 31 can be connected only by the metal which is buried in only one contact hole, the area occupied by the above-mentioned nodes is reduced and the circuit integration is improved.

Further, the connection points 25, 26, 27 and the connection points 29, 30, 31 do not require wiring such as aluminum, and the drains 3, 7,
Since the gates 5 and 9 are connected at the shortest distance, the wiring capacity added to the first and second inverters and the transfer gate is reduced. As a result, the circuit characteristics of SRAM are improved.

Furthermore, when the size of the contact hole becomes smaller and becomes closer to the thickness of the silicon thin film, it is better to make contact with the silicon thin film surface on the side wall of the contact hole than to make contact with the conventional upper surface of the silicon thin film. The contact area is large. Therefore, the contact resistance is expected to decrease.

[Brief description of drawings]

1 (a) and 1 (b) are sectional views of a portion corresponding to the nodes 25, 26, 27 in the active layer double-layer CMOS / SRAM according to the embodiment of the present invention, and FIG. Sectional view of the part corresponding to nodes 25, 26, 27, Fig. 3 shows active layer 2-layer CMOS / SRAM
It is a circuit diagram of. The numbers in the figure indicate the following. 1 is a silicon substrate, 2, 6 and 10 are silicon oxide films, 3 is an nMOSFET drain, 4,5 is an nMOSFET gate, 7 is a pMOSFET drain, 8 and 9 are pMOSFET gates, 11 is tungsten, 12 is aluminum. Wiring, 13 is a silicon thin film, 20,22,24,28 are nMOSFETs, 21,23 are pMOSFETs, 25,26,27,29,30,31 are the node points of the electrodes of each MOSFET

Claims (1)

[Claims] 1. A static type memory device having a 6-transistor structure formed by laminating two active layers, wherein a MOSFET of the first conductivity type is arranged in the lower active layer and a MOSFET of the second conductivity type is arranged in the upper active layer. A drain of a first conductivity type MOSFET and a drain of a second conductivity type MOSFET in which a MOSFET is arranged to form a first inverter, and a first conductivity type of a second inverter.
Only one MOSFET gate and second conductivity type MOSFET gate
An active layer two-layer laminated storage element, characterized in that the connection is made by a columnar metal embedded in each contact hole.