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JPH07109904B2 - Heterojunction diode manufacturing method - Google Patents
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JPH07109904B2 - Heterojunction diode manufacturing method - Google Patents

Heterojunction diode manufacturing method

Info

Publication number
JPH07109904B2
JPH07109904B2 JP1043707A JP4370789A JPH07109904B2 JP H07109904 B2 JPH07109904 B2 JP H07109904B2 JP 1043707 A JP1043707 A JP 1043707A JP 4370789 A JP4370789 A JP 4370789A JP H07109904 B2 JPH07109904 B2 JP H07109904B2
Authority
JP
Japan
Prior art keywords
manufacturing
silicon carbide
heterojunction
amorphous silicon
heterojunction diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1043707A
Other languages
Japanese (ja)
Other versions
JPH02222179A (en
Inventor
美生 三戸
龍馬 平野
雅俊 北川
孝 平尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1043707A priority Critical patent/JPH07109904B2/en
Priority to US07/483,872 priority patent/US5070027A/en
Publication of JPH02222179A publication Critical patent/JPH02222179A/en
Publication of JPH07109904B2 publication Critical patent/JPH07109904B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 産業上の利用分野 本発明は、光、放射線等の検出に用いるヘテロ接合ダイ
オードの製造方法に関するものである。
TECHNICAL FIELD The present invention relates to a method for manufacturing a heterojunction diode used for detecting light, radiation and the like.

従来の技術 従来、半導体を用いた接合素子は可視光、赤外光や放射
線等を電気信号に変換する装置として幅広く用いられて
いるが、それらは主にシリコン単結晶基板に熱拡散性や
イオン注入法によって作製したpn(pin)接合ダイオー
ドに逆バイアス電圧を印加した時に発生する空乏層を有
感層として使用するものである。しかしながらこれらの
製造プロセスは、900℃以上の高温処理が必要でありこ
れに起因する熱誘起欠陥が生じたり、イオン注入法の場
合には注入時に於いて生じた打ち込みによる基板ダメー
ジがアニール処理によっても取り除ききれない場合が多
い。その結果再結合による暗電流が増大するためにS/N
比が取れにくかった。
2. Description of the Related Art Conventionally, a junction element using a semiconductor has been widely used as a device for converting visible light, infrared light, radiation, etc. into an electric signal. A depletion layer generated when a reverse bias voltage is applied to a pn (pin) junction diode manufactured by the injection method is used as a sensitive layer. However, these manufacturing processes require high-temperature treatment of 900 ° C. or higher, which causes thermally-induced defects, and in the case of the ion implantation method, the substrate damage due to implantation generated during implantation is also caused by the annealing treatment. Often cannot be removed. As a result, the dark current due to recombination increases and S / N
It was hard to get the ratio.

そこで最近ではシリコン単結晶基板上に高周波または直
流プラズマCVD法によって非生質シリコンカーバイト膜
を200℃〜300℃の比較的低温工程によって堆積し、ヘテ
ロ結合を形成した後、両面にオーミック電極、例えばア
ルミニウム電極を形成し、ヘテロ結合ダイオード構成を
取ることによって欠陥の誘起を低減しかつヘテロ効果に
よって暗電流を低減しようと試みられている。
Therefore, recently, a non-natural silicon carbide film was deposited on a silicon single crystal substrate by a high frequency or direct current plasma CVD method at a relatively low temperature process of 200 ° C to 300 ° C to form a heterojunction, and then ohmic electrodes were formed on both surfaces. Attempts have been made to reduce the induction of defects and reduce dark current by the hetero effect, for example by forming aluminum electrodes and adopting a hetero-coupled diode configuration.

発明が解決しようとする課題 しかし、上記の方法によるヘテロ接合ダイオードでは、
逆バイアス電圧印加時の暗電流が、結晶半導体基板表面
のプラズマダメージによって生じる界面の欠陥準位を通
しての再結合電流のために大きくなるという現状であ
る。
However, in the heterojunction diode by the above method,
In the present situation, the dark current at the time of applying a reverse bias voltage becomes large due to the recombination current through the defect level at the interface caused by plasma damage on the surface of the crystalline semiconductor substrate.

そこで、本発明は上記課題を解決し得るヘテロ接合ダイ
オードの製造方法を提供することを目的とする。
Therefore, an object of the present invention is to provide a method for manufacturing a heterojunction diode that can solve the above problems.

課題を解決するための手段 上記課題を解決するため、本発明のヘテロ接合ダイオー
ドの製造方法は、シリコン単結晶基板上に水素を含有す
る非晶質シリコンカーバイト膜を堆積する製造において
アニール処理を追加して行う方法である。
Means for Solving the Problems In order to solve the above problems, a method for manufacturing a heterojunction diode according to the present invention includes an annealing treatment in a manufacturing process for depositing an amorphous silicon carbide film containing hydrogen on a silicon single crystal substrate. This is a method of adding.

作用 本発明の製造方法によれば、シリコン単結晶基板上に水
素を含有する非晶質シリコンカーバイト膜を堆積したヘ
テロ接合ダイオードをアニール処理することによって、
非晶質シリコンカーバイト膜中に含まれる結合状態にな
い有離水素がシリコン基板のプラズマダメージによる欠
陥を埋め、界面の欠陥準位を通しての再結合電流が減少
し暗電流を低減できる。
Effect According to the manufacturing method of the present invention, by annealing the heterojunction diode in which the amorphous silicon carbide film containing hydrogen is deposited on the silicon single crystal substrate,
The isolated hydrogen contained in the amorphous silicon carbide film, which is not in a bound state, fills the defects due to plasma damage of the silicon substrate, and the recombination current through the interface defect level is reduced, so that the dark current can be reduced.

実施例 以下、本発明の一実施例を図面に基づき説明する。Embodiment An embodiment of the present invention will be described below with reference to the drawings.

第1図は、本発明の製造方法によって製造されたヘテロ
接合ダイオードの製造工程を示している。
FIG. 1 shows a manufacturing process of a heterojunction diode manufactured by the manufacturing method of the present invention.

まず、シリコン単結晶基板(P型、10kΩcm)1の上部
全面に基板1とのヘテロ接合を形成する非晶質シリコン
カーバイト膜2を平行平板型プラズマCVD装置を用いて
以下の条件で形成する(第1図(a))。
First, an amorphous silicon carbide film 2 forming a heterojunction with the substrate 1 is formed on the entire upper surface of a silicon single crystal substrate (P type, 10 kΩcm) 1 using a parallel plate plasma CVD apparatus under the following conditions. (FIG. 1 (a)).

基板温度 200℃ 使用ガス モノシラン(100%),メタン(100%) ガス流量 モノシラン70SCCM メタン 30SCCM ガス圧力 0.6Torr 膜 厚 100〜200nm RF電力 30W(42mW/cm2) 次に、非晶質シリコンカーバイト膜の堆積面上にメタル
マスク3を介してアルミニウム電極4を抵抗加熱蒸着装
置によって約300nm形成する(第1図(b))。
Substrate temperature 200 ℃ Gas used Monosilane (100%), Methane (100%) Gas flow rate Monosilane 70SCCM Methane 30SCCM Gas pressure 0.6Torr Film thickness 100-200nm RF power 30W (42mW / cm 2 ) Next, amorphous silicon carbide An aluminum electrode 4 having a thickness of about 300 nm is formed on the deposition surface of the film through a metal mask 3 by a resistance heating vapor deposition device (FIG. 1 (b)).

更に、裏全面にアルミニウム電極5を抵抗加熱蒸着装置
によって約300nm形成する(第1図(c))。
Further, an aluminum electrode 5 is formed on the entire back surface by a resistance heating vapor deposition device to a thickness of about 300 nm (FIG. 1 (c)).

最後に、電気炉を用いて以下の条件でアニール処理を行
う(第1図(d))。
Finally, an annealing process is performed using an electric furnace under the following conditions (Fig. 1 (d)).

雰囲気 窒素 温 度 230℃ 時 間 30〜90分 アニール温度は、第2図に示す上記方法で作製したヘテ
ロ接合ダイオードの逆バイアス印加状態での暗電流のア
ニール温度依存性のデータから決定した。これは1時間
のアニール時間の場合であるが、これから望ましくは20
0℃〜250℃の温度でアニールを行なえば最も暗電流を小
さくできることがわかる。なお、アニール温度は100℃
以上であれば効果が発揮される。
Atmosphere Nitrogen temperature 230 ° C Time 30 to 90 minutes Annealing temperature was determined from the annealing temperature dependence data of dark current under the reverse bias application condition of the heterojunction diode manufactured by the above method shown in FIG. This is for an annealing time of 1 hour, but from now on 20
It can be seen that the dark current can be minimized by annealing at a temperature of 0 ° C to 250 ° C. The annealing temperature is 100 ℃
If it is above, the effect is exhibited.

第3図は、上記方法で作製したヘテロ接合ダイオードの
I−V特性を示すもので、アニール処理を行なった場合
6はアニール処理を行わない場合7に比べ、暗電流が1
〜2桁減少する。
FIG. 3 shows the IV characteristics of the heterojunction diode manufactured by the above method, in which the dark current is 6 in the case where the annealing treatment is performed as compared with the case 7 in which the annealing treatment is not performed.
~ 2 digits decrease.

なお、本発明のアニール処理は、非晶質シリコンカーバ
イト膜の形成後電極形成前に行ってもよい。
The annealing treatment of the present invention may be performed after forming the amorphous silicon carbide film and before forming the electrodes.

アニール処理によって暗電流が減少する理由を調べるた
めに、上記方法で作製したヘテロ接合ダイオードの非晶
質シリコンカーバイト膜中からの水素の熱脱離の測定を
行なった。第4図は昇温速度20℃/分での測定結果で、
放出曲線が3つのピークから構成されていることがわか
る。それらのうち最も低温(約180℃)のピークが非晶
質シリコンカーバイト膜中に含まれる結合状態にない有
離水素の放出ピークで、他の2つのピーク(約450℃、
約750℃)は結合状態の水素の放出ピークであると考え
られる。このことから第2図を使ってアニール処理の効
果について説明すると、200℃までは非晶質シリコンカ
ーバイト膜中に含まれる結合状態にない有離水素が1時
間程度の短時間のアニール処理ではシリコン基板のプラ
ズマダメージによる欠陥を埋めるのに到らないために暗
電流はアニール処理前と不変であるが、200℃〜300℃で
は結合状態にない有離水素がシリコン基板のプラズマダ
メージによる欠陥を充分に埋めて界面の欠陥準位を通し
ての再結合電流が減少し暗電流は減少する、ところが30
0℃になると結合状態の水素が放出され膜中にダングリ
ングボンド(未結合手)が発生するために暗電流が増大
すると考えられる。
In order to investigate the reason why the dark current is decreased by the annealing treatment, the thermal desorption of hydrogen from the amorphous silicon carbide film of the heterojunction diode manufactured by the above method was measured. Figure 4 shows the measurement results at a heating rate of 20 ° C / min.
It can be seen that the release curve is composed of three peaks. Among them, the lowest temperature peak (about 180 ° C) is the release peak of free hydrogen in the bonded silicon contained in the amorphous silicon carbide film, and the other two peaks (about 450 ° C,
Approximately 750 ° C) is considered to be the release peak of hydrogen in the bound state. From this, the effect of annealing treatment will be explained with reference to FIG. 2. Up to 200 ° C., the amount of isolated hydrogen contained in the amorphous silicon carbide film that is not in a bonded state is about 1 hour in a short annealing treatment. The dark current is unchanged from that before annealing because it does not fill the defects due to the plasma damage of the silicon substrate, but at 200 ℃ ~ 300 ℃ the isolated hydrogen which is not in the bonded state causes the defects due to the plasma damage of the silicon substrate. By fully filling the interface, the recombination current through the defect level at the interface is reduced and the dark current is reduced.
It is considered that at 0 ° C., hydrogen in a bonded state is released and dangling bonds (unbonded hands) are generated in the film, so that the dark current is increased.

発明の効果 上記本発明の製造方法によれば、アニール処理を行い、
基板表面のプラズマダメージを緩和することによって、
暗電流を低減でき、非晶質シリコンカーバイト膜を用い
た高性能なヘテロ接合ダイオードの実現に実用上極めて
有効である。
Effects of the Invention According to the manufacturing method of the present invention, an annealing treatment is performed,
By mitigating plasma damage on the substrate surface,
The dark current can be reduced, and it is extremely effective in practice for realizing a high-performance heterojunction diode using an amorphous silicon carbide film.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施例の工程を示す説明図、第2図は
逆バイアス印加状態での暗電流のアニール温度依存性を
示す図、第3図は実施例のヘテロ接合ダイオードのI−
V特性を示す図、第4図は非晶質シリコンカーバイト膜
中の水素の熱脱離を測定した図である。 1……シリコン結晶基板、2……非晶質シリコンカーバ
イト膜、3……メタルマスク、4,5……アルミニウム電
極、6……アニール処理有、7……アニール処理無。
FIG. 1 is an explanatory view showing a process of an embodiment of the present invention, FIG. 2 is a view showing an annealing temperature dependency of dark current in a reverse bias applied state, and FIG. 3 is an I-of a heterojunction diode of the embodiment.
FIG. 4 is a diagram showing V characteristics, and FIG. 4 is a diagram in which the thermal desorption of hydrogen in the amorphous silicon carbide film was measured. 1 ... Silicon crystal substrate, 2 ... Amorphous silicon carbide film, 3 ... Metal mask, 4,5 ... Aluminum electrode, 6 ... Annealing treatment, 7 ... No annealing treatment.

フロントページの続き (72)発明者 平尾 孝 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (56)参考文献 Japanese Journal o f Applied Physics,P art1、Vol.23,No.5,P. 515−524(1984)Front Page Continuation (72) Inventor Takashi Hirao 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References Japanese Journal of Applied Physics, Part 1, Vol. 23, No. 5, P. 515-524 (1984)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】プラズマCVD法によってシリコン単結晶基
板上に水素を含有する非晶質シリコンカーバイト膜を堆
積したヘテロ接合の両面にオーミック電極を形成したダ
イオードの製造において、アニール処理を行うことによ
り非晶質シリコンカーバイト膜中に含まれる結合状態に
ない遊離水素を活性化させ、シリコン基板に発生したプ
ラズマダメージによる欠陥を埋めさせることを特徴とす
るヘテロ接合ダイオードの製造方法。
1. In manufacturing a diode in which ohmic electrodes are formed on both surfaces of a heterojunction in which an amorphous silicon carbide film containing hydrogen is deposited on a silicon single crystal substrate by a plasma CVD method, an annealing treatment is performed. A method for manufacturing a heterojunction diode, characterized in that free hydrogen contained in an amorphous silicon carbide film which is not in a bound state is activated to fill a defect due to plasma damage generated in a silicon substrate.
【請求項2】アニール処理を100℃〜300℃の温度範囲で
行うことを特徴とする特許請求の範囲第1項記載のヘテ
ロ接合ダイオードの製造方法。
2. The method for manufacturing a heterojunction diode according to claim 1, wherein the annealing treatment is performed in a temperature range of 100 ° C. to 300 ° C.
JP1043707A 1989-02-23 1989-02-23 Heterojunction diode manufacturing method Expired - Fee Related JPH07109904B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1043707A JPH07109904B2 (en) 1989-02-23 1989-02-23 Heterojunction diode manufacturing method
US07/483,872 US5070027A (en) 1989-02-23 1990-02-23 Method of forming a heterostructure diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1043707A JPH07109904B2 (en) 1989-02-23 1989-02-23 Heterojunction diode manufacturing method

Publications (2)

Publication Number Publication Date
JPH02222179A JPH02222179A (en) 1990-09-04
JPH07109904B2 true JPH07109904B2 (en) 1995-11-22

Family

ID=12671286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1043707A Expired - Fee Related JPH07109904B2 (en) 1989-02-23 1989-02-23 Heterojunction diode manufacturing method

Country Status (1)

Country Link
JP (1) JPH07109904B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2801502B2 (en) * 1992-09-11 1998-09-21 松下電器産業株式会社 Metal film deposition apparatus and metal film deposition method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JapaneseJournalofAppliedPhysics,Part1、Vol.23,No.5,P.515−524(1984)

Also Published As

Publication number Publication date
JPH02222179A (en) 1990-09-04

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