JPH07111352B2 - Analysis section calculation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention is an apparatus for analyzing various time-series signals including an abnormal signal value, and an analysis section (start point and start point) having a constant time width with respect to a certain time of the time-series signal. In the device that performs analysis using the signal value of (end point), an analysis permission signal indicating whether analysis is permitted or prohibited is integrated at each time during analysis permission,
This integrated value is stored in the memory at each time, while each time information is stored in two memories at each time by using the integrated value as an address, and the read addresses of the two memories are adjusted next to each output time. It outputs the start time and end time of the corresponding analysis section.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analysis section calculation device in a device that analyzes various time series signals.

Examples of the time-series signal analysis device include an ultrasonic diagnostic device, a radar, and various calculation devices.

[Prior Art] There are various types of time-series signal analyzers that output an average value of data in a certain time interval as a function of a change in time, such as a moving average.

For example, FIG. As shown in, the sample value of each minute time of the time-series signal is obtained, and the calculation of the time t to be analyzed is performed using the values of the start point and the end point of the time section T centered on the time t. . That is, FIG. 3 (d) b. The time t ₁ , t ₂ around T / 2 hours with respect to
The value of is used.

In that case, since the section length is constant, it was easy to calculate the start time and the end time of each analysis section.

On the other hand, when the signal contains an unnecessary signal component such as noise, for example, in FIG. For signals such as that shown in (1), there has been a growing demand for analysis without using data at times when unnecessary signal components are included.

As an answer to this, c. As shown in, the time when noise is included takes "0" as the value, and the time when noise is not taken takes "1" as the value, and the binary analysis permission signal (weight function signal) is There is one that obtains an output that is not affected by noise from the analysis permission signal and the original time-series signal by obtaining the serial signal by preprocessing.

In this case, do not use the signal while the analysis permission signal is "0", and perform the analysis in a fixed analysis section length (a time around T / 2, which is constant with respect to t, regardless of the analysis permission signal). However, the number of valid data was insufficient and the analysis output with sufficient accuracy could not be obtained.

Therefore, analysis has been started by changing the analysis interval length so that the number of data used for analysis is constant without using the signal when the analysis permission signal is "0". .

As a device for calculating an analysis interval (a time around T / 2 hours for a certain analysis time) in a device using such an analysis method, a conventionally known specific example is not known,
The configurations shown in FIGS. 3A and 3B are conceivable.

In the figure, 30 is a counting circuit, 31 is a memory, and 32 is an MPU (microprocessor unit).

First, the counting circuit 30 shown in FIG. 3 (a) counts the clock signal CLK and supplies the address input of the memory 31 with the data corresponding to each moment as its output.

Therefore, the state of 1,0 at each time point of the analysis permission signal shown in FIG. 3C is sequentially stored in the memory 31 at each address (time position). Next, as shown in FIG. 3 (b), MP
Using U32, the start time t ₁ and the end time t ₂ of the analysis section corresponding to the output time t are obtained. In that case, the analysis permission signal is searched from the time t toward the direction of the positive time and the direction of the negative time, and the time when the sum of the times when the value of the analysis permission signal is 1 is T / 2 is searched for. Is.

[Problems to be solved by the invention]

As described above, the conventional method requires at least T times of memory access and addition processing for each output time. Therefore, if the data length is N, at least N × T memory accesses and additions are required.

As described above, there is a problem that real-time processing is difficult because a large amount of calculation is required to determine the analysis section.

[Means for solving problems]

The present invention provides an analysis permission signal indicating whether analysis is permitted or prohibited in an apparatus that performs analysis using signal values of an analysis section (start point and end point) of a constant time width for a certain time of a time series signal. While the analysis is permitted, integration is performed at each time, and the integrated value is stored in the memory at each time, while each time information is stored in two memories at each time using the integrated value as an address.
Next, the read addresses of the two memories are adjusted to output the start time and end time of the analysis section corresponding to each output time.

The principle configuration of the present invention is shown in FIGS. 1 (a) and 1 (c).
FIGS. 1 (b) and 1 (d) are views for explaining the respective operations.

In FIG. 1A, 10 is an integrating circuit, 11 to 13 are memories 1 to 3, 14 is a counting circuit for counting clock signals, 100 is an analysis permission signal, 120 is a clear signal,
Reference numeral 130 represents a clock signal, which is 11 in FIG.
1 to 14 are the same as those in FIG. 1 (a), 15 is a polarity conversion circuit, 16 and 17 are addition circuits, 170 is an input line for numerical values corresponding to T / 2 hours, and 150 and 160 are analysis sections respectively. Indicates the output of start time and end time.

[Operation] First, the time signal accumulating operation according to FIG. 1A will be described.

When the analysis permission signal 100 is input to the integrating circuit 10, the integrating circuit 1
At 0, the ENABLE terminal receives the analysis permission signal of the waveform shown in FIG. 1 (b), and only when the value is 1, accepts the input of the clock signal 130 to perform integration (counting), and the counting circuit 14 causes the clock signal 130 to operate. Are sequentially counted to output time data from the output line 140.

On the other hand, in the memory 1, the memory 2, and the memory 3, data is written by the write control signal WR at each time (every clock), and the memory 1 receives the output of the integrating circuit 10 as the data input and outputs the output of the counting circuit 14. Stored as an address, the memories 2 and 3 use the output of the counting circuit 14 as a data input,
Storage is performed using the output of the integrating circuit 10 as an address.

In this way, as shown in FIG.
After the data are respectively stored in 3, the analysis section data is obtained by the configuration shown in FIG. 1 (c).

That is, the counting circuit 1 which supplies the read control signal RD to the memories 1 to 3 of FIG. 1C and counts the clock signal 130.
The data of the memory 1 is read using the output of 4 (representing time t) as an address.

The output data of the memory 1 is output as a value in the X-axis (horizontal) direction in FIG. 1 (d). When the data corresponding to T / 2 time is supplied to the data at the time t from the input line 170, the adder circuit 1
At 7, the address corresponding to the time T / 2 is added to the address at time t, the result is used as an address to access the memory 3, and the time data representing t ₂ in FIG. 1 (d) is output.
At the same time, the adder circuit 16 adds the address at time t and the polarity converter circuit 15 with the data corresponding to the negative sign T / 2 time, and the result is read as the address of the memory 2 and the result of FIG. The time data representing t ₁ in d) is output.

In this way, there is always a fixed time (a fixed number of data) for each time on the time axis of the 1 state of the analysis permission signal.
Only the plus and minus analysis sections are calculated.

[Embodiment] FIG. 2 shows the configuration of an embodiment of the present invention.

In the figure, 30 is an integrating circuit, 31 to 33 are memory 1, memory 2, memories 3 and 34 are counting circuits, 35 is a polarity converting circuit,
Reference numerals 36 and 37 denote adder circuits, which correspond to the circuits or devices of the symbols 10 to 17 in FIGS. 1A and 1C.

38 and 39 are switching circuits that specify whether the device is in a data writing state (a state in which contacts a and b are connected) or a data reading state (a state in which contacts a and c are connected), and 39 is a contact point. "0" data is stored in b, and "T / 2" is stored in contact c.
Data corresponding to time is supplied to each, and 40 is an integrating circuit 30
And clock signal 330 and clear signal 320 to counting circuit 34
Of the timing control circuit for controlling the switching circuits 38 and 39, the generation of the data, the supply of the read / write control signals to the memories 1 to 3 and the supply of the read control signals.

In the case of writing data in FIG. 2, the timing control circuit 40 causes the switching circuits 38 and 39 to change contact points a and b, respectively.
The write addresses of the memories 2 and 3 are added with the output of the integrating circuit 30 and the “0” output from the switching circuit 39 in the adding circuits 36 and 37, and finally the output of the integrating circuit 30 is given.

The weighting function signal (corresponding to the analysis permission signal in FIG. 1) 300 is input to the integrating circuit 30, the integration is performed according to the clock signal 330, the counting circuit 34 performs time counting, and the timing control circuit in the memories 1 to 3. Data writing for each clock signal by the write control signal 340 from 40 is executed in real time, and the operation principle thereof is as described in FIGS. 1 (a) and 1 (b).

After writing the data, the analysis interval signal is calculated by reading the data next.

In that case, the timing control circuit 40 causes the switching circuits 38, 39
The contacts a and c are connected by switching control.

As a result, the read address of the memory 2 is supplied to the adder circuit 36 together with the output of the memory 1 because the numerical value data of T / 2 becomes a negative value in the polarity conversion circuit 35 and is supplied from the output of the memory 1 to T / 2. Only the value of is subtracted.

Further, the read address of the memory 3 is obtained by adding the value of T / 2 from the time of the memory 1 because the numerical data of T / 2 and the output of the memory 1 are added by the adder circuit.

The reading is performed in real time (without the calculation processing time) by supplying the clock signal 330 from the timing control circuit 40 to the counting circuit 34 and giving the read control signal to the memories 1 to 3 for each clock signal. The operating principle thereof is as described with reference to FIGS. 1 (c) and 1 (d).

By this reading, the output data 360 and 370 of the memory 2 and the memory 3 are given time t supplied from the counting circuit 34, respectively.
On the other hand, the output showing the time before and after T / 2 hours when the number of data becomes constant is obtained.

EFFECTS OF THE INVENTION According to the present invention, when it is necessary to calculate an analysis section before and after a fixed time corresponding to each time such as a moving average of a time-series signal including a signal section unsuitable for analysis In addition, the time data representing each section can be obtained almost in real time. Specifically, assuming that the data length is N, calculation can be performed by 2N times of memory access and address addition, and addition and memory access are performed simultaneously. Therefore, the third
It can be calculated at a speed of about T times or more compared with the conventional method shown in the figure.

[Brief description of drawings]

1 (a) to 1 (d) are views for explaining the principle configuration and operation of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIGS. 3 (a) to 3 (D) is a figure explaining the structure of a prior art example, and the relationship of a time series signal and an analysis permission signal. 1 (a) and 1 (c) 10: Integration circuit 11 to 13: Memory 1 to memory 3 14: Count circuit 100: Analysis permission signal 120: Clear signal 130: Clock signal 15: Polarity conversion circuit 16 , 17: Adder circuit 170: T / 2 hour value input line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G01S 7/526

Claims (1)

[Claims] 1. An analysis interval calculation device in a device for analyzing a time-series signal including a time interval in which analysis is prohibited by using signal function values of a predetermined time width before and after each analysis target time, Means (10) for integrating the time when the binary analysis permission signal obtained from the time-series signal is at one value, time counting means (14), and integrating means using each output of the time counting means as an address. A first memory (11) for storing the output of the counting means, and second and third memories (12, 13) for storing the output of the counting means using the output of the integrating means as an address, and the first memory It is provided with means (16, 17) for generating two addresses separated by the analysis time width (T) by using the read output of the above as an input, and by the two addresses, the start point and the end point of the analysis section are output from the second and third memories. Configured to read time data in real time An analysis interval calculation device characterized by the above.