JPH07111442B2 - Waveform storage - Google Patents

Description

The present invention relates to sampling control of a waveform storage device.

[Outline of Invention]

When the sampling speed becomes faster than the access time of the memory, a method of preparing a plurality of memories in parallel and storing them sequentially is used. (Hereinafter, this is referred to as a polyphase memory.) When this polyphase memory is used, the positional relationship between the stored waveform data and the trigger is in addition to the case of the single-phase memory and the relationship between the trigger and the memory address. Therefore, it is necessary to have information on what phase the trigger was generated. The present invention describes a circuit system for obtaining information on which phase the trigger has occurred, and realizes this without using a high-speed circuit.

[Conventional technology]

FIG. 3 is a block diagram showing an example of the prior art, and FIG. 4 is a time chart similarly. Reference numeral 1 is an AD converter, 2 to 5 are latches, 6 to 9 are memories, 10 is a 4-phase signal generation circuit, 14 is a counter circuit for controlling the number of samples which operates at high speed, 12 is a D type flip-flop, and 21 is a tri-state buffer. The circuit, 20 is a microprocessor. The operation will be described below.

AD converter 1 performs AD conversion according to a clock (hereinafter referred to as CLK) and outputs digital waveform data A. The four-phase signal generation circuit 10 outputs signals B, C, D, and E that are 1/4 the frequency of CLK and are out of phase by one CLK cycle. Latches 2 to 5 sequentially latch the digital waveform data A by the signals B, C, D and E. The output of this latch is CL, which is the sampling rate.
It becomes 1/4 frequency rate of K. Next, the data is written in the memories 6 to 9. (In this example, consider that the memories 6 to 9 are FIFO-like.) The waveform data AD-converted in this way are sequentially stored in the memories 6 to 9. Next, when a trigger signal is input from TRIG, the high-speed sample number control counter 14 that operates at the same frequency as CLK thereafter starts counting CLK, and outputs a count end flag J when a predetermined number has been counted. This signal J is latched by the D time flip-flop 12 at the next CLK, the signal L becomes low level, and the four-phase signal generation circuit 10 receives C
The LK signal does not come in, the four-phase signals B to E stop, and writing to the memories 6 to 9 stops.

The phase of the memory in which the trigger is generated can be obtained by the microprocessor 20 reading the states of the four-phase signals B to E through the buffer circuit 21. (Because the four-phase signal generation circuit 10 is stopped by counting the predetermined number of CLK signals from the time of TRIG signal, there is a one-to-one correlation between the signals B to E at the time of TRIG and when writing is stopped. After that, the microprocessor 20 determines the reading order of the waveform data in the memories 6 to 9 according to the states of the read signals B to E, and transfers the waveform data to a display circuit (not shown).

[Problems to be Solved by the Invention]

Here, the counter circuit 14 for controlling the number of samples used in the above-mentioned conventional technique must operate at the same frequency as the sampling rate CLK, and therefore must be a high-speed counter circuit. Also, since the number of counts corresponding to the memory capacity is required, the number of bits of the count must be increased as the number of phases of the multi-phase memory (in the above example, four phases are used). A counter circuit that is high-speed and has a large number of counts is expensive, and it must be a circuit that always considers synchronization with CLK, which makes logic difficult. Further, if the sample rate becomes higher, there will be a limit that cannot be realized. The present invention aims to overcome these drawbacks.

[Means for Solving the Problems]

According to the present invention, in the multi-phase memory system, the detection of the trigger position is divided into two circuits in order to achieve the above object. The first is a sample number control circuit which looks at all the phases as one group and counts every time when all the phases are stored by one word or several words after a trigger is input. Second
Is a circuit that measures the time from the trigger to a certain phase.

These two circuits control sampling and detect the trigger position. The first circuit only needs to be able to operate at a frequency that is a fraction of the number of phases of the memory with respect to the sampling rate, and can cope with an increase in the number of phases without changing anything. Second
As an example, since it suffices to have a dual slope circuit and a counter, there is an advantage that a high-speed sample number control counter circuit is not required and high-speed parts can be reduced.

[Action]

As a result, the above-mentioned first circuit has only to operate at a fraction of the number of phases of the memory with respect to the sampling rate, so that a relatively low-speed circuit can be used. The second circuit provides the correlation between the trigger position and the memory phase. Therefore, sampling control and trigger position detection can be obtained without using the high-speed counter circuit as shown in the prior art.

〔Example〕

A block diagram of one embodiment of the present invention is shown in FIG. 1, and a time chart is shown in FIG. In both figures, the same reference numerals as those in FIGS. 3 and 4 indicate the same items. Further, in this embodiment, four phases will be described as in the conventional example, but the number of phases such as 16 phases and 32 phases is not limited. The waveform data A output from the AD converter 1 is latched by the latch circuits 2 to 5 and stored in the memory circuits 6 to 9 in the same manner as the above-mentioned conventional technique. The first difference is that the sample number control counter circuit 14 'counts a D phase signal instead of CLK. (That is, for the sample number control counter 14 in FIG.
The counter 14 'shown in the figure may operate at a speed of 1/4. After the trigger signal (TRIG), the counter 14 'for controlling the number of samples counts each time the memory of all phases stores one word, counts a predetermined number of counts, and outputs the sample end flag J. The sample end flag is synchronized with CLK by the D flip-flop circuits 13 and 12, and the 4-phase signal generation circuit 10 is stopped.
Terminate the memory storage operation. However, in this circuit, the storage operation is always stopped when the memory 9 is completely written, so that it is not possible to know the phase of the memory in which the trigger was located. Therefore, the second difference from the conventional one is that it has a circuit for measuring the time from the trigger to a certain phase, and the pulse generator circuit 15 dual slope generator circuit 16, comparator circuit 17, AND circuit 18, counter circuit 19, An example is a circuit for detecting the trigger position, which is composed of the frequency dividing circuit 22. The operation of this circuit is explained below.
15 is for G from trigger signal (TRIG) to the next B-phase signal
High level is output. Dual slope circuit 16
The peak value of the output H increases in proportion to the High level period. That is, the peak value of the output H is proportional to the time from the trigger signal to the B-phase signal, and the peak value H decreases with time from the moment G becomes the Low level (that is, the time when the B-phase signal is input). At this time, the way of falling is proportional to time. The comparator 17 is at a high level until the output H rises and then falls, and the AND circuit 18 passes the CLK whose frequency is divided by the frequency divider 22. The counter circuit 19 counts the number. As described above, the time when the output H of the dual slope circuit falls is proportional to the peak value (the time when it rises). For example, the rising and falling slopes of the output of the dual slope circuit 16 are 1: 1000. In this case, the period when the output G is High can be extended 1000 times equivalently. Therefore, the counter circuit 19 does not need to have high speed.

Since the count value of the counter circuit 19 is proportional to the time difference from the trigger signal to the timing B of the first phase, the microprocessor 20 must read the calculated value of the counter circuit 19 to know the timing relationship between the trigger and memory phases. You can

〔The invention's effect〕

According to the present invention, it becomes possible to realize a sample control circuit of a waveform storage device using a polyphase memory with a cheaper low-speed circuit. Also, it is possible to deal with the increase in the number of phases of the multi-phase memory without adding anything.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart of FIG. FIG. 3 is a block diagram showing an embodiment of the prior art, and FIG. 4 is a time chart of FIG. 1: AD converter, 2 to 5: Latch, 6 to 9: Memory, 10: 4-phase signal generation circuit, 11: AND circuit, 12 to 13: D flip-flop, 14, 1
4 ': counter circuit for controlling the number of samples, 15: pulse generator circuit, 16: dual slope generator circuit, 17: comparator circuit, 18: AND circuit, 19: counter circuit, 20: microprocessor, 22: frequency divider, 21 : Tri-state buffer.

Claims (1)

[Claims] 1. A waveform storage device for analog-digital converting an input signal and storing the same, wherein the waveform data is sequentially written into the plurality of memories when the plurality of memories are provided and the waveform data are sequentially stored. Means for reducing the storage speed of the above-mentioned analog-to-digital conversion speed, counting each time one word or a plurality of words is written in all the plurality of memories, and stopping writing when a predetermined number is reached, and a plurality of all the memories. Charging is started at the timing of the trigger signal that comes within the period of writing one word or a plurality of words at a time, and the charging is ended and the discharge is started at the timing of the writing signal to any of the plurality of memories that follows. And a dual-slope circuit that compares the dual-slope signal with a reference voltage. The dual slope signal of the rope circuit has a counter that counts a clock signal by the comparator output signal while the reference voltage is exceeded, and the time between the trigger signal and the write signal to the arbitrary memory according to the count value of the counter. A waveform storage device having means for measuring a relationship.