JPH07111626B2 - Performance pattern writing device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a performance pattern writing device, and more particularly to a technique for inputting a performance pattern in real time.

[Prior Art] In a performance pattern writing device, the first point that must be taken into consideration when recording a pattern to be played in real time in a digital memory is processing for each timing of the performance. That is, it is to determine in which time slot of the time when the key depression occurs in the time managed by the musical instrument, and determine the address of the corresponding memory.

There are two known conventional techniques in this respect.

The first is to use an address counter that is stepped at a fixed interval, and when the support pattern is flown together with this interval, when the key is pressed, the value of the address counter at that time is used as the write address. is there. According to this
The value of the address counter incremented by the last increment clock generated before key depression always occurs becomes the write address.

The second one is the same as the first one in that the support pattern is flown and the address counter is used, but writing is not performed immediately even if a key is pressed, and when the address counter is advanced by the next advance clock. The contents are written using the contents as a write address. According to this, the value of the address counter incremented by the first increment clock that always occurs after the key depression occurs becomes the write address.

In both the first and second cases, a shift in the storage timing corresponding to the stepping cycle of the address counter is likely to occur. For example, the first
Even if there is a key press just before the address counter is stepped up, the value closer to the timing,
That is, the write address is not the value of the address counter that is incremented by the next increment clock, but the farther value, that is, the value of the current address counter that is about to advance. The second one is inconvenient under the opposite situation, and the value of the address counter corresponding to the farther timing becomes the write address. For this reason, when reproduced, the pattern is not output at the timing intended by the performer, which often causes a musical unnaturalness.

[Object of the Invention] The present invention has been made in view of the above circumstances, and provides a performance pattern writing device capable of easily obtaining an accompaniment pattern that matches a timing intended by a performer without special practice. The purpose is to do.

[Summary of the Invention] In order to achieve the above object, the present invention provides a fine adjustment time zone before and after each step timing of the address counter, and determines which time zone the operation input generation timing belongs to. Therefore, the main point is that the write address (storage timing) is obtained.

[Operation] According to the present invention, fine adjustment time zones are provided not on one side of each step timing of the address counter but on both sides, and the output of the address counter is adjusted by specifying the time zone to which the operation input timing belongs. To obtain a write address. As a support for input, for example, when a pattern that coincides with the step timing of the address counter is flowed, there is a variation in the key operation timing of the player who attempts to input along with this pattern. That is, in some cases, the key is pressed slightly before a certain step timing, and in some cases, the key is pressed a little later than the step timing. In such a case, according to the present invention, when the key is pressed slightly before the step clock C (N), the timing of the step clock C (N) becomes the storage timing, and the step clock C (N) is stored. When the key is pressed a little later, the timing of the step clock C (N) becomes the storage timing. That is, in either case, the processing is performed at the timing intended by the performer. Therefore,
As a whole, the timing pattern intended by the player can be easily created.

An input performance pattern can be used as an example of the support pattern. In other words, the data that has been input is read from the next writing cycle and the sound is emitted.

In order to create a playing pattern, when the performer performs key operation while playing the support pattern on the instrument side or sequentially displaying LEDs etc. at predetermined timing,
The key operation timing tends to be delayed or advanced from the timing of the support pattern (stepping timing of the address counter) due to individual differences. One player performs the key operation mainly at a timing slightly before the timing of the support pattern, and another player performs the key operation at a timing slightly after the timing of the support pattern. In consideration of such individual differences and the like, it is preferable that each user can freely select and set the fine adjustment time zone. By providing the variable setting time zone, it is possible to individually compensate for the deviation that tends to occur between the timing intended by the performer and the timing at which the performer actually operates.

In other words, the present invention is characterized in that the read timing of the support pattern or the lighting display timing of the LED or the like and the step timing of the write address of the performance pattern are relatively adjusted. Therefore, as one modification, the stepping / reading timing of the read address on the support pattern side may be shifted by the time adjustment width from the stepping timing of the write address on the write pattern side. For example, the reading of the support pattern can be configured to occur in the middle of the stepping cycle of the address on the writing side.
This uses, for example, a quaternary counter for timing adjustment, and when this counter reaches "2", the read address of the support pattern is incremented to read the pattern and the adjustment counter is set to "0". This can be achieved by advancing the write address of the performance pattern when it becomes.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

The overall structure of this embodiment is shown in FIG. In the figure, 1 is a keyboard, 2 is a CPU that controls the entire apparatus, 3 is a program memory that stores programs used by the CPU 2, 4 is an accompaniment pattern memory that stores each accompaniment pattern of rhythm, bass, and chord, and 5 is a rhythm Sound source, 6 is a sound source for melody, bass, chord, 7 is a sound source of sampled sound, 8, 9 and 10 are microphones for inputting sampled sound,
Amplifiers, A / D converters, 11, 12, and 13 are D / A converters, amplifiers, and speakers for outputting the tone signals generated by the sound sources 5, 6, and 7.

In the present embodiment, the output of the address counter that is stepped at the regular timing is used for adjustment during key depression in order to create the performance pattern of the key information input by the player while outputting the sample pattern at the regular timing. Whether or not to add 1 is determined according to the value of the counter of, and the storage timing of each key operation is obtained using the value obtained as a result as the write address.

A block diagram relating to this function is shown in FIG. In the figure, all elements other than the pattern creation memory 41 and the support pattern memory 42 are functional elements of the CPU 2 in FIG.

2-1 to 2-6 are for giving a write address,
The counter 2-2 for timing adjustment is incremented by the clock 2-1 and the address counter 2-3 is incremented by the carry (normal timing). The count output A of the timing adjustment counter 2-2 is output by the comparator 2-4.
It is compared with the adjustment value B from the margin adjusting unit. When the count output A> the adjustment value B, that is, when the content of the adjustment counter 2-2 for measuring from the arrival of the regular timing to the arrival of the next regular timing becomes longer than a certain adjustment value B , The comparator 2-4 outputs "1" to enable the plus one 2-6 and gives a value obtained by adding 1 to the content of the address counter 2-3 to the pattern forming memory 41 as a write address. However, when the time has not passed so far (A <B), the output of the comparator 2-4 is “0”, the plus one 2-6 does not operate, and the value of the address counter 2-3 is written as it is. It becomes an address.

The carry of the timing adjustment counter 2-2 is also used as a read timing to the pattern reading unit 2-7, and the pattern reading unit 2-7 which receives the carry advances the internal address to generate the support pattern memory 42 and the pattern creation. The memory 41 is accessed to read the data. The read data is passed to the output control unit to create a musical tone signal,
Finally output to the outside.

While the support pattern is sounding, the performer operates the keys to input the performance pattern. By the key scan 2-8, the key depression and its key information are detected, and the key depression detection signal is input to the pattern creation memory 41 as a write signal, and the key information relating to the key depression is written at the write address at that time. Be done. Here, when the time set by the margin adjusting unit 2-5 has not yet passed from the normal timing, the content of the address counter 2-3 becomes the write address, but when it has passed, the address counter 2
A value obtained by adding 1 to the content of -3 becomes the write address.
Generally speaking, when the address counter 2-3 is shortly incremented, the content is the write address as it is, and when the address counter 2-3 is shortly incremented, the value after the step is incremented. This is a write address. That is, a time zone is provided before and after each regular stepping timing of the address counter, and when a key is pressed, it is determined which time zone the timing belongs to.

In the present embodiment, the pattern once input to the pattern creation memory 41 is read from the next writing cycle via the pattern continuous section 2-7 and is emitted to the outside. However, at the time of input, the mode of output is different depending on whether it occurred before or after the normal timing. That is, when the input is made earlier than the normal timing, it is already stored in the pattern creation memory 41 at the time of the normal timing, so that it is read by the pattern reading unit 2-7. However, when the input is delayed from the regular timing, the pattern reading unit 2-7 cannot read the input information until the regular timing comes again in the next write cycle. Therefore, in this case, immediate output is performed. That is, the gate 2-9 is enabled by the delay signal defined by the output "0" of the comparator 2-4, and the key information related to the key depression is passed to the output control unit.

FIG. 3 shows a flow chart of the detailed operation of the CPU 2 and FIG. 4 shows an input example. A part related to the present invention will be described. Here, a set rhythm, bass, and chord accompaniment pattern is used as a support pattern, and a performance pattern to be created is shown as a bass pattern. However, using other patterns (eg tempo, rhythm pattern only for bass drum, etc.) as support patterns and other patterns (eg rhythm pattern, chord pattern) as performance patterns is within the range of easy transformation. Can be achieved with.

First, in order to select a support pattern, the performer selects a predetermined rhythm pattern (S2, S6, S7, S9). next,
Set the base pattern writing mode (S2, S6, S7, S
8). Then, in order to actually enable writing, start the rhythm with rhythm start / stop (S2, S6,
S7, S9; S13-1 and below).

On the other hand, the CPU2 internally sets the rhythm ON flag and ON flag and resets the internal adjustment counter and address counter, and increments the adjustment counter each time the internal timer times out. )
Each time it reaches 3, it increments by 3 and increments the address counter so that the address counter (here)
-32 to return to the beginning of the bar after reaching 32.

Each time the rhythm address counter is incremented, the rhythm and accompaniment patterns are read as the rhythm read timing (S4-2), the data format of the patterns is converted, and the related sound source section is data set and sound is produced (S4). -3 to S4-7, S4-10).

While such a support pattern is output, the performer inputs a bass pattern. FIG. 4 shows the key input timing for the second and third beats.
The key operation at the beat occurs when the value of the address counter is 15 and the value of the adjustment counter is 2. Since the intended timing is the beginning of "3rd beat", the write address must be "16" instead of "15". That is, in this example, the key operation is performed before the regular timing. On the other hand, the key operation of the second beat is an example that occurs after the normal timing, and at this time, the value of the address counter is "8" and the value of the adjustment counter is "0".

If the key operation is performed before the regular timing,
In S13-3 of FIG. 4, it is determined as "Sumi", and in S13-4, the address counter plus 1 is set as a write address, and in S13-7, key information related to key depression is written. In this case, since the memory writing is performed at the arrival of the normal timing, it is output as an accompaniment person (S4-2, S4-
7, S4-10).

On the other hand, when the key operation is performed later than the normal timing, it is determined as "delay" in S13-3 of FIG. 4, and S13-
The value of the address counter is set as it is as the write address in 5, the delay flag is set in S13-6, the input data is written in the write address in S13-7, and S13-8 to S13.
-2, the key information is converted into accompaniment data for immediate pronunciation, and S4-1, S4-8, S4-9, and S4 of the rhythm accompaniment processing are performed.
Play the note through -10.

As a result of the above processing, in the example of FIG. 4, the bass sound data of the second beat is at address "8" representing the normal timing of the head of the second beat, and similarly the bass sound data of the third beat is 3 It is placed at address "16", which represents the normal timing of the beginning of the beat.

In the above embodiment, the operation information input at a predetermined timing is obtained using a key. However, for example, various operation input means such as a key switch, a pattern input pad, and a drum pad are used. You may get it. Further, in the above-described embodiment, the case where the operation information is input in synchronization with the support pattern has been described, but the operation information may be input in synchronization with the lighting timing of the LED or the like, for example.

[Effects of the Invention] As described above in detail, in the present invention, the shift of the key operation is performed before and after each normal step timing of the address counter which is stepped in synchronization with the normal timing defined by the clock. The time width is set in anticipation of this, and the write address is calculated according to the time width of the operation timing of the operation input, so the timing intended by the performer can be interpreted more accurately than before, and pattern creation is possible. Can be done smoothly.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a functional block diagram of essential parts of the embodiment, FIG. 3 is a flowchart of operation of the embodiment, and FIG. 4 is a diagram showing an example of pattern input. Is. 2-2 ... Timing adjustment counter 2-3 ... Address counter, 2-4 ... Comparator, 2-5 ... Margin adjustment, 2-6 ... Plus one, 2-7 ... Pattern reading, 2 -8 …… Key scan, 41 …… Pattern creation memory, 42 …… Support pattern memory.

Claims (1)

[Claims] 1. A real-time performance pattern book in which a performance pattern is written by allocating a write address that is stepped in synchronization with a regular timing defined by a clock as a storage timing of operation information input at a predetermined timing. In the performance pattern writing device provided with the input means, the performance pattern writing means includes an adjustment time zone giving means for providing an adjustment time zone before and after each of the regular timings, and the adjustment time zone giving means at the time of operation input. And specifying a regular timing having an adjustment time zone to which the timing of the operation input belongs, and using the address corresponding to the specified regular timing as the write address. A performance pattern writing device.