JPH07112134B2 - High frequency amplifier - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an improvement of a high-frequency amplifier in which field-effect transistors are cascade-connected in multiple stages.

Conventional technology and problems Conventionally, field effect transistors are often used because of their high input impedance for amplifying high frequencies.
The gain decreases as the handled frequency increases. For example, at frequencies of 12 to 18 [GHz], 3 to
Only gain of 4 [dB] can be obtained.

Therefore, in recent years, a high-frequency amplifier has been developed in which a plurality of field-effect transistors are formed in one chip and the gain is increased by cascade-connecting the field-effect transistors. In the conventional high frequency amplifier, one field effect transistor is usually formed on one chip.

FIG. 1 is a circuit diagram of a main part of a high frequency amplifier having the field effect transistors connected in cascade.

In the figure, Q1 and Q2 are field effect transistors, S is a source, D is a drain, G is a gate, MN is a matching circuit, C is a DC cut capacitor, L is an inductance, V _DD is a drain side supply voltage, and V is a drain side supply voltage. _GG indicates the gate bias voltage, respectively.

In this conventional example, the gate bias voltage V _GG must be applied to each transistor Q1 and Q2, and the values of the gate bias voltage V _GG and the drain side supply voltage V _DD are significantly different. Therefore, there is a DC cut capacitor C between the drain of the front stage, that is, the drain of the transistor Q1 and the gate of the rear stage, that is, the gate of the transistor Q2.
Must be intervened.

By the way, as described above, when a plurality of field effect transistors are formed on one chip and they are cascade-connected to form a circuit, this is a kind of integrated circuit, and therefore a large capacity is provided in the same chip. It is difficult, if not impossible, to form a capacitor, the occupied area becomes large, and the inductance L inserted in the gate bias voltage supply circuit also contributes to miniaturization.

The high frequency amplifier shown in FIG. 2 has been provided in an attempt to reduce such drawbacks. In FIG. 2, the same parts as those described with reference to FIG. 1 are designated by the same symbols.

In the conventional example of FIG. 2, the resistor R1 is connected to the gate of the transistor Q1.
And the resistor R2 is connected to the source, the resistor R3 is connected to the gate of the transistor Q2, and the resistor R4 is connected to the source, which is a so-called self-bias system. Note that CP is a bypass capacitor.

However, even in this improved conventional example, the DC cutting capacitor C must be used, and the number of the inductances L inserted in the circuit for applying the drain side supply voltage V _DD does not change. Not effective.

An object of the present invention is to simplify the bias circuit by reducing the number of DC cutting capacitors and inductances between stages when a plurality of field effect transistors are cascade-connected to form a multi-stage high frequency amplifier. Allows for miniaturization.

Embodiment of the Invention FIG. 3 is a circuit diagram of an essential part of an embodiment of the present invention, and the same parts as those described with reference to FIGS. 1 and 2 are designated by the same symbols.

This embodiment is different from the conventional example shown in FIGS. 1 and 2 in that the drain of the field effect transistor Q1 and the gate of the field effect transistor Q2 are directly connected in a direct current manner, and the field effect transistor Q1 is Resistor R5 between source and ground
, And R6 are inserted in series so that the voltage generated in the resistor R5 is applied to the gate as the gate bias voltage, and similarly for the field effect transistor Q2, resistors R7 and R8 are also inserted in series at the source. The voltage generated in the resistor R7 is applied to the gate as a gate bias voltage. Since the drain of the transistor Q1 and the gate of the transistor Q2 are directly connected, it goes without saying that the gate bias voltage of the transistor Q2 is applied as the drain voltage to the drain of the transistor Q1.

By adopting this configuration, the DC cut capacitor between the transistor Q1 and the transistor Q2 becomes unnecessary,
Also, the number of inductances L inserted in the circuit for applying the drain side supply voltage V _DD is reduced.

In this embodiment, the drain side supply voltage V _DD is applied to the drain of the transistor Q2, and the voltage generated in the resistor R7 is also applied to the gate of the transistor Q2 and the drain of the transistor Q1. The voltage applied across the transistor Q1 differs from the voltage applied between the drain of transistor Q1 and ground.
The voltage at Q1 is smaller. However, by appropriately selecting the values of the resistors R5 to R8, the drain-source voltage of the transistor Q1 and the drain-source voltage of the transistor Q2 are made equal, for example, 3 [V], and
It is easy to pass a current of 20 [mA].
However, when such a configuration is adopted, the number of transistors that can be cascade-connected is limited depending on the power supply voltage or the breakdown voltage of the members used, but it is not possible to configure at least several stages of amplifiers under normal conditions. There is no hindrance.

Specific numerical examples in this embodiment are as follows.

Drain-source current I _DSS = 30 [mA] transconductance g _m = 40 [m] in transistor Q1 Drain-source current I _DSS = 60 [mA] transconductance g _m = 50 [transistor g2 in transistor Q2 m] Also, V _DD = 8 [V] R ₅ = 50 [Ω] R ₆ = 0 [Ω] R ₇ = 10 [Ω] R ₈ = 160 [Ω] As a result of the above, V _DS = 3 [V] I _DS = 10 [mA] With the transistor Q2, V _DS = 4.1 [V] I _DS = 40 [mA] can be obtained.

EFFECTS OF THE INVENTION According to the present invention, in a high frequency amplifier in which a plurality of field effect transistors are cascade-connected, the front stage drain and the rear stage gate of these field effect transistors are directly connected in a direct current manner, and , A plurality of resistors are inserted in series to the sources of the field effect transistors, and the connection point between the resistors is connected to the gate to apply the gate / bias voltage and the drain voltage of the previous stage. Therefore, the DC cut capacitor between the stages is not required, and the number of inductances inserted in the circuit for applying the drain side supply voltage is also reduced. Therefore, the configuration of the bias circuit is simplified, only one power supply line is required for the plurality of field effect transistors, and the entire amplifier can be downsized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 are main circuit diagrams of a conventional example, and FIG. 3 is a main circuit diagram of one embodiment of the present invention. In the figure, Q1 and Q2 are field effect transistors, MN is a matching circuit, C is a DC cut capacitor, L is an inductance, R1 to R8 are resistors, CP is a bypass capacitor, V _DD is a drain side supply voltage, V _GG is the gate bias voltage.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Hayakawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Kazuhiro Matsumoto 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (1)

[Claims] 1. A high-frequency amplifier comprising a plurality of field-effect transistors connected in cascade, wherein the drain of the front stage and the gate of the rear stage are directly connected in direct current, and a plurality of resistors are inserted in series to the source thereof. A high-frequency amplifier comprising a plurality of field-effect transistors each having a gate connected to a connection point between resistors.