JPH07112154B2 - PLL frequency synthesizer circuit - Google Patents

Description

The present invention relates to a PLL frequency synthesizer for performing frequency modulation (hereinafter referred to as FM or FM modulation) on a reference signal by using a PLL circuit (phase locked loop circuit). It is about circuits.

(Prior Art) A PLL circuit is used for various applications such as a tuning circuit, a demodulation circuit, a modulation circuit, and the basic configuration thereof is shown in FIG.

This PLL circuit compares a phase of a constant reference frequency F _in with a frequency-divided signal φ _in after frequency division, and outputs a voltage V ₀ corresponding to the phase comparator with a characteristic V ₀ / φ _in = K _d . 1, a loop filter 2 having a characteristic V _in / V ₀ = F (s) (where s is a Laplace operator) in a loop shape with respect to the phase comparator 1, and a characteristic φ ₀ /
A voltage controlled oscillator (hereinafter referred to as VCO) 3 having V _in = K _v / S and a frequency divider 4 having a frequency division ratio φ ₀ / φ _in = 1 / N are connected.

In the above configuration, the phase of the reference frequency F _in and the frequency divider 4
The phase of the divided signal φ _in output from the phase comparator 1
The output voltage V ₀ is compared with the above, the high frequency component is removed by the loop filter 2, and then the output voltage V ₀ is supplied to the VCO 3 in the form of the voltage Vin. Then, VCO 3 oscillation frequency changes in response to the voltage V _in, after divided into signals phi ₀ of the oscillation frequency by the frequency divider 4 1 / N, the phase comparator in the form of a signal phi _in 1 Be fed back to.

The operation of the PLL circuit is largely different between the band of the input / output characteristic F (s) in the loop filter 2 and the band outside thereof, and operates so as to suppress all phase fluctuations within the band. This means that in-band FM modulation cannot be applied in the usual way. Out-of-band FM means FM modulation with a modulation frequency outside the band of F (s). In-band FM means FM modulation with a modulation frequency within the band of F (s).

Conventionally, a PLL for performing FM modulation using this type of PLL circuit
The frequency synthesizer circuit includes, for example, the following.

FIG. 3 is a block diagram showing a conventional PLL frequency synthesizer circuit for out-of-band FM.

In this PLL frequency synthesizer circuit, an adder 10 is provided on the output side of the loop filter 2, and the adder 10 adds the output of the loop filter 2 and the modulation signal S _in and supplies the addition result to the VCO 3. It has become. Modulation signal
The output frequency F _out of S _in and VCO 3 is expressed by the following equation.

If this equation (1) is illustrated, the characteristic diagram of the out-of-band FM as shown in FIG. 4 can be obtained. As is clear from FIG. 4, when the modulation frequency is plotted on the horizontal axis and the modulation sensitivity is plotted on the vertical axis, an FM with a constant frequency deviation of 2πK _v is obtained outside the F (s) band. By using the band where the modulation sensitivity is constant, accurate out-of-band FM can be performed.

When it is necessary to extend the modulation bandwidth to a position lower than the loop bandwidth, for example, in-band as shown in FIG.
A PLL frequency synthesizer circuit for FM has been proposed.

In this PLL frequency synthesizer circuit, in the PLL circuit of FIG. 2, the integrator 11 having the characteristic E (s) integrates the modulation signal S _in, and the output V ₁ of the integrator 11 and the output of the phase comparator ₁ are integrated. The adder 12 performs addition, and the addition result is given to the loop filter 2. Modulation signal S _in and output frequency F _out
Can be expressed as

If the Laplace operator is small enough, E (s) = A / S
(Where A is a constant), the equation (2) is approximated by the equation (3).

When the equation (3) is illustrated, the characteristic diagram of the in-band FM as shown in FIG. 6 can be obtained. As shown in FIG. 6, when the modulation frequency is plotted on the abscissa and the modulation sensitivity is plotted on the ordinate, a constant frequency shift of 2πNA / K _d is obtained within the F (s) band, so that the modulation By using the band where the sensitivity is constant, highly accurate in-band FM can be obtained.

Therefore, if the out-of-band FM of FIG. 3 and the in-band FM of FIG. 5 are combined and the modulation sensitivities of both are set to be constant, FM modulation can be performed from a low modulation frequency. A wide carrier frequency can be obtained.

(Problems to be Solved by the Invention) However, the circuit having the above configuration has the following problems.

To obtain a wide band carrier frequency, the out-of-band FM in Fig. 3
And the in-band FM shown in FIG. 5 must be combined and set so that the modulation sensitivities of both of them are constant, resulting in an increase in the number of parts, a complicated circuit, and a high cost. , And it was difficult to solve them.

SUMMARY OF THE INVENTION The present invention provides a PLL frequency synthesizer circuit which solves the problems of the prior art described above, such as the complexity of the circuit and the increase in cost due to an increase in the number of parts.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a phase comparator that compares the phases of a reference signal and a frequency-divided signal, and passes only the low-frequency component of the output of the phase comparator. A loop filter, and an adder for adding a modulation signal to the output of the loop filter,
A VCO that outputs an output signal having a frequency corresponding to the output voltage of the adder, and a frequency divider that divides the output signal of the VCO by a predetermined frequency division number and outputs the frequency division signal are provided. The following measures are taken in the PLL frequency synthesizer circuit.

That is, in the present invention, a plurality of parallel resistors are branched and connected to a fixed resistor, and a resistance division circuit for correcting a modulation signal level for changing the level of the modulation signal according to a resistance division ratio thereof, resistance driving data and the data thereof. Shift register for inputting binary code serial data having frequency division number data corresponding to, and resistance values of the plurality of parallel resistors are multiplied by 2 ⁿ based on the resistance drive data output from the shift register. A driver which is changed by (where n is a plurality) and a reference signal generator which outputs a reference signal having a frequency corresponding to the output voltage of the resistance dividing circuit and supplies the reference signal to the phase comparator are provided. Further, the frequency divider is a programmable frequency divider whose frequency division number is set by the frequency division number data output from the shift register.

(Operation) According to the present invention, since the PLL frequency synthesizer circuit is configured as described above, when serial data is input to the shift register, the shift register responds to the division ratio of the programmable frequency divider. The resistance drive data and the frequency division number data corresponding to the resistance drive data are output.
In the programmable frequency divider, the frequency division ratio is set according to the input frequency division number data. Further, the driver changes the resistance value of the resistance division circuit based on the resistance drive data, and the level of the input modulation signal changes according to the resistance division ratio of the resistance division circuit. A reference signal having a frequency corresponding to the output voltage of the resistance divider circuit is output from the reference signal generator and applied to the phase comparator. The phase comparator compares the phase of the reference signal with the phase of the divided signal output from the programmable frequency divider. The comparison result is added to the modulation signal by the adder, the oscillation frequency of the VCO is controlled by the addition result, and the output signal of the VCO is frequency-divided by the programmable frequency divider and fed back to the phase comparator.

As a result, for example, the out-of-band FM with a constant modulation sensitivity and the in-band FM whose modulation sensitivity changes according to the frequency division ratio of the programmable frequency divider are combined, and FM modulation can be performed from a low modulation frequency. In particular, the resistance drive data according to the division ratio is given to the driver, the resistance value of the resistance division circuit changes, the level of the modulation signal changes depending on the resistance division ratio, and the reference signal according to the level generates the reference signal. Since it is output from the device and given to the phase comparator, the modulation sensitivity of the in-band FM in which the modulation sensitivity changes is kept constant without requiring time to stabilize the carrier frequency. Therefore, the modulation sensitivity is within the band,
It is constant outside.

(Embodiment) FIG. 1 is a block diagram of a PLL frequency synthesizer circuit showing an embodiment of the present invention.

This PLL frequency synthesizer circuit includes a PLL circuit 20 composed of an integrated circuit and the like, and a modulation sensitivity correction circuit is connected to the PLL circuit 20.

PLL circuit 20 compares the corrected reference signal F _a and division phases of the signal S25 after the dividing, comprising a characteristic S21 / S25 = K _d of the phase comparator 21 to output a signal S21 corresponding thereto A loop filter 22 is connected to the output side of the phase comparator 21. The loop filter 22 passes only the low frequency component of the signal S21 in the form of the signal S22, and the characteristic S22 / S21 = F (s)
have. The output signal S22 of the loop filter 22 and the modulation signal S _in are connected to the adder 23, and the output signal 23 of the adder 23 is connected to the phase comparator 21 via the VCO 24 and the programmable frequency divider 25. VCO24 is an oscillator that outputs signal S24 of frequency F _out corresponding to signal S23.
23 = K _v / S. The programmable frequency divider 25 operates in synchronization with the clock signal CLK, takes in the serial frequency division number N data represented by a binary code by the strobe signal SB, and divides the signal S24 based on the frequency division number N data. The divided signal S25 is output by frequency division, and the divided signal S25 is phase-compared.
21 has a function to give.

In this embodiment, a circuit for correcting the modulation sensitivity is provided for the following reason.

In the formula (3), the modulation sensitivity of in-band FM is 2πNA / K.
_d , A and K _d are constant from the performance of the circuit, but N is the frequency division number of the programmable frequency divider 25, and the modulation sensitivity changes with this frequency division number N. In particular, when the frequency range of the carrier wave is wide, the change in the modulation sensitivity is remarkable, and it is necessary to change the level of the input modulation signal S _in .

If you want to use the modulated signal S _in from a low frequency, V
In the in-band FM _in which the modulation signal S _in is superimposed on the signal S22 input to the CO24, the loop filter 2 in the PLL circuit 20
It takes time to stabilize the carrier frequency because of the function of 2. Therefore, by the frequency of the reference signal F _a is also used in combination band FM controlled by the modulation signal S _in, a short time can stabilize the carrier frequency, it is possible to apply modulation from the modulation signal S _in the low frequencies. Therefore, a circuit for correcting the modulation sensitivity is provided.

This modulation sensitivity correction circuit has a variable gain amplifier 30 for amplifying the modulation signal S _in, and the output signal of the amplifier 30
S30 is connected to the phase comparator 32 via the resistance division circuit 31 and the reference signal generator 32 for applying in-band FM. The resistance divider circuit 31 is a circuit that changes the level of the output signal S30 of the amplifier 30 and supplies the signal S31 to the reference signal generator 32, and a fixed resistor R connected in series between the amplifier 30 and the reference signal generator 32. and _a, is composed of its fixed resistance R _a branch connected parallel resistor R _b. The parallel resistance R _b is composed of, for example, six resistances R, 2R, 4R, 8R, 16R and 32R. Here, for example, the resistor 2R has a resistance value twice that of the resistor R. The reference signal generator 32 has a function of outputting _a reference signal F _a having a frequency corresponding to the output signal S31 of the resistance division circuit 31 and supplying it to the phase comparator 21, which is more stable than the VCO 24, for example. It is composed of a good voltage controlled crystal oscillator (hereinafter referred to as VCXO). Further, a shift register 33 for data input is provided, and a driver 34 for driving a resistance division circuit is connected to the shift register 33. The shift register 33 inputs binary code serial data DA having resistance drive data and frequency division number N data in synchronization with the clock signal CLK, and causes the strobe signal SB to latch the resistance drive data in the triber 34. , And has a function of supplying the frequency division number N data to the programmable frequency divider 25. The driver 34 has a function of changing the resistance value of the resistance division circuit 31 based on the resistance drive data.

FIG. 7 is a block diagram of the serial data DA of FIG. 1, and FIG.
The figure is a block diagram of the driver of FIG.

In FIG. 7, the binary code serial data DA is composed of, for example, frequency division number N data DA1 of a plurality of bits, resistance drive data DA2 of 5 bits, and the like. The frequency division NA data DA1 and the resistance drive data DA2 are set in advance so as to correspond to each other.

In FIG. 8, the driver 34 is composed of, for example, six switches 34a to 34f, and the respective switches 34a to 34f are connected in series to the respective (resistors) R to 36R of the resistance division circuit 31. Each of the switches 34a to 34f has a function of turning on and off according to the data of each bit of the resistance drive data DA2.

The operation of the PLL frequency synthesizer circuit configured as above will be described.

First, the basic operation of this PLL frequency synthesizer circuit will be described.

In FIG. 1, when the modulation signal S _in is supplied to the adder 23, the adder 23 adds the modulation signal S _in to the output signal S22 of the loop filter 22 and supplies the output signal S23 to the VCO 24. As a result, out-of-band FM becomes possible as in the case of the conventional FIG.

On the other hand, in the case of in-band FM, from the above formula (3), F _out / F _a is proportional to the frequency division number N of the programmable frequency divider 25, and the frequency division number of the lowest channel is N _l and the frequency division of the highest channel. If the frequency is N _h , the difference between F _out / F _a is 20Log ₁₀ N _h / N _l (dB) (4). Therefore, in order to correct this level difference and keep the modulation sensitivity constant, the level of the reference signal Fa input to the phase comparator 21 is controlled by changing the resistance value of the resistance division circuit 31 for each channel. , FM in a proper band can be performed.
Here, the resistance value of the fixed resistance Ra in the resistance division circuit 31 is That is, It is obtained more and is set to that value.

Next, a concrete out-of-band FM of the PLL frequency synthesizer circuit
The operation (1) and the in-band FM operation (2) will be described.

(1) Out-of-Band FM Operation The reference signal generator 32 outputs _a reference signal Fa with _a constant frequency, which is supplied to the phase comparator 21. The reference signal F _a ,
A phase of the frequency-divided signal S25 output from the programmable frequency divider 25 is compared by the phase comparator 21, the high frequency component of the output signal S21 of the phase comparator 21 is removed by the loop filter 22, and then the signal S22. Is given to the adder 23 in the form of. The signal S22 and the modulation signal S _in are added by the adder 23,
The signal S24 of frequency F _out corresponding to the output signal S23 is VCO2
It is output from 4 and given to the programmable frequency divider 25. Programmable frequency divider 25 has a fixed frequency division N
Divide F _out and divide it by the phase comparator 21 in the form of divided signal S25.
Give feedback to. By the operation of this PLL loop, the carrier of frequency F _out that has undergone _out- of-band FM modulation is converted into VCO2.
You can send from 4.

(2) In-band FM operation When the serial data DA is supplied to the shift register 33, the shift register 33 sequentially inputs the serial data DA in synchronization with the clock signal CLK, and the frequency division number N data in FIG.
DA1 is supplied to the programmable frequency divider 25, and resistance drive data DA2 is supplied to the driver 34. By the strobe signal SB, the frequency division number N data DA1 is latched by the programmable frequency divider 25, and the resistance drive data DA2 is latched by the driver 34. Then the programmable frequency divider
25 sets the frequency division number N corresponding to the frequency division number N data.

On the other hand, the driver 34 determines the resistance R based on the resistance drive data DA2.
Set the resistance value of _b . For example, with 32 channels,
Bit 5 of the resistance drive data DA2 shown in FIG. 8 is logic "1".
In this case, the switch 34a is turned on and the resistance value of the resistor _Rb becomes R. When all the bits of the resistance drive data DA2 are "1", all the switches 34a to 34f are turned on and the resistance value of the resistance _Rb becomes (32/63) R, during which 32 resistance values change. It is possible that the resistance value changes almost linearly from R to 0.5R corresponding to the binary number from 32 to 63. That is, the driver 34 changes the resistance value of the resistance dividing circuit 31 in 32 steps with respect to the binary number from 32 to 63. The situation is shown in the following table.

When the modulation signal S _in is amplified by the amplifier 30, its output signal S in
30 is a resistance divider circuit 31 whose resistance value is set as described above.
Is adjusted to a level corresponding to the channel by the, and then applied to the reference signal generator 32 in the form of a signal S31. The reference signal generator 32 outputs _a reference signal Fa having a frequency corresponding to the signal S31 and supplies it to the phase comparator 21.

Therefore, the signal S24 output from the VCO 24 is divided by the programmable frequency divider 25 by the frequency division number set by the frequency division number N data, and the frequency division signal S25 is fed back to the phase comparator 21. Then, the phase comparator 21 compares the phase of the reference signal F _{a of the} frequency corresponding to the channel and the frequency-divided signal S25, and supplies the output signal S21 to the loop filter 22, so that the frequency subjected to the in-band FM modulation is applied. Carrier of F _out is VCO2
It will be sent from 4.

In the present embodiment, since the resistance value of the resistance division circuit 31 is changed for each channel, it is possible to correct the modulation sensitivity of the in-band FM that changes depending on the frequency division number N with good linearity. Further, since the resistance value of the resistance division circuit 31 and the division number of the programmable frequency divider 25 are set by the binary data serial data DA, the number of parts is small, the circuit configuration is simple, and the cost is low. In addition, it is possible to obtain a PLL frequency synthesizer circuit that can perform FM modulation from a low modulation frequency and that has a wide channel interval and a large number of channels and that can transmit a wide carrier frequency without requiring time to stabilize the carrier frequency. .

It should be noted that the present invention is not limited to the illustrated embodiment, the number of channels is set to a number other than 32, and the number of bits of the resistance drive data DA2 and the number of resistors R _b are modified accordingly to a number other than that shown in the drawings.
Various modifications are possible.

(Effects of the Invention) As described in detail above, according to the present invention, the shift register and the driver change the resistance value of the resistance division circuit to change the level of the modulation signal in accordance with the frequency of the resistance wave. As a result, the stabilization time of the carrier frequency is short, and in-band FM with constant modulation sensitivity can be performed accurately. Moreover, since the resistance value of the resistance division circuit is digitally changed by using the shift register and the driver,
The effects of reducing the number of parts, simplifying the circuit configuration, and reducing the cost can be expected.

[Brief description of drawings]

1 is a block diagram of a PLL frequency synthesizer circuit of the present invention, FIG. 2 is a basic block diagram of a PLL circuit, FIG. 3 is a block diagram of a conventional out-of-band FM, and FIG. 4 is a characteristic of a conventional out-of-band FM. Fig. 5 is a block diagram of a conventional in-band FM, and Fig. 6 is a conventional in-band FM
FIG. 7 is a characteristic diagram of FM, FIG. 7 is a configuration diagram of serial data in FIG. 1, and FIG. 8 is a configuration diagram of the driver in FIG. 20 …… PLL circuit, 21 …… Phase comparator, 22 …… Loop filter, 23 …… Adder, 24 …… VCO, 25 …… Programmable frequency divider, 31 …… Resistance divider circuit, R _a … Fixed Resistance, R _b …
… Parallel resistance, 32 …… Reference signal generator, 33 …… Shift register, 43 …… Driver.

Claims (1)

[Claims] 1. A phase comparator that compares the phases of a reference signal and a frequency-divided signal, a loop filter that passes only the low frequency component of the output of the phase comparator, and an addition that adds a modulation signal to the output of the loop filter. And a voltage-controlled oscillator that outputs an output signal having a frequency corresponding to the output voltage of the adder, and a component that divides the output signal of the voltage-controlled oscillator by a predetermined frequency division number and outputs the divided signal. In a PLL frequency synthesizer circuit equipped with a frequency divider, a plurality of parallel resistors are branched and connected to a fixed resistor, and a resistance division circuit for correcting the modulation signal level that changes the level of the modulation signal according to the resistance division ratio thereof is used. A shift register for inputting binary code serial data having resistance drive data and frequency division number data corresponding to the resistance drive data; and the resistor output from the shift register. Based on the dynamic data, 2 ⁿ times the resistance value of said plurality of parallel resistors (where, n is a plural number) and drivers vary, and outputs a reference signal having a frequency corresponding to the output voltage of the resistive divider circuit wherein A reference signal generator for supplying to a phase comparator is provided, and the frequency divider is a programmable frequency divider in which a frequency division number is set by the frequency division number data output from the shift register. A characteristic PLL frequency synthesizer circuit.