JPH07112180B2 - Line fault information transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A time-division multiplexer A in which a time-division multiplexer B connected to a digital line B is cascade-connected to another digital line A.
When data is received via the TD, and is transferred to the time division multiplexer B, the line failure information is transferred from the time division multiplexer A to the time division multiplexer B when a line failure occurs on the digital line A. However, in order to enable the time division multiplexer B to perform normal data transmission via the digital line B without being affected by the line failure, the time division multiplexer A has no connection to the digital line A. The transmission line interface means 4 and the terminal interface 5 on the output side, to which the time division multiplexer B is cascade-connected to the next stage, are provided, and the transmission line interface means 4 of the time division multiplexer A is the data from the digital line A. Is received, a clock is extracted from the data, an internal clock is generated based on the received clock, the internal device is controlled by the internal clock, and it is sent to the time division multiplexer B. The internal clock is sent to the terminal interface 5 together with the data, the terminal interface 5 sends the internal clock together with the data to the time division multiplexer B, and when the digital line fails, the transmission line interface means 4 detects the failure and the data. In the configuration in which the extraction of the clock from the clock is stopped and the free-running clock is generated, the transmission line interface means 4 has a function of sending the line fault information indicating the fault of the digital line A to the terminal interface 5 and the terminal interface 5. Is provided with a line failure information transfer means, and when the transmission line interface means 4 sends the line failure information to the terminal interface 5 when the digital line A fails, the terminal interface replaces the clock which has been sent up to that time, and the line failure information is transferred. Insert information or leave it unclocked When the data is transferred to the time-division multiplexer B connected in cascade and the line interface information 6 of the time-division multiplexer B detects the line failure information, the clock selection circuit in the line interface 6 has the time-division multiplexer A until then. The selection of the clock sent from the device is stopped, the clock extracted from the data received from the other digital line B is selected, the internal clock is generated based on the selected clock, and the control in the own device is performed by the clock. To do.

[Industrial application field]

In the present invention, when a time-division multiplexer A, which is a cascade connection of time-division multiplexers B connected to a digital line B, is transmitting data through the digital line A, the line is connected when a failure occurs in the digital line A. The present invention relates to a line failure information transfer method for transferring failure information from the time division multiplexer A to the time division multiplexer B.

In recent years, for example, computer-to-computer communication, high-speed data transmission, image transmission, telephone-based transmission, and composite transmission of these tend to be widely performed by using a digital line having a transmission speed of 64,192,384,768,1536,6144 Kb / s, for example. .

Here, since the high-speed channel of the above digital line can be divided and used for the low-speed channel, for example, 6144
1536 Kb / s using a digital line of Kb / s x 1 channel
It can transmit data of × 3 channels and 384 Kb / s × 4 channels.

FIG. 5 shows an explanatory diagram of a system example to which the present invention is applied.

As shown in the figure, the terminal interface of the time division multiplexer A
The LS is connected not only to a CPU, a telephone set, a PBX to which a FAX is connected, etc., but also a time division multiplexer B is cascade-connected as shown in FIG.
The digital line B is also connected via -B.

Also, the input side interface NP of the time division multiplexer A is DSU.
-A, digital line A, and DSU-C are connected to the time division multiplexer C, and data transmission is performed between the time division multiplexer A and the time division multiplexer C.

Here, when a line failure occurs in the digital line A,
It is necessary for the time division multiplexer B to be able to continue normal data transmission through the digital line B without being affected by this line failure.

[Conventional technology]

FIG. 6 shows a conventional block diagram. The operation of the figure will be described below. The time division multiplexer B is cascade-connected to the time division multiplexer A, and the time division multiplexer B has n input side interfaces (hereinafter abbreviated as NP) 33-1 to 33-1. 33-n is mounted and connected to the corresponding digital line B etc.,
It is assumed that the time division multiplexer A is equipped with one NP13 and is connected to the digital line A.

First, the function of each part is as follows.

The line terminators 12 and 32 terminate the digital lines A and B and form a digital interface of the time division multiplexer, and the NPs 13-33-1 to 33-n form an input side interface with the line and input. The clocks are extracted from the data to be transmitted, the line fault is detected, and the line fault information is transferred, and the multiplexers 14 and 34 separate / multiplex the data from the NP and the terminal interface 2.

Further, the phase synchronization units 15 and 35 generate a master clock as an internal clock used by the time division multiplexer, and the clock selection circuit 37 selects one of the clocks extracted by the NP receiving the data at that time.

Next, the NP 13 in the time division multiplexer A extracts a clock from the data input via the digital line A and the line terminator 12 and transfers it to the phase synchronizer 15 and transfers this data to the multiplexer 14. To do.

Therefore, the phase synchronization unit 15 generates a master clock in synchronization with the input clock, operates each unit in the time division multiplexing apparatus A with this master clock, and performs time division multiplexing via the terminal interface 2 and NP33-n. It is added to the clock selection circuit 37 in the device B. Here, each NP33-1 to 33-
The clock extracted from the digital line B or the like corresponding to (n-1) is also added.

Here, when the clock selection circuit 37 selects the clock from the time division multiplexer A, the selected time division multiplexer A
Similarly, each section of the time division multiplexer B operates with the master clock generated in the phase synchronizing section 35.

That is, each part of the time division multiplexer A and the time division multiplexer B operates in synchronization with the clock of the digital line A. Here, it is assumed that all digital circuits are network-synchronized.

On the other hand, the input data is demultiplexed by the multiplexing unit 14 and then added to the NP33-n in the time division multiplexer B via the bus 16, the bus interface 21 in the terminal interface 2, and the output interface 22. To be Therefore, NP33-1 ~
The data from 33-n is processed by the multiplexer 34 in the same manner as above, and is transferred via the bus 36 and the terminal interface (not shown).

[Problems to be solved by the invention]

When the NP13 of the time division multiplexer A detects the line failure of the digital line A, the above clock extraction is stopped, so that the phase synchronization unit is free-running, and this free-running clock is the terminal interface 2 and the time division multiplexer B. NP33-n in FIG.

Therefore, the clock of the time division multiplexer B becomes asynchronous with the digital line B, a malfunction occurs due to a clock slip in the NP33-1, and normal data transmission via the digital line B cannot be performed. is there.

[Means for solving problems]

According to the present invention, the above problems are caused by the transmission line interface means 4 on the connection side of the digital line A and the time division multiplexing device B in the time division multiplexing device A as shown in the principle diagram of FIG. 1 and FIG. Is equipped with a terminal interface 5 on the output side connected in cascade to the next stage, and the transmission path interface means 4 of the time division multiplexer A receives the data from the digital line A, extracts the clock from the data, and An internal clock is generated based on the internal clock, the internal device is controlled by the internal clock, and the internal clock is sent to the terminal interface 5 together with the data for sending to the time division multiplexer B. The terminal interface 5 sends the internal clock together with the data to the time. When the signal is sent to the division multiplexer B, and when there is a failure in the digital line, the transmission line interface means 4 detects the failure, In the configuration in which the extraction of these clocks is stopped and a free-running clock is generated, the transmission line interface means 4 has a function of sending the line fault information indicating the fault of the digital line A to the terminal interface 5, and the terminal interface 5 Is provided with a line failure information transfer means, and when the transmission line interface means 4 sends the line failure information to the terminal interface 5 when the digital line A fails, the terminal interface replaces the clock which has been sent up to that time, and the line failure information is transferred. Information is inserted or transferred in a clockless state to the cascaded time division multiplexer B, and when the transmission line interface means 6 of the time division multiplexer B detects line failure information, the transmission line interface 6 The clock selection circuit in the inside selects the clock sent from the time division multiplexer A until then. Stop, the clock extracted from the data received from the other digital line B is selected, an internal clock is generated based on the selected clock, and the own device is controlled by the clock. It is solved by the information transfer method.

[Action]

According to the present invention, when the transmission line interface means 4 detects a line fault, it stops the clock extraction from the data input via the digital line A and transfers the line fault information to the terminal interface 5.

Therefore, the line-fault information transfer means 53 in the terminal interface 5 inserts the line-fault information in place of the clock that has been sent up to that time and transfers it to the transmission-line interface means 6 of the time-division multiplexer B. Instead of the clock that has been sent, no clock is used, and the transfer of the clock to the transmission line interface means 6 is cut off, whereby the information on the line fault is transferred to the time division multiplexer B.

Therefore, in the clock selection circuit of the time division multiplexer B, instead of the clock from the time division multiplexer A which has been used so far, another clock is switched to the clock extracted from the data received from the digital line B, for example. Since the internal clock is generated and the clock synchronization is ensured by controlling the own device by this clock, normal data communication from the digital line B can be continuously maintained.

〔Example〕

2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of the line fault information transfer circuit in FIG. 2, and FIG.
The operation explanatory drawing of a figure is shown. The reference numeral on the left side of FIG.
The waveforms of the portions having the same reference numerals in the drawings and FIG. 3 are shown. Also, the same reference numerals denote the same objects throughout the drawings.

Here, the transmission line interface means 4 is a line terminating device 4
2, the NP43, the multiplexing unit 44, the phase synchronization unit 45 and the bus 46, the terminal interface 5 is composed of the bus interface 51, the line fault information transmission means 53 and the output side interface 52, the line fault information transfer means 53 Signal separation circuit 531, line fault information transfer circuit 532 and timing pulse generator 533
Shall consist of

Hereinafter, as in the conventional example, the time division multiplexer B is cascade-connected to the time division multiplexer A, and the device B is n NPs (63-1 to 63-1).
63-n), and the device A is equipped with one NP43, the operation of FIG. 2 will be described with reference to FIGS.

First, the NP 43 of the time division multiplexer A in FIG. 2 extracts a clock from the data input via the digital line A and the line terminating device 42 and adds it to the phase synchronizer 45. Therefore, the phase synchronization unit generates a master clock as an internal clock synchronized with this clock and transfers it to each unit of the time division multiplexer A.

On the other hand, in the time division multiplexer B, (n-1) NPs 63-1 to 63- (n-1) out of the n NPs mounted are clocked from data input from the corresponding digital line B or the like. Extract.

Then, these clocks and the clock transferred from the time division multiplexer A via the terminal interface 5 and NP63-n are added to the clock selection circuit 67, where one clock is selected from the n clocks. Each part of the time division multiplexer B is operating with the master clock as an internal clock that is selected and synchronized with the clock selected as described above.

Here, when the selected clock is the clock transferred via the terminal interface 5 of the time division multiplexer A connected in cascade, the NP43 in the time division multiplexer A causes the line failure of the digital line A. When detected, the line fault information is sent from here to the terminal interface 5 by intra-device transfer.

In the terminal interface 5, in addition to the signal separation circuit 531 via the bus interface 51, it is separated into data and line fault information here, and sent to the line fault information transfer circuit 532.

When the line fault transfer circuit is configured as shown in FIG. 3 (a), the line fault information is multiplexed with the data and sent to the time division multiplexer B as shown in FIG. 4 (a). That is, in FIG. 3 (a)
The AND gates 5322 and 5324 are added with the data and line fault information shown in FIG.

The timing pulse shown in FIG. 4 (a)-is applied to this AND gate, but when one is turned on by the inverter 5323, the other is turned off. Therefore, as shown in FIG. 4 (a)-from the OR gate 5321. 6 is the NPn in the time division multiplexer B from the output interface 52.
Forwarded to 3-n.

On the other hand, in the case of the circuit configuration shown in FIG. 3 (b), the data is sent as it is to the output side interface 52 as shown in FIG.
Since it is added to the AND gate 5326 at 5325, the master clock from the phase synchronization unit 45 is sent to the output side interface 52 when there is no line failure information, but this master clock is not sent when there is line failure information ( Fig. 4 (b)-
,reference).

Therefore, the NPn in the time division multiplexer B detects the line failure information in the case of FIG. 3 (a), and detects the clock interruption in the case of FIG. The clock is switched to the clock, and each unit operates in synchronization with the switched clock.

That is, when a failure occurs in the digital line A connected to the time division multiplexer A, the line failure occurs in the time division multiplexer B which is cascade-connected to the time division multiplexer A and is connected to another digital line B. Information is transferred.

As a result, the time division multiplexer B switches to the clock extracted from the data from the digital line B, generates a new internal clock, and controls its own device, so that clock synchronization is ensured and, for example, the digital line B is normally operated. Data transmission becomes possible.

〔The invention's effect〕

As described in detail above, according to the present invention, when a failure occurs in the digital line A controlled by the time division multiplexer A, it is cascade-connected to the time division multiplexer A and connected to another digital line B. The information on the line failure is transferred to the time division multiplexer B which is operating.

Therefore, there is an effect that the time division multiplexing apparatus B switches to another clock extracted from the data from the digital line B, for example, and normal data transmission with the digital line B becomes possible.

[Brief description of drawings]

1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of the line fault information transfer circuit in FIG. 2, and FIG. 4 is of FIG. Operation explanatory diagram, FIG. 5 is an explanatory diagram of a system example to which the present invention is applied, and FIG. 6 is a block diagram of a conventional example. In the figure, 4 and 6 are transmission line interface means, 5 is a terminal interface, and 53 is a line fault information transfer means.

Front page continued (72) Inventor Takao Matsuda 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References JP-A-54-18209 (JP, A) JP-A-61-245728 (JP) , A) JP-A-57-112149 (JP, A)

Claims (1)

[Claims] 1. A time-division multiplexer A is provided with a transmission line interface means 4 on the connection side of a digital line A, and a terminal interface 5 on the output side to which the time-division multiplexer B is cascade-connected to the next stage. The transmission line interface means 4 of the time division multiplexer A receives the data from the digital line A, extracts a clock from the data, generates an internal clock based on the data, and controls its own device by the internal clock. In addition, the internal clock is sent together with the data to the terminal interface 5 for sending to the time division multiplexer B, the terminal interface 5 sends the internal clock together with the data to the time division multiplexer B, and when the digital line fails, it is transmitted. The path interface means 4 detects a failure, stops extracting the clock from the data, and generates a free-running clock. In the configuration, the transmission line interface means 4 has a function of sending the line fault information indicating the fault of the digital line A to the terminal interface 5, and the terminal interface 5 is provided with the line fault information transfer means. When the digital line A has a fault, the line fault information is sent to the terminal interface 5, and the terminal interface inserts the line fault information in place of the clock that has been sent up to that time, or puts it in a non-clock state, When the data is transferred to the time-division multiplexer B connected in cascade and the line interface information 6 of the time-division multiplexer B detects the line failure information, the clock selection circuit in the line interface 6 has the time-division multiplexer A until then. Data received from another digital line B after stopping the selection of the clock sent from A line failure information transfer method characterized in that a clock extracted from the inside is selected, an internal clock is generated based on the selected clock, and the internal control is performed by the clock.