JPH07112185B2 - PLL time constant switching circuit - Google Patents

Description

Detailed Description of the Invention

INDUSTRIAL APPLICABILITY The present invention relates to a PCM that is transmitted with a signal absence period, for example.
The present invention relates to a time constant switching circuit suitable for use in a PLL for extracting a clock signal from a signal. [Summary of the Invention] The present invention relates to a time constant switching circuit of a PLL, and a time constant circuit
By connecting a capacitor in parallel through the source-drain resistance of ET and controlling the gate voltage of the FET according to the lack of a signal, the adverse effect on the PLL at the time of switching is eliminated. [Prior Art] In a so-called SMPTE-C type video tape recorder, two heads are provided on a rotating drum, and this drum is rotated at a rate of one rotation per one field, and at the same time, the circumference of the drum is rotated. The magnetic tape is wound diagonally over nearly 360 degrees of the surface and transported at a predetermined speed. The video period of the video signal is recorded in one of the two heads described above, and the signal is recorded in the other head during the period (synchronization period) in which the head is separated from the magnetic tape. Has been done. That is, FIG. 3 shows a recording pattern of the magnetic tape thus recorded. In the figure, the magnetic tape is divided into two in the width direction, a signal in the video period is recorded on an oblique track by the above-mentioned one head in the divided wide portion, and the other in the divided narrow portion. The signal of the synchronization period is recorded on the diagonal track by the head. A control track, a first audio track, a second audio track, and a third audio signal track, which are recorded by a fixed head, are provided between these parts and on both side edges of the magnetic tape. By the way, in such a format, if a so-called time base collector is used for the reproduction signal, even if the signal in the synchronization period is lost, a regular video signal can be reproduced without trouble as long as the signal in the video period is obtained. . Therefore, it has been considered to record a digitized PCM audio signal in the above-mentioned format instead of the signal in the synchronization period on an oblique track in a narrow portion. That is, in the above-mentioned conventional format, the audio signal is analog-recorded by the fixed head, but in such analog recording, the deterioration is remarkable especially when the dubbing is repeated. On the other hand, if the recording is performed digitally, the problem of deterioration during dubbing can be solved. The applicant of the present application has previously proposed a video tape recorder (Japanese Patent Application No. 60-180257) in consideration of such a point. That is, FIG. 4 is a block diagram of a PCM signal system for that purpose. In this block diagram, the analog audio signal supplied to the input terminal (41) is supplied to the AD conversion circuit (43) through the IO circuit (42). And converted into digital data. This data is supplied to the data bus (44). The data on the data bus (44) is supplied to and stored in the memory (45). Further, the data stored in the memory (45) is supplied to the encoder (47) through the data bus (46), and encoding such as addition of a predetermined error correction code and rearrangement is performed. Then, the data from the memory (45) is transferred to the modulation circuit (4
8) is supplied to the recording head (50) through the recording amplifier (49) and is modulated by the data to be supplied to the recording head (50), and the diagonal portion of the narrow portion of the magnetic tape (51) corresponding to the above-mentioned synchronous track is supplied. Recorded on the track. During playback, the tape (51) to the playback head (52)
The signal reproduced in (4) is supplied to the demodulation circuit (54) through the reproduction amplifier (53), and the recorded digital data is demodulated. This demodulated data is the data bus (55) (56)
The data of the data buses (55) and (56) are supplied to the memory (45) and to the first and second decoders (57) and (58), respectively. The demodulator circuit (5
The address of the data detected in 4) is the address bus (5
It is supplied to the memory (45) through 9). Then, the data that has been subjected to predetermined rearrangement and decoding such as error correction is supplied from the memory (45) to the data bus (44). The data of the data bus (44) is supplied to the DA conversion circuit (60) to be an analog audio signal, and this signal is taken out to the output terminal (61) through the IO circuit (42). The signal from the digital signal input terminal (62) is supplied to the data bus (44) through the digital IO circuit (63), and the signal from the data bus (44) is output as a digital signal through the IO circuit (63). Taken out to the terminal (64). Further, during editing, data from another video tape recorder or the like is supplied to the editing control circuit (66) through the terminal (65), and the data from this circuit (66) is transferred to the data bus (44).
The control signal detected by the circuit (66) is also supplied to the memory (45) through the auxiliary bus (67). Further, FIG. 5 shows a time chart of the recording / reproducing operation of this apparatus. Vertical lines in the figure are field boundaries. In this figure, first, A is a recording operation,

The signal AD-converted in the period of [0] is encoded in the first half of the next field [1], time-axis-compressed and read in the latter half of this field [1], and the recording heads (50A) (50B) are read. Will be recorded at. The recording is divided into two tracks. On the other hand, B is a reproducing operation, and for example, the signals reproduced by the reproducing heads (52A) and (52B) in the first half of the field [-2] are from the second half of the field [-2] to the next field. Decoded in the first half of [-1], and then the next field

The time axis is expanded during the period [0], DA converted, and taken out. Therefore, in the device described above, the same field

The reproducing heads (52A) and (52B) are provided three or more fields ahead of the recording heads (50A) and (50B) in order to extract the audio signal at [0]. That is, FIG. 6 shows the rotary drum as viewed from above. In the figure, (71A) and (71B) are recording heads for audio signals, and (72A)
(A) and (72B) are playback heads for checking the recording of audio signals, and (73B)
A) (73B) are audio signal reproducing heads, and (74A) (74B) are audio signal reproducing heads for variable speed reproduction of video signals. Furthermore, (81) is a recording / playback head for video signals, and (82)
Is a variable speed reproducing head for video signals, and (83) is an erasing head for video signals. Here, there are a total of eight recording / reproducing heads for audio signals, and three recording / reproducing heads for video signals. Providing a total of eleven heads in a balanced manner is especially important for recording / reproducing for video signals. The arrangement of the head (81) and the variable speed reproducing head (82) is 120 according to the standard of SMPTE-C type format, for example.
It is not possible if it is set in every degree. Therefore, as shown in the figure, the dummy head (9
0) is provided, and a total of 12 heads are arranged at an angle of 30 degrees. That is, in the figure, the recording heads (71A) (71B), the erasing head (83), the recording / reproducing head (81), the dummy head (90), the reproducing heads (72A) (72B) are rotated counterclockwise from the position at 3 o'clock in the figure. ), Playhead (82), playhead (73
A) (74A) (73B) (74B) are arranged in this order. The heads (72A) and (72B) are set so as to trace the same track recorded by the heads (71A) and (71B).
(71B) is provided with a step that follows the track by 1/3 track, and the heads (73A) and (73B) are
There is a step ahead of B) by 3 1/3 tracks,
The heads (74A) and (74B) are provided with a step that follows the heads (73A) and (73B) by 1/3 track. As a result, appropriate tracking is performed for each recording track, and recording of audio signals with consideration of time delay for a predetermined field is also performed for video signals recorded and reproduced by the heads (81) (82). Playback is performed. By the way, in the above-mentioned device, the PCM signal to be recorded and reproduced is intermittently transmitted in a burst form as shown in the above-mentioned time chart. On the other hand, in processing the PCM signal, a so-called PLL is used to reproduce the clock signal in the signal and perform the processing. In that case, in order to satisfactorily lock the PLL to the signal transmitted intermittently as described above, it is necessary to shorten the so-called PLL pull-in time constant. However, if the time constant of the PLL is simply shortened, the lock will be easily released when a dropout occurs in the PCM signal this time, which is unfavorable because the dropout is affected. Therefore, it has been conventionally proposed to provide two types of PLL time constants, long and short, to shorten the time constant during the signal blank period and to lengthen it during the PCM signal period. However, conventionally, it has been found that when the above-mentioned time constant is instantaneously switched using a switch, the PLL may be impacted at the time of switching and the retracted lock may be released. [Problems to be Solved by the Invention] As described above, the conventional technology has a problem in that the time constant of the PLL is instantaneously switched, so that the PLL is impacted and the lock is released. . [Means for Solving Problems] The present invention relates to a PLL (3) for reproducing a clock signal from an input data signal, a detection circuit (5) for detecting a blank period of the input data signal, and the PLL. Connected to the
A time constant circuit having a value of a first time constant and including a first capacitor (8) and a source-drain resistance of a FET (6) in parallel with the first capacitor of the time constant circuit. A second capacitor (7) connected to the output of the detection circuit to the gate of the FET to turn on the FET and short circuit the first capacitor
A time constant switching circuit for a PLL, wherein a pull-in time constant of L is controlled to a value larger than the first value. [Operation] According to this, since a capacitor is provided in series with the switching FET, the time constant at the time of switching is changed by controlling the gate voltage of the FET with a signal according to the signal lack of the detection circuit output. Can be made smoother and will not impact the PLL. [Embodiment] In FIG. 1, the PCM signal supplied to the input terminal (1) is supplied to the PCM signal processing circuit (2) and the PLL.
The clock signal supplied to (3) and reproduced by the PLL (3) is supplied to the processing circuit (2), and the processed signal is taken out to the output terminal (4). Further, the PCM signal from the input terminal (1) is supplied to the detection circuit (5) in the blank period, the period in which the PCM signal is missing is detected, and this detection signal is supplied to the gate of the FET (6). . And this F
The source of ET (6) is grounded, the drain is grounded through capacitors (7) and (8), and this capacitor (7)
The midpoint of the connection of (8) is grounded through a series circuit of the resistor (9) and the parallel circuit of the capacitor (10) and the resistor (11), and the middle point of connection of the resistor (9) and the parallel circuit. The point is connected to the PLL (3). The numbers in the figure indicate the values of each element. Therefore, in this circuit, when the FET (6) is off, the time constant circuit consisting of the resistors (9) (11) and the capacitors (8) (10) is connected to the PLL (3), and a relatively short pull-in time occurs. When it is a constant and FET (6) turns on,
The capacitor (7) is connected in parallel to the capacitor (8) via the source / drain resistance of the FET (6), and the time constants are approximately resistors (9) (11) and capacitor (7).
It becomes the value determined by (10), and the pull-in time constant is FE.
It is made longer than in the off period of T (6). FET (6)
Is controlled by the blank period detection circuit (5). The blank period detection circuit (5), which is not shown, is triggered by an input PCM signal and outputs a pulse signal having a pulse width corresponding to the lack period of the PCM signal, and this retrigger It is composed of an integrating circuit that outputs the integrated signal of the output of the Bull Mono Multi as a detection signal. Therefore, if the input PCM signal is lacking, the FET
Since the gate of (6) is controlled so that the level thereof is gradually changed by the detection signal, the time constant is changed relatively gently and the time constant is smoothly switched. That is, in FIG. 2, when there is an input PCM signal like A, the detection signal of the blank period detection circuit (5) is as shown in FIG. B, and this signal is the FET (6).
Is supplied to the gate of and the time constant is changed as shown in FIG. As a result, the PLL (3) has a long pull-in time constant during the PCM signal period, and will not be unlocked even if there is a dropout as shown in a in the figure. The constant is shortened and the next PCM
The pull-in is performed immediately when the signal arrives, and the time constants are smoothly switched between them. In this way, the time constant of the PLL is switched,
According to the circuit described above, switching is performed smoothly, so there is no risk of the lock being disengaged or other adverse effects on the PLL due to shock during switching. [Effect of the Invention] According to the present invention, a capacitor is provided in parallel in the time constant circuit of the PLL via the resistance between the source and drain of the FET so that the gate voltage of the FET gradually changes according to the lack of a signal. Since the change of the time constant at the time of switching the time constant is controlled by the control, it is possible to eliminate the adverse effects such as the lock loss of the PLL at the time of switching the time constant.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 to 6 are diagrams for explaining a conventional technique. (1) is an input terminal, (2) is a signal processing circuit, (3) is a PL
L, (4) is an output terminal, (5) is a blank period detection circuit, (6) is a FET, (7), (8) and (10) are capacitors,
(9) and (11) are resistors.

Claims (1)

[Claims] 1. A PLL for recovering a clock signal from an input data signal, a detection circuit for detecting a blank period of the input data signal, and a first time constant value connected to the PLL. A time constant circuit including one capacitor, and a second capacitor connected in parallel to the first capacitor of the time constant circuit via a source-drain resistance of the FET, and the output of the detection circuit is Supply it to the gate of the FET and
A time constant switching circuit for a PLL, wherein the pull-in time constant of the PLL is controlled to a value larger than the first value by turning on ET and short-circuiting the first capacitor.