JPH07112207B2 - Bus interface circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface circuit used when transmitting / receiving data between systems or between LSIs by a serial data bus.

2. Description of the Related Art In recent years, digital data has been increasingly transmitted and received between systems and between LSIs with the digitization of circuits of consumer devices. For example, even in a television receiver, each data such as brightness, volume, and correction of deflection distortion is
The usage is to send each function from the computer to the corresponding LSI. At this time, if each data is transmitted in parallel, for example, 8-bit data is transmitted through 8 lines,
There is an increase in the number of I pins and the number of wires between LSIs,
Not preferable. Therefore, a method of serially transmitting and receiving data with a few lines is used.

As a prior document using a serial data bus for a television receiver, there is "Broadcasting Technology 1985 VOL.38 No.2p.p.94-96 Kenrokukan Publishing".

Hereinafter, an example of the conventional bus interface circuit described above will be described with reference to the drawings. FIG. 3 is a block diagram for explaining the bus system. In FIG. 3, reference numerals 31 and 32 are microcomputers, 33 and 34 are LSIs, and 35 and 36 are ICs. The elements are connected by two serial buses to transmit and receive digital data.
The bus interface circuit must be included in each of these elements. The bus interface circuit on the data receiving side is taken up here.

FIG. 4 is an example of a bus signal waveform when digital data is transmitted by two lines. In the example of transmitting data by the waveform a and the waveform b, as data, the address for each element is A _{4 to} A ₁ , the address inside the element is S _{4 to} S ₁ , and the address inside the element is D _{4 to} D ₁ . Indicates the data to be stored in. When (A ₄ , A ₃ , A ₂ , A ₁ ) = (1010), the LSI (B) 34 in FIG. 3 is targeted, and (S ₄ , S ₃ , S ₂ , S ₁₎ = (0101) the address of the data (D _{4,
D 3, D 2, D 1} ) = become so on is changed to (1100). In order to send and receive these information with a few lines, it is necessary to give meaning to the "1" and "0" levels of each bus signal, the rising edge, and the falling edge.

In FIG. 4, when the waveform b is “1” at the time of the rising edge or the falling edge of the waveform a, the signal indicates the end of transmission or the start of transmission, and the address and data are the waveform a at the time of the rising edge of the waveform b. "1" and "0" levels. That is, the transmission start signal is set at time Q in the figure, and the transmission end signal is set at time U, during which the rising edge of the waveform b, for example, S ₄ at time S is determined. Between the transmission start time Q and the transmission end time U, the rising edge and the falling edge of the waveform a are always when the waveform B is "0" as at times R and T.

FIG. 5 shows a block diagram of a conventional bus interfence circuit for receiving such a bus signal input. In the figure, 1 and 2 are bus signal input terminals, 3 is an output terminal for received data, 4 is a transmission end detection output terminal, 5 is a transmission start detection output terminal, and 6 to 8 are D flip-flops (hereinafter referred to as DFF). Abbreviated), 9 and 10 are inverters, and 50 and 5
1 is a coil and 52 and 53 are capacitors.

The operation will be described below with reference to the waveforms in FIG. The waveform c is an example of the waveform of the output signal of the transmission start detection output terminal 5, and is the output of DFF8. D • FF8 is the rising edge of the waveform a signal inverted by the inverter 10.
The signal of the waveform b is input to the data input to the clock input of the trigger, and the signal obtained by inverting the signal of the waveform b by the inverter 9 is input to the reset input (“0” to output “0”). Therefore, at time Q, the waveform b is captured at the falling edge of the waveform a and the waveform c becomes “1”. At time V, the waveform b becomes “0”, so that the waveform c is reset and the waveform c becomes “0”. "0" continues until the next transmission starts.

The waveform d is an example of the waveform of the output signal of the transmission end detection output terminal 4, which is the output of DFF7. In D · FF7, the signal of waveform a is for clock input, the signal of waveform b is for data input, and the waveform b
A signal obtained by inverting the signal of 1 by the inverter 10 is input to each reset input. Therefore, at time U, the waveform a
The waveform b is captured at the rising edge of and the output waveform d of D · FF4 becomes “1”. Considering that the transmission like the waveforms a and b is repeated, the waveform d is “1” during the period of no transmission, and when the waveform b becomes “0” at time V, the D / FF7 is reset. The waveform d becomes "0". After that, “0” continues until time U.

The waveform e is the waveform of the output signal of the data output terminal 3, and D · FF
The output of 6. The signal of waveform b is input to the clock input of D · FF6, and the signal of waveform a is input to the data input thereof. Therefore, the output of DFF6 latches A4 at time S, thereafter fetches up to D1 in order, and ends at "0" at time X.

As described above, the waveforms c, d and e are synthesized from the waveforms a and b. Convert the serial data of waveforms c, d, and e to the desired parallel
Easy to convert to data. Converts four data each after waveform a becomes "1" to parallel data, confirms the address of each element by the first four data, and confirms the address in the element by the next four data Then, the following four data are captured at the rising edge of the waveform d.

SUMMARY OF THE INVENTION However, the bus interface circuit having the above-mentioned configuration has a drawback that it is weak against external noise.

For example, in the case of a television receiver, a high voltage of about 30 KV is applied to the anode of the cathode ray tube, and a strong noise is generated due to the discharge, which disturbs the bus signal due to power supply, ground, and induction. When noise is superposed on the waveforms a and b in FIG. 4, the edges of the waveforms are used for operation, leading to malfunction. If the waveform a is noisy, the transmission start or end is not detected properly, and if the waveform b is noisy, the number of data does not match and the address is erroneous.

In the circuit shown in FIG. 5, the coil 50, 5 is also used as a countermeasure.
A low-pass filter consisting of 1 and capacitors 52 and 53 is inserted between the bus signal input terminals 1 and 2 and D flip-flops 6, 7 and 8, but the original waveforms a and b may be out of timing. However, it was difficult to take measures because the time constant was not chosen enough to remove noise.

In view of the above problems, it is an object of the present invention to provide a bus interface circuit that can reduce malfunctions due to external noise.

Means for Solving the Problems In order to solve the above problems, the bus interface circuit of the present invention further includes a digital low-pass filter connected to a bus signal input terminal, and a switch bypassing the digital low-pass filter. , A circuit for compressing the pulse width of the digital low-pass filter output on the clock bus signal side.

Effect The present invention has the above-described configuration to remove the external noise by the digital low-pass filter, and to obtain a sufficient noise removal characteristic by the simple digital low-pass filter by inserting the signal compression circuit on the clock bus signal side. You can

Also, if you want to rewrite the data inside the LSI at high speed during LSI testing, the test time will be long if you have this digital low-pass filter. Therefore, by providing a switch that bypasses this, it is easy to make this configuration LSI. became.

Embodiment Hereinafter, a bus interface circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a bus interface circuit according to an embodiment of the present invention.

In FIG. 1, 1 is a data bus signal input terminal, 2 is a clock bus signal input terminal, 3 is a received data output terminal, 4 is a transmission end detection signal output terminal, and 5 is a transmission start detection signal. Output terminals, 6 to 8 are DFFs, 9 and 10 are inverters, and the above correspond to the same numbers in FIG. 5 of the conventional example.

12 and 13 are digital low pass filters, 14 are digital
It is an input terminal for a clock that drives a low-pass filter. 15 to 22 constitute an internal circuit of the digital low-pass filter, 15 to 17 are D / FF, and 19 to 21 are 2-input AN.
D gate, 22 is a 3-input OR gate, 23 and 24 are 2-input 1-output switches bypassing the digital low-pass filters 12 and 13, 2
5 is a switch control input terminal for the switches 23 and 24, 26 to 28 are DF
F and 29 are 2-input AND gates.

The operation of the bus interface circuit configured as described above will be described below with reference to the waveform diagrams of FIGS. 2 and 4.

First, the signal of the waveform a shown in FIG. 4 is input to the input terminal 1 of the data bus signal, and the signal of the waveform b is input to the clock bus signal input terminal 2. The waveform f in FIG. 2 is enlarged from the time points R to T of the waveform b. A waveform g is a waveform example when noise is superimposed on the waveform f, and is a waveform example when a malfunction occurs in the conventional example. Waveform h is an example of the waveform of clock input terminal 14, and it is a digital low pass filter.
It is supplied to the clock input of each D and FF of 12,13. The waveform i is an example of the output waveform of the DFF15, and the waveform g is sampled at the rising edge of the waveform h. Waveform j, k
Is an example of the output waveform of DFF16,17.
The clocks are sequentially time-shifted. These 3
AND gates 19 to 21 take two different products of D / FF 15 to 17, and OR gate 2 takes the sum of AND gates 19 to 21.
Is 2. The output waveform of the OR gate 22 is the waveform l, and the waveforms i, j, k
Majority decision, that is, "1" for two or more "1", "0" for two or more
If so, "0" is output. This waveform 1 is the output of the digital low pass filter 13. It can be seen that the original bus signal waveform f is reproduced from the waveform g on which the external noise is superimposed.

The same circuit applies to the digital low-pass filter 12 on the data bus signal input terminal 1. The amount of noise that can be removed is related to the clock frequency at clock input terminal 14. If the waveform h is selected to have a high frequency such that sampling is performed twice or more during the noise period, noise cannot be removed. Therefore, the frequency of the clock input terminal 14 should be kept as low as several times the frequency of the clock bus signal input terminal 2. However, if it is selected low, comparing waveforms a and b in FIG.
The margin between S and time X to T is reduced, and there are cases in which time S and time R both enter within the period of W of the waveform h in FIG. In this case, the digital low-pass filter 12,1
The change time of "1" and "0" of the output of 3 coincided, and it would be confusing if it was connected to DFF5, 4 which detects the start and end of transmission as it is.

Countermeasures are D / FF 26-28 and AND gate 29. DF
The clock input terminals of F26 to 28 are connected to the clock input terminal 14. DFFs 26 and 27 delay the output (waveform 1) of the digital low-pass filter 13 by two clock periods. The output waveforms of the D · FFs 26 and 27 are waveforms m and n, respectively. AN
The D gate 29 takes the product of the input of D.FF26 (waveform 1) and the output of D.FF27 (waveform n) to synthesize waveform 0.

On the other hand, the output of the digital low-pass filters 12 and 13 is "1".
When the change period of "0" is matched with that of "0", the output of D · FF28 becomes like the waveform p. Comparing the waveform p with the waveform o, the pulse width of the digital low-pass filter 13 is compressed by the DFFs 26 and 27 and the AND gate 29 as shown in the waveform o, and as described above, the clock frequency of the clock input terminal 14 is increased. It can be seen that the problem when lowering the value was avoided. When the switches 23 and 24 are connected to the D / FF 28 and the AND gate 29 side, respectively, the bus is used as a normal condition to provide a bus / interfence circuit with good noise resistance.

However, when such a circuit is included in an LSI, there is a problem in mass production test time. That is, in order to check the function in the LSI, it is necessary to rewrite the data at each address in the LSI one after another and check it. In this case, input the fastest clock to the clock / bus signal input terminal 2. I want to test However, the digital low-pass filter 12,13
And if there is a circuit such as D-FF26,27, that becomes impossible, and even if the fastest clock is input to the clock input terminal 14, the signal that can be input to the clock / bus signal input terminal 2 is "1". The period requires three cycles of the fastest clock, which increases the test time accordingly. Therefore, during the test, the control input terminal 25 is controlled so that the switches 23 and 24 bypass the digital low-pass filters 12 and 13, the D.FFs 26 to 28, and the AND gate 29 to restore the configuration of the conventional example.

As described above, according to the present invention, the digital low-pass filter connected to the bus signal input terminal, the switch bypassing the digital low-pass filter, and the output of the digital low-pass filter on the clock bus signal side By providing the circuit for compressing the pulse width of, the bus interface circuit having good rejection characteristics against external noise and good LSI mass production characteristics can be realized.

In the embodiment, the two-wire serial data bus has been described, but the three-wire uniform data serial data bus is not suitable for a system that transmits / receives signals based on mutual level and edge of signals. The bus interface circuit of this configuration is effective.

[Brief description of drawings]

FIG. 1 is a block diagram of a bus interface circuit in an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, FIG. 3 is a conceptual diagram of a serial data bus, and FIG. 4 is a serial diagram. FIG. 5 is a block diagram of a bus interface circuit in the conventional example, which is a waveform diagram of the data bus. 1 ... Data bus signal input terminal, 2 ... Clock bus signal input terminal, 3 ... Data output terminal, 4 ... Transmission end detection output terminal, 5 ... Transmission start detection output terminal, 6-8
...... D flip-flop, 12,13 ...... Digital low-pass filter, 15 to 17 ...... D flip-flop, 19 to 21 ...
… AND gate, 22 …… OR gate, 23,24 …… Switch, 26
~ 28 …… D flip-flop, 29 …… AND gate.

Claims (2)

[Claims] 1. A data bus signal input terminal and a clock
A bus signal input terminal, a first digital lowpass filter connected to the data bus signal input terminal, a second digital lowpass filter connected to the clock bus signal input terminal, and the second digital lowpass filter A delay circuit connected to the output terminal of the digital low-pass filter, an AND gate for multiplying the input and output of the delay circuit, an output signal of the first digital low-pass filter and an output signal of the AND gate are data. A bus interface circuit comprising a D flip-flop as an input or a clock input. 2. A digital low-pass filter comprises three D flip-flops connected in series, and three ANs for multiplying two different outputs of the three D flip-flops.
The three D flip-flops are composed of a D gate and an OR gate that takes the sum of the AND gates.
2. The bus interface circuit according to claim 1, wherein the bus interface circuit is driven by a clock asynchronous with an input signal to the low pass filter.