JPH07114211B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing various single semiconductor devices or semiconductor devices such as semiconductor integrated circuit devices.

[0002]

2. Description of the Related Art In the manufacture of various semiconductor devices, a process of selectively etching a polycrystalline semiconductor layer or an amorphous semiconductor layer formed on a semiconductor substrate, such as a silicon substrate, is often involved.

An example of a conventional method for forming a polycrystalline semiconductor layer of silicon on a silicon substrate and selectively etching the polycrystalline semiconductor layer to obtain a semiconductor device will be described with reference to FIGS. 9 to 13.

In this example, an NPN type bipolar transistor is obtained.

First, as shown in FIG. 9A, a P-type single crystal silicon substrate 1 is provided, and an N-type buried region 2 is formed facing one main surface 1a thereof by selective diffusion or the like.

As shown in FIG. 9B, an N type silicon semiconductor layer 3 is epitaxially grown on the main surface 1a of the substrate 1 to form a single crystal silicon substrate 4.

As shown in FIG. 10A, in the silicon semiconductor layer 3 of the substrate 4, a portion 3a which finally forms an emitter / base region and a portion 3b which forms a collector extraction electrode are left on the buried region 2. The portion is selectively thermally oxidized to form a thick oxide insulating layer 5.

As shown in FIG. 10B, a polycrystalline silicon semiconductor layer 6 which is entirely doped with P-type impurities such as boron B on the semiconductor layer 3 including the oxide insulating layer 5 is chemically vapor-deposited. Method (CVD method), and, for example, the base electrode lead-out region and the portion which will finally become the base electrode are left, and the other portions are selectively etched and patterned.
Then, a mask layer 7 of SiO ₂ oxide is similarly formed on the entire surface including the polycrystalline silicon semiconductor layer 6 by the CVD method, for example.

As shown in FIG. 11A, the mask layer 7 is photoetched to selectively form a window 7a on a portion of the portion 3a of the semiconductor layer 3, particularly on a portion where an emitter region is finally formed. The polycrystalline silicon layer 6 is selectively etched through the window 7a to form the window 6 corresponding to the window 7a.
a is drilled.

As shown in FIG. 11B, P-type impurities such as boron B are selectively ion-implanted into the portion 3a of the semiconductor layer 3 through the windows 7a and 6a using the polycrystalline silicon layer 6 and the mask layer 7 thereabove as a mask. Implantation is performed to form a P-type impurity implantation region 8.

As shown in FIG. 12A, the SiO ₂ oxide insulating film 9 including C on the region 8 is formed so as to close the window 7a.
Polysilicon which is entirely formed by the VD method or the like, and is further heat-treated to activate the ion-implanted region 8 to form a base region, and the impurity-doped polycrystalline silicon directly deposited on the portion 3a. Part 6a of the impurities from layer 6
To form a high-concentration region 8a for taking out the base electrode, for example, around the base region 8.

As shown in FIG. 12B, the oxide insulating layer 9 is photoetched to form a window 9 in a part of the region 8.
The oxide insulating layer 9 and the mask layer 7 under the oxide insulating layer 9 are selectively etched on the other portion 3b of the semiconductor layer 3 to form a window 10 exposing the portion 3b to the outside. Then, N type impurities are ion-implanted through the windows 9a and 10, respectively, to form an emitter region 11 and a low resistance region 12 for taking out the collector electrode.

As shown in FIG. 13, a window 13 for exposing the polycrystalline silicon layer 6 to the outside is formed in a part of the polycrystalline silicon layer 6 connected to the base electrode take-out region 8a, and the windows 9a, 10, 13 are formed.
Through, metal electrodes of the emitter electrode 14, the collector electrode 15, and the base electrode 16, for example, aluminum electrodes are formed respectively. In this case, the thin silicon polycrystalline layer 17 is formed by the CVD method or the like, if necessary.

In this way, the portion 18 of the portion 3a of the semiconductor layer 3 on the buried region 2 of low resistance on the substrate 4 is used as the collector region, and the base region 8 is formed thereon.
Further, an NPN having an emitter region 11 formed thereon
A bipolar transistor is obtained.

According to the method of manufacturing the bipolar transistor as described above, the base is formed by impurity diffusion from the portion of the polycrystalline silicon semiconductor layer 6 which is a part of the base electrode, which is directly connected to the portion 3a of the semiconductor layer 3. Since the base electrode take-out region 8a of the region 8 is formed, the positional relationship between the region 8a and the silicon polycrystalline layer 6 as the base electrode is automatically set, that is, so-called self-aligned. The base electrode can be easily taken out from the narrow surface portion of the.

[0016]

Various problems occur when selective etching of a polycrystalline layer is involved as in the method of manufacturing a semiconductor device described above.

This problem will be described with reference to FIG. FIG. 14 shows an enlarged cross-section of the main part of FIG. 12A with the oxide insulating layer 9 removed, and in FIG. 14, parts corresponding to those of FIG. 12A are denoted by the same reference numerals.

The first problem is that when the surface of the polycrystalline layer 6 has irregularities due to the particles, selective etching is carried out through the window 7a of the oxide film 7 formed thereon. When the etching depth is limited to the surface of the semiconductor layer 3, the uneven surface 19 that follows the unevenness of the surface of the polycrystalline silicon layer 6 is formed. When such an uneven surface 19 is formed, Since the lower surface of the base region 8 formed by ion implantation from the surface 19 also has irregularities, when the emitter region 11 is formed on the base region 8 as described above with reference to FIG. The distance between the collector and the collector is not uniform, which causes an accident such as so-called punch-through. In addition, stable characteristics cannot be obtained due to the unstable uneven surface. Control and reproducibility has the disadvantage that bad.

The second problem is that when the polycrystalline silicon layer 6 is etched by ordinary wet etching, the etching rate is isotropic, so that the etching window 6a has an oxide mask. Window 7 of layer 7
When a region 8a is formed by diffusing impurities from the polycrystalline silicon layer 6 into the semiconductor layer 3 because a so-called side etching that is larger than a, that is, enters into the periphery of the window 7a occurs, the region 8a is formed. There may be a problem such that a gap g is formed between the center base region 8 and the original base region 8 and the two do not communicate with each other.

Furthermore, as a third problem, when a polycrystalline silicon layer pre-doped with impurities as described above is used, for example, in a semiconductor integrated circuit, a resistor is formed by the other portion of this polycrystalline layer. In this case, since this is also used as the base electrode, it has a low specific resistance.
There is a drawback in that the degree of integration is reduced, such as making the pattern delicate or increasing the length of the resistor pattern.

As described below, it is effective to apply crystallographic etching as a method for avoiding such drawbacks.

However, in the case of such an etching method, the semiconductor layer as the layer to be etched is isotropically etched and is formed by side etching to form a large opening (window) to form a fine pattern. This is a problem for accurate formation, and when impurities are introduced into the semiconductor layer as described above, this introduction of impurities may cause resistance to the above-mentioned isotropic etching.

The present invention solves such a problem.

[0024]

According to the present invention, in a method of manufacturing a semiconductor device including a step of selectively etching and removing a semiconductor layer on a semiconductor substrate, a semiconductor layer is provided with respect to isotropic etching of the semiconductor layer. A first step of introducing impurities having etching resistance, a second step of selectively anisotropically etching the semiconductor layer while leaving a part of the semiconductor layer in the thickness direction, and in the thickness direction of the semiconductor layer The third step of removing the partially left region by the above isotropic etching is adopted.

Further, according to the present invention, the impurity diffusion process is performed before the third process after the second process.

Further, according to the present invention, in the first step, the impurities are introduced into the semiconductor layer so that the semiconductor layer has a peak of the impurity concentration in at least a part of its thickness direction.

Furthermore, according to the present invention, in the second step, the region including the peak portion of the impurity concentration is removed by anisotropic etching.

[0028]

According to the above-mentioned method of the present invention, the semiconductor layer on the semiconductor substrate is first anisotropically etched to a certain depth, and then isotropically etched, so that side etching is extremely small. Etching can be performed, but particularly when introducing an impurity that is resistant to etching against isotropic etching to the semiconductor layer, the impurity concentration peak of the impurity introduction should be located in a part of the thickness direction. By doing so, this peak portion can be removed by anisotropic etching in the opening, that is, in the portion where etching is performed, and the inhibition of etching due to the introduction of impurities for the subsequent isotropic etching can be effectively avoided.

[0029]

EXAMPLES Examples of the present invention will be described. In this case, a so-called crystallographic etching is applied to a semiconductor substrate, for example, a silicon substrate, that is, an etching solution having a dependence on a plane index of a single crystal semiconductor is used. In other words, by specifying the plane index, the etching is carried out by utilizing the difference in etching rate between this and the polycrystalline or amorphous semiconductor layer formed thereon.

Furthermore, the controllability of etching is obtained by utilizing the fact that the etching rate depends on the doping amount of impurities into the polycrystalline or amorphous silicon semiconductor layer.

Furthermore, the controllability of the selective etching for the polycrystalline or amorphous semiconductor layer is further improved by the relationship between the impurity doping amount and the etching property, and by the combination with the dry etching.

As the etching liquid having a large dependence of the etching rate on the plane index of the semiconductor single crystal substrate, for example, KOH etching liquid or APW (amine, pyrocatechol, water) etching liquid is used, while the above-mentioned main surface of the semiconductor substrate is used. Is specified as a 111 crystal plane having a small surface index with respect to the etching solution, a polycrystalline semiconductor layer or an amorphous semiconductor layer is formed on the crystal plane, and the selective etching I do.

Ion implantation having a peak concentration of impurity ion implantation is performed in at least a part of the thickness direction of the polycrystalline semiconductor layer or the amorphous semiconductor layer on the semiconductor substrate described above, and then this polycrystalline Dry etching is performed to leave a part of the semiconductor layer or the amorphous semiconductor layer in the thickness direction, and then wet etching having dependency on the above-described surface index on the etching rate is performed.

Further, with respect to the thickness direction of the polycrystalline semiconductor layer or the amorphous semiconductor layer formed on the semiconductor substrate selected to have the above-mentioned plane index, the impurity concentration peak is partially present except in the vicinity of the interface with the semiconductor substrate. After removing the portion including at least the ion implantation peak portion by dry etching after performing an ion implantation having, an annealing treatment is performed,
Substantially different amounts of impurities are formed in the plane direction of the polycrystalline semiconductor layer or the amorphous semiconductor layer, and then the plane index described above is applied to the polycrystalline semiconductor layer or the amorphous semiconductor layer. Wet etching having dependence is performed.

Example 1 This example is the same as the case described above with reference to FIGS.
This corresponds to the case of obtaining a PN type bipolar transistor, and will be described with reference to FIGS. 1 to 10. 1 to 10, those parts corresponding to those in FIGS. 9 to 13 are designated by the same reference numerals.

In this example, as shown in FIGS. 1A, 1B and 1C, the same steps as those in FIGS. 9A, 9B and 10A are performed. That is, also in this example, the silicon semiconductor layer 3 is epitaxially grown on the single crystal, for example, the silicon semiconductor substrate 1 to form the silicon substrate 4. In this case, the surface direction of the substrate 4 is {11.
1} A substrate having a crystal plane. That is, the principal surface 1a of the substrate 1 shown in FIG. 1A is selected as the {111} crystal plane, and therefore the plane direction of the silicon semiconductor layer formed on the principal surface 1a is also formed as the {111} crystal plane.

Then, as shown in FIG. 2A, the surface index {1
For example, the polycrystalline silicon layer 26 is formed on the substrate 4 selected in 11} by the CVD method to have a thickness of 3000 Å, for example, but in the present invention, this polycrystalline silicon semiconductor layer 26 is formed at the time of formation thereof. It is formed as a polycrystalline silicon layer not doped with impurities, and then impurities are introduced. That is, impurity ions such as B ⁺ or B with a required impurity concentration in a required portion of the semiconductor layer 26.
Ions are implanted with F ₂ ⁺ or As ⁺ having a concentration distribution described later.

That is, in this case, in the ion implantation to the polycrystalline silicon layer 26, the peak value of the impurity concentration distribution is set to the interface with the semiconductor layer 3 in order to avoid the influence on the concentration to the semiconductor layer 3 as much as possible. The polycrystalline silicon layer 26 is arranged at a more distant position, that is, at an intermediate portion or a surface side in the thickness direction of the polycrystalline silicon layer 26, for example.

Similarly, as shown in FIG. 2B, the oxide mask layer 7 is entirely formed by, eg, CVD method.

Then, as shown in FIG. 2C, a window 7a is formed in the oxide mask layer 7 by, for example, photoetching in the same manner as described with reference to FIG. 11A, and the window 7a is formed.
Through, the polycrystalline silicon layer 26 thereunder is selectively etched to form a window 26a corresponding to the window 7a.

The opening of the window 26a, that is, the selective etching of the polycrystalline silicon layer 26 is anisotropic etching and crystallographically anisotropic but isotropic with respect to the polycrystalline silicon layer 26. At least two steps are performed.

That is, in this case, the etching of the polycrystalline silicon layer 26 is performed by a combination of dry etching capable of directional etching, for example, reactive ion etching (RIE) and wet etching by crystallographic etching. .

That is, for example, as shown in FIG. 5A, the polycrystalline silicon layer 26 is etched through the window 7a by dry etching by RIE to a required depth d leaving a part of the thickness of the polycrystalline silicon layer 26. Then, as shown in FIG. 5B, the remaining thickness of the polycrystalline silicon layer 26 is etched through the window 7a by wet etching by crystallographic etching to obtain the window 2a.
6a is to be drilled.

This crystallographic etching is carried out by using an etching solution such as KOH which has a dependency on the surface index of silicon.
Solution (aqueous solution of KOH 250 g relative to H ₂ O 2000 cc) or APW liquid (ethylenediamine N
H ₂ (CH ₂ ) ₂ and pyrocatechol C ₆ H ₄ (OH) ₂
And H ₂ O are mixed at 255 cc, 45 g, and 120 cc) to perform the etching. At this time, the etching of the polycrystalline silicon layer 26 progresses relatively quickly, but when the etching of silicon progresses to the point where the {111} crystal planes of the surface of the semiconductor layer 3 are exposed, the etching rate here rapidly decreases. Since the etching apparently stops, the etching process is stopped at this point. By doing so, a window 26a is formed by removing only the polycrystalline silicon layer 26 by etching, and the surface of the semiconductor layer 3 exposed in the window 26a becomes a smooth surface of the {111} plane.

That is, the above-mentioned KOH solution or AP
An etching solution having so-called crystallographic anisotropy, such as a W solution, has an etching rate for the {111} plane of a silicon single crystal that is 1/100 of that for the {100} plane.
It is as low as 1000. However, in the polycrystalline semiconductor layer, both of these crystal planes {100} and {11}
Since the 1} planes and the like exist in a mixed manner, the etching of the polycrystalline silicon layer 26 mainly progresses around the {100} plane having a high etching rate. As a result, the etching progresses quickly.

However, when the etching reaches the surface of the substrate 4 having the {111} plane, that is, the semiconductor layer 3,
Since the etching rate is remarkably reduced, the progress of etching is apparently stopped here. Therefore, if the etching process is terminated at this point, only the polycrystalline layer 26 is removed and the surface of the semiconductor layer 3 having a smooth surface of the {111} plane is exposed.

Next, as shown in FIG. 3A, windows 7a and 26a are provided.
Ion-implanted regions 8 are formed by ion-implanting P-type impurities, such as boron B, into the portion 3a of the semiconductor layer 3 exposed through a.

Next, as shown in FIG. 3B, an oxide insulating layer 9 similar to that described with reference to FIG. 12A is formed, and heat treatment is performed to activate the ion-implanted region 8 to be a base region and, for example, its periphery. To the base electrode extraction region 8a by diffusing P-type impurities from the polycrystalline silicon layer 26 into
To form. In this case, it should be noted that the bottom surface of the region 8 is formed as a smooth and flat surface following the ion implantation surface of the semiconductor layer 3 which is smooth and flat.

Next, as shown in FIG. 4A, the base region 8 in the portion 3a of the semiconductor layer 3 is the same as that described in FIG. 12B.
The upper insulating layer 9 and the insulating layers 7 and 9 in the portion 3b are selectively etched by photoetching or the like to open windows 9a and 10, respectively, and N type impurities are ion-implanted through these windows. The emitter region 11 is formed and the collector electrode lead-out region 1 having a low specific resistance is formed.
Form 2.

Next, as shown in FIG. 4B, a window 13 is formed in the mask layers 7 and 9 on a part of the polycrystalline silicon layer 26 to be a base electrode by photoetching, and a base metal electrode 16 is formed in this part. And each area 12 and 1
The collector electrode 15 and the emitter electrode 14 are ohmic-deposited on No. 1 respectively. Each of these electrodes 14, 15 and 16 can be formed in a desired pattern by selectively vapor-depositing an aluminum metal electrode or the like and then selectively etching it. Even in this case, the thin polycrystalline silicon layer 17 can be formed by the CVD method or the like, if necessary.

In this way, an NPN-type bipolar transistor similar to that described with reference to FIG. 13 is obtained, but in the case of the manufacturing method of the first embodiment described above, each emitter region 11 and base region 8 are semiconductors. Since the flat surface is formed by the ion implantation from the smooth surface of the portion 3a of the layer 3, the space between them, that is, the base width can be uniformly and reproducibly obtained. . Further, it is possible to avoid an accident in which the emitter region 11 is punched through to the collector region due to the unevenness, and it is possible to obtain a highly reliable transistor, that is, a semiconductor device.

Then, according to the above-mentioned method, the window 26a
Occurrence of side etching in is effectively suppressed. That is, when the step described in FIG. 5 is omitted and the window 2a is formed only by crystallographic etching, the surface of the semiconductor layer 3 exposed by the window 26a becomes a smooth surface 29 as shown in FIG. Although formed, the polycrystalline silicon layer 2
Because the etching in 6 is isotropic, the window 26
The contour shape of a is larger than that of the window 7a, that is, side etching occurs.

In contrast to this, in the method of the present invention, most of the thickness d of the semiconductor substrate 1 of the polycrystalline silicon layer 26 is anisotropically etched, and the crystallography is performed only in the vicinity of the interface with the remaining portion of the semiconductor substrate 1. Since the static etching, that is, the isotropic etching of the polycrystalline silicon layer is performed, the occurrence of side etching can be suppressed to a small level.

According to the method of the first embodiment described above, it is possible to avoid the occurrence of side etching by combining dry etching and wet etching by crystallographic etching. It is possible to avoid the inconvenience in etching when the impurity concentration implanted into the crystalline silicon layer 26 is increased to obtain a sufficiently low specific resistance.

That is, impurity ions such as B ⁺ , BF ₂ ⁺ , As ⁺ , P ⁺ , are added to the polycrystalline silicon layer.
When Si ⁺ or the like is ion-implanted, the etching rate of the above-mentioned wet etching becomes extremely low in the portion doped with a high concentration, but as in the example described above, the impurity ions are previously implanted into the polycrystalline silicon layer 26. At that time, the peak of the concentration distribution of the impurity concentration is located at the intermediate portion or the surface side which is separated from the interface between the polycrystalline silicon layer 26 and the semiconductor layer 3, and the impurity ions are highly doped during the dry etching described above. By performing the etching to a deeper portion, for example, to a position deeper than the depth showing the peak value of the concentration, and then performing the wet etching, the high-concentration portion of impurities is removed, so that the wet etching is favorably performed.

Since the polycrystalline silicon layer 26 to be the remaining electrode or wiring is sufficiently doped with impurities, the impurities from this are diffused into the semiconductor layer 3 and the low resistance electrode extraction region 8a is formed. Can be formed, and can itself be an electrode or wiring having a low specific resistance.

Further, the effect of performing selective etching by performing wet etching after the above-mentioned dry etching by RIE will be described in detail with reference to FIGS. explain.

In FIG. 6, a curve 31 indicated by a broken line shows a concentration distribution when BF ₂ ⁺ ions are implanted into the polycrystalline silicon layer 26 at an acceleration of 60 keV and a dose of 5 × 10 ^15. The depth showing the peak value of the concentration of R, that is, R _P is about 440 Å.

Similarly, the solid curve 32 in the figure shows B ⁺ ions of 30 keV, 5 × in the polycrystalline silicon layer 26.
It shows the concentration distribution in the polycrystalline silicon layer when ions are implanted with a dose of 10 ¹⁵ and the depth R _P showing the peak value in this case is about 1000Å. The etching rates of the crystallographic wet etching for the polycrystalline silicon layer for those showing such respective concentration distributions 31, 32 are as shown by the curved lines 41 and 42 in FIG. In the portion where the distribution is high, the etching rate hardly increases and the concentration becomes low, and the etching rate is rapidly increased. As described above, the etching rate largely depends on the ion implantation concentration in the polycrystalline silicon layer.

Therefore, when the polycrystalline silicon layer 26 is subjected to the ion implantation whose concentration distribution in the thickness direction is shown by the curve 31 in FIG. 6, the dry etching is performed at the depth d shown by the chain line in FIG. If wet etching is performed after that, etching is performed in a portion having a low impurity concentration, so that etching can be sufficiently performed at a high etching rate.

However, in the case of ion implantation with the distribution of the curve 32 in FIG. 6, similarly, even if the wet etching is performed after the dry etching of the depth d shown in FIG. 6, the etching is difficult to proceed.

Therefore, when the method described with reference to FIGS. 5A and 5B is adopted, the impurity concentration distribution and the dry etching depth d must be selected in relation to each other. Incidentally, the impurity concentration is 10 ¹⁹ atoms / cm ³
If above, the crystallographic wet etching, impurity ions B ^+, BF ₂ ⁺ becomes 50 Å / min or less etch rate when, when the As ⁺ 500 Å / min, P ⁺
Is 600 Å / min, and Si ⁺ is 400 Å / min. When the concentration is 10 ¹⁷ atoms / cm ³ or less, the respective etching rates are high, and it is about 1500 Å / min for polycrystalline silicon containing almost no impurities. Further, when the similar concentration is 10 ²⁰ atoms / cm ³ or more, the etching rate becomes the minimum.

Furthermore, as described above, in the case where the wet etching is performed after the dry etching, when the method of performing the annealing treatment after the dry etching and then performing the wet etching is performed, the side etching is further suppressed. be able to.

That is, now, when considering the case where impurity ions are implanted into the polycrystalline silicon layer with the concentration distribution shown by the solid line curve 51 in FIG. 8, when performing heat treatment, that is, annealing treatment after the ion implantation, Impurities in the peak portion are diffused to have a pinhole characteristic as shown by a curve 51 'shown by a broken line. However, in the case of having such a distribution 51, when it is removed by dry etching, for example, RIE from the surface to the position of depth d in FIG. Because it is a change in part, 5
The change is as small as 1 ″.

Therefore, as described with reference to FIG. 5, when a part of the polycrystalline silicon layer 26 is left and the dry etching is performed to a depth larger than the depth R _P showing the peak value of the impurity ions, the dry etching is performed. The concentration distribution at the bottom of the etched groove is lower than that shown by the curve 51 ″ in FIG. 8, whereas in the other portions, the high concentration portion is eliminated by dry etching. Since it does not exist, the density is higher than that of the curve 51 "shown by the broken line 51 '.

Therefore, when the crystallographic wet etching is performed thereafter, the groove or window 7 having a low impurity concentration is formed.
Under a, the etching rate is high, but in other areas, the etching rate is lower than this, so that side etching hardly occurs and the etching of the pattern corresponding to the window 7a is polycrystalline. It will be done in the silicon layer 26.

In this case, as described above, the etching rate sharply decreases when the ion concentration is 10 ¹⁹ / cm ³ or more. It is desirable to select the ion implantation conditions so that the concentration exceeds 10 ¹⁹ / cm ³ , and when selecting such a concentration, the above-mentioned polycrystalline silicon layer is used as a part of the base electrode, for example. The specific resistance can be low enough to be used.

Further, as described above, when the method of dry etching → annealing → wet etching is used, the selective fine pattern etching of the polycrystalline silicon layer 26 can be performed with a high degree of fineness. .

Although the selective etching of the polycrystalline silicon layer has been described in the above-mentioned example, the same effect can be obtained by applying it to the case where another polycrystalline or amorphous semiconductor etching process is involved.

Further, the above example is the case where the present invention is applied to the case of obtaining the NPN bipolar transistor, but in the case of obtaining various other single semiconductor devices or various semiconductor integrated circuit devices including high density integrated circuits. The present invention can be applied to.

[0071]

As described above, according to the present invention, selective etching with small side etching of the semiconductor layer can be performed.

In particular, the side etching can be arbitrarily controlled by applying a combination of the concentration distribution by ion implantation of impurities and further dry etching, and a highly reliable semiconductor device can be obtained because fine patterning of the semiconductor layer can be achieved according to the purpose. In addition to being obtainable, it is possible to achieve high density in a semiconductor integrated circuit, for example.

Further, in the manufacturing method of the present invention, after the polycrystalline or amorphous semiconductor layer is formed, impurities are introduced, for example, ion implantation is performed. Therefore, by selecting the concentration pattern of the ion implantation, for example, the semiconductor is used. When a resistor is formed by a polycrystalline silicon layer in an integrated circuit or the like, the specific resistance in this portion can be increased, which allows miniaturization of the resistor pattern and higher integration density. .

[Brief description of drawings]

FIG. 1 is a process diagram (1) of an embodiment of the method of the present invention.

FIG. 2 is a process diagram (2) of an embodiment of the method of the present invention.

FIG. 3 is a process drawing (3) of an embodiment of the method of the present invention.

FIG. 4 is a process drawing (4) of an embodiment of the method of the present invention.

FIG. 5 is a partial process chart of an embodiment of the method of the present invention.

FIG. 6 is a distribution diagram of impurity ion concentration.

FIG. 7 is a characteristic diagram of an etching rate.

FIG. 8 is an impurity ion concentration distribution chart.

FIG. 9 is a process diagram (1) of a conventional method.

FIG. 10 is a process diagram (2) of the conventional method.

FIG. 11 is a process diagram (3) of the conventional method.

FIG. 12 is a process diagram (4) of the conventional method.

FIG. 13 is a process diagram (5) of the conventional method.

FIG. 14 is a diagram for explaining a case of a conventional method.

FIG. 15 is a diagram for explaining a comparative example.

[Explanation of symbols]

 1 Semiconductor Substrate 3 Semiconductor Layer 4 Semiconductor Substrate 26 Polycrystalline Semiconductor Layer 7 Oxide Mask Layer 7a Window

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor device, which includes a step of selectively etching away a polycrystalline semiconductor layer on a single crystal semiconductor substrate, wherein the semiconductor layer has etching resistance against isotropic etching of the semiconductor layer. A first step of introducing an impurity having a concentration of the impurity so as to be located at a position separated from an interface with the semiconductor substrate, and selectively leaving the semiconductor layer partially in the thickness direction. A second step of anisotropically etching to a depth that removes a region including a peak portion of the impurity concentration, and a region left partially in the thickness direction of the semiconductor layer with respect to the etching rate with respect to the single crystal semiconductor substrate And a third step of removing the polycrystalline semiconductor layer by isotropic etching having a smaller etching rate than the etching rate of the polycrystalline semiconductor layer. 2. A method of manufacturing a semiconductor device, which comprises a step of selectively etching away a polycrystalline semiconductor layer on a single crystal semiconductor substrate, wherein the semiconductor layer has etching resistance against isotropic etching of the semiconductor layer. A first step of introducing an impurity having a concentration of the impurity so as to be located at a position separated from an interface with the semiconductor substrate, and selectively leaving the semiconductor layer partially in the thickness direction. The second step of anisotropically etching to a depth that removes the region including the peak portion of the impurity concentration, and the region left partially in the thickness direction of the semiconductor layer, the etching rate for the single crystal semiconductor substrate A second step of removing the crystalline semiconductor layer by the isotropic etching having a smaller etching rate than the etching rate, and after the second step and before the third step, an impurity diffusion process is performed. Method of manufacturing a semiconductor device and performing.