JPH07114393B2 - Interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used for an interface circuit of a time division multiplexer of a digital network. In particular, the present invention relates to a loopback test control circuit in an interface circuit that functions as an interface with a digital network.

〔Overview〕

According to the present invention, in an interface circuit, received data from a digital network is synchronized with a frame aligner speed conversion circuit at an in-device reference timing of a time division multiplexing device to select a predetermined time slot in the received data to perform time division multiplexing. Even if an error occurs in a specific time slot after the service is started by inserting it in the transmission data of the device and giving it to the transmission part, it will not affect other active time slots and the corresponding time slot. It is possible to turn back and isolate the faulty part.

[Conventional technology]

FIG. 3 is a block diagram of a conventional interface circuit.

Conventionally, the interface circuit has two types of folding functions, that is, folding on the digital network side and folding on the device side. This is because the main purpose is to separate the line on the digital network side from the line on the device side to judge pass / fail, so the return is performed by bundling each line. FIG. 3 shows a block diagram of a conventional interface circuit.

[Problems to be solved by the invention]

However, in such a conventional interface circuit,
In particular, when returning to the transmission line side, that is, to the digital network side, since each digital line is folded back in a bundle, it is possible to perform the return before the service is started on that digital network, but once the service starts When an error occurs in the data of a specific time slot after the above, if the above-mentioned folding is performed, it is almost impossible to use the folding function as a practical problem in order to kill all the other timeslots in use. It was impossible, and there was a problem that it was extremely difficult to isolate the faulty part.

The present invention solves the above-mentioned problems. Even if an abnormality occurs in a specific time slot after the service is started, the corresponding time slot is folded without affecting other active time slots. It is an object of the present invention to provide an interface circuit that can be returned and can isolate a fault location.

[Means for solving problems]

The present invention is directed to a receiving unit that inputs a data signal from a transmission line connected to a digital network and outputs received data and received clock timing, and the above transmission based on the transmitted clock timing from a time division multiplexing device that receives transmitted data. In the interface circuit including a transmission unit for transmitting to the channel, the received data is stored based on the received clock timing, and is read at the device clock timing and the device frame timing of the time division multiplexing device to perform the time division multiplexing. A first speed conversion circuit to be provided to the device, and the transmission data to be stored based on the in-device clock timing and the in-device frame timing, read based on the transmission clock timing, and given to the transmission section as the transmission data The speed conversion circuit and the predetermined selection control pulse are generated. And a selection control circuit for selecting the output of the first speed conversion circuit or the transmission data of the time division multiplexer based on the predetermined selection control pulse and giving the selected data to the second speed conversion circuit. It is characterized by having.

[Action]

The first speed conversion circuit includes a memory having a capacity of at least one frame of received data, stores the received data in this memory based on the received clock timing, and reads it at the in-device clock timing of the time division multiplexing device and the in-device frame timing. To the time division multiplexer. The second speed conversion circuit stores the transmission data at the internal clock timing and the internal frame timing of the time division multiplexer, reads the transmission data at the transmission clock timing from the time division multiplexer, and gives it to the transmitter. The selection control circuit selects the reception data from the first speed conversion circuit for each predetermined time slot based on a predetermined selection control pulse of the pulse generation circuit and inserts it into the transmission data from the time division multiplexer. Even if an error occurs in a specific time slot after the digital network service is started by the above operation, the corresponding time slot can be returned without affecting other active time slots. Can be divided into parts.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. First
The figure is a block diagram of an interface circuit according to an embodiment of the present invention. In FIG. 1, the interface circuit comprises a receiving section 2 for inputting a data signal from a transmission line 17 connected to a digital network, outputting reception data 11 and reception clock timing 10 extracted from the data signal, and transmission data 18.
And a transmission unit 9 for transmitting to the transmission line 17 based on the transmission clock timing 13 from the time division multiplexer.

Here, the feature of the present invention is that the received data 11 is stored based on the reception clock timing 10, and is read at the internal clock timing 12 and the internal frame timing 15 of the time division multiplexing device to perform the time division multiplexing. The frame aligner speed conversion circuit 3 as the first speed conversion circuit to be given to the apparatus, and the data is stored on the basis of the in-apparatus clock timing 12 and the in-apparatus frame timing 15, and is read out based on the transmission clock timing 13 to the transmission section 9 as transmission data 18. Speed conversion circuit 8 as a second speed conversion circuit to give
A pulse generating circuit 7 for generating a predetermined selection control pulse 14; and an output of the frame aligner speed conversion circuit 3 and transmission data 5 of the time division multiplexing device based on the predetermined selection control pulse 14. And a selection control circuit 6.

The operation of the interface circuit having such a configuration will be described.

FIG. 2 is a diagram showing the signal timing of each part of the interface circuit of the present invention.

In FIG. 1, the receiver 2 in the interface circuit 1
Receives the data signal from the transmission line 17, extracts the reception clock timing 10, and supplies it to the frame analyzer speed conversion circuit 3 together with the reception data 11 that has undergone code conversion and level conversion. The frame analyzer speed conversion circuit 3 is a circuit mainly for wander absorption and frame phase synchronization, and is composed of a memory and a reading and writing counter.
The reception data 11 written at the reception clock timing 10 on the 17 side is read at the in-device frame timing pulse 15 and the in-device clock timing 12 on the device side, and the read reception data 4 is sent to the device side. At the same time, the reception data 4 is also given to the selection control circuit 6 as return data. The selection control circuit 6 uses the selection control pulse 14 of the pulse generation circuit 7.
On the basis of the above, the received data 4 and the transmitted data 5 having the same frame timing are selected for each time slot. The output of the selection control circuit 6 is the transmission data to the transmission line 17 side.
The signal is passed through the speed conversion circuit 8 as 16 and is code-converted and level-converted by the transmitter 9 and then transmitted to the transmission line 17. Like the frame aligner speed conversion circuit 3, the speed conversion circuit 8 is composed of a memory and a counter, and the transmission data 16 written at the in-device lock timing 12 is transmitted at the transmission clock timing 13 corresponding to the physical speed on the transmission line 17. Read.

In FIG. 2, in-apparatus frame timing pulse 15
Is a signal indicating a unit frame in the apparatus, and the phases of the reception data 4 and the transmission data 5 are matched with each other by the frame aligner speed conversion circuit 3 and the like. Here, for example, when it is desired to return only the reception data of the time slot TS3 to the transmission path 17 side, the pulse generation circuit 7 generates the selection control pulse 14 and selects the reception data only at the timing of the time slot TS3. The transmission data 16 selected in this way is transmitted to the transmission path 17 side.

〔The invention's effect〕

As described above, the present invention is applicable without affecting other active time slots even when an abnormality such as a data error occurs in a specific time slot after the service of the digital network is started. Only the time slot can be folded back, and it has an excellent effect that is very useful for isolating the failure point.

[Brief description of drawings]

FIG. 1 is a block diagram of an interface circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing the signal timing of each part of the interface circuit of the present invention. FIG. 3 is a block diagram of a conventional interface circuit. 1 ... Interface circuit, 2 ... Reception unit, 3 ... Frame aligner speed conversion circuit, 4, 11 ... Received data,
5, 16, 18 ... Transmission data, 6, 20 ... Selection control circuit,
7 ... Pulse generation circuit, 8 ... Speed conversion circuit, 9 ... Transmission unit, 10 ... Reception clock timing, 12 ... Internal clock timing, 13 ... Transmission clock timing,
14 …… Selection control pulse, 15 …… Internal frame timing pulse, 17 …… Transmission path (digital network), 21 …… Folding data clock, 22 …… Sending data clock, 23 ……
Loopback control signal.

Claims (1)

[Claims] 1. A receiver for receiving a data signal from a transmission line connected to a digital network and outputting received data and received clock timing; and a receiver for receiving transmitted data and transmitting clock timing from a time division multiplexer. In an interface circuit including a transmitting section for transmitting to a transmission line, the received data is stored based on the received clock timing, and is read out at the internal clock timing and the internal frame timing of the time division multiplexing apparatus to perform the time division multiplexing. A first speed conversion circuit to be provided to the digitizing device, the transmission data being stored based on the device clock timing and the device frame timing, and read based on the transmission clock timing and applied to the transmission unit as the transmission data. Second speed conversion circuit and predetermined selection control pulse And a selection control circuit for selecting the output of the first speed conversion circuit or the transmission data of the time division multiplexer based on the predetermined selection control pulse and giving the selected data to the second speed conversion circuit. An interface circuit comprising: