JPH07114459B2 - Vertical deflection circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a vertical deflection circuit of a TV (television) receiver, and particularly to a TV receiver for displaying characters on a TV screen when there is no signal. A vertical deflection circuit suitable for use in

(B) Prior Art A countdown vertical deflection circuit for generating a vertical drive pulse in response to a vertical synchronization signal from a synchronization separation circuit is disclosed in Japanese Utility Model Laid-Open No. 60-98971.

According to the vertical deflection circuit described in the above publication, when the vertical synchronizing signal arrives, the counter can generate a vertical drive pulse having a constant cycle in synchronization with it. Further, when the vertical synchronizing signal does not arrive, the counter is in a self-reset operation and it is possible to generate a vertical driving pulse having a period longer than the fixed period. The period of the vertical drive pulse during the self-reset operation is normally set to be several tens H (H is one period of the horizontal synchronizing signal) longer than the fixed period, which is longer than the normal period. This is to enable synchronization when a synchronization signal arrives.

By the way, recently, TV receivers that have the function of displaying text information (channel display or video input display) on a part of the TV screen have appeared, but in such cases, vertical disturbance generated from the counter described above. The read operation start time of the memory storing the character information is controlled according to the pulse. By doing so, the character information can be displayed at a predetermined position in the vertical direction. The memory is configured to generate character information a predetermined time after an input trigger (vertical disturbance pulse) is applied. Therefore, when a vertical disturbance pulse having a regular cycle is applied, a desired position can be set on the screen. However, when there is no signal (for example, when receiving an empty channel), the above-mentioned counter generates a vertical disturbance pulse having a long period, and when the memory is disturbed accordingly, the position of the character information on the screen is increased. Has a problem that it is generated in the upper part as compared with the normal case and is unsightly, and in an extreme case, it is shifted out of the screen.

Therefore, a vertical deflection circuit that solves such a problem is disclosed in Japanese Patent Application No.
Proposed in 63-146312. According to the vertical deflection circuit, when the absence of a vertical synchronizing signal from the outside is detected, the vertical counter self-resets in a regular cycle. Therefore, even when there is no signal, character information is displayed at a predetermined position on the TV screen. Can be projected.

(C) Problems to be Solved by the Invention By the way, a vertical sync signal from the outside is separated by a sync separation circuit and then applied to a vertical counter. However, the sync separation circuit uses the vertical sync signal to improve the detection sensitivity. The sync separation sensitivity is increased in the period before and after the arrival of a signal is expected. Therefore, if the vertical counter is in the self-resetting operation in order to display the character information at the correct position as described above, the sensitivity is switched according to the phase. In this state, when a composite sync signal is applied to the sync separation circuit from an external source, the phase relationship is irrelevant, so if the vertical sync signal is applied during a period of low sensitivity, sync separation cannot be performed. I will end up. Then, there is a problem that the phase of the input vertical synchronizing signal and the phase of the vertical driving pulse generated from the vertical counter do not match and vertical synchronization cannot be achieved. In particular, some commercially available video software has a special vertical sync signal that is difficult to detect recorded to prevent dubbing. In that case, the vertical sync signal cannot be detected at all, which is a problem.

(D) Means for Solving the Problems The present invention has been made in view of the above points, and in a vertical deflection circuit including a vertical counter that resets itself in a normal vertical cycle and generates a vertical drive pulse, A no-signal detection circuit for detecting the absence of a vertical synchronization signal coming from the outside and resetting the vertical counter by itself, and a detection means for detecting the arrival of a video signal from the outside are provided, and the detection output of the detection means is used. The vertical counter is switched to an external reset operation.

(E) Operation According to the present invention, since the vertical synchronizing signal does not come from the outside and the vertical counter displays the character information at a predetermined position, even if the self-reset state is set, a new image is received from the outside. When a signal arrives, the signal is detected and the vertical counter is switched so as to perform an external reset operation.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which (1) is a sync for separating a vertical sync signal and a horizontal sync signal from a composite sync signal applied to an input terminal (2). Separation circuit, (3)
Is a horizontal AFC circuit to which the horizontal sync signal from the sync separation circuit (1) is applied, and (4) is a clock signal of a frequency 2f _H (f _H is a horizontal sync signal frequency) from the horizontal AFC circuit (3). Counts and outputs the first to fourth frequency division output signals (φ _{1 to} φ ₄ )
A vertical counter that generates a horizontal deflection current according to the output signal of the horizontal AFC circuit (3), and (6) a vertical synchronization signal from the synchronization separation circuit (1). And an OR gate for passing the _second divided output signal φ ₂ from the vertical counter (4), and (7) is an output signal of the OR gate (6) and a third from the vertical counter (4).
A selection circuit for switching and outputting the frequency-divided output signal φ ₃ ; (8) a no-signal detection circuit for detecting the absence of an incoming vertical synchronizing signal and switching the selection circuit (7) in accordance with the detection output. (9) is a character display memory for generating an image signal having character information in response to a vertical drive pulse from the vertical counter (4), and (10) is an image signal from the character display memory (9) and a terminal ( An addition circuit for adding the luminance signal applied to 11), (12) subtracts the luminance signal from the addition circuit (10) and each color difference signal to generate R, G, B primary color signals. Subtraction circuit, (13) is a cathode ray tube, and (14)
Is a horizontal sync detection circuit that detects the arrival of a video signal and switches the operation of the no-signal detection circuit (8) according to the detection output.

The first divided output signal φ ₁ generated from the vertical counter (4) is between 260.5H and 1.5H of the next vertical cycle, or 26
Signal generated between 0.5H and 264H, second divided output signal φ ₂
Is a signal generated after 297H, the third divided output signal φ ₃ is generated after 262.5H, and the fourth divided output signal φ ₄ is generated after 1.5H.
H indicates one cycle of the horizontal synchronizing signal.

FIG. 1 shows a case where an NTSC system broadcast is being received, and its normal vertical synchronization is 262.5H. First, a case where a station of an empty channel is received and a vertical synchronization signal does not come from the outside and the character information is displayed on the television screen in that state will be described.

In this case, since no vertical sync signal is generated from the sync separation circuit (1), no signal is applied to the OR gate (6) and the no-signal detection circuit (8). Then, the vertical counter (4) advances the counting of the clock signal from the horizontal AFC circuit (3), and when it reaches 297H, generates the _second frequency division output signal φ ₂ . The second frequency-divided output signal φ ₂ is passed through an OR gate (6) and a selection circuit (7) to a vertical counter (4).
Is applied to the reset terminal R and the signalless detection circuit (8). Then, the second divided output signal φ
_In response to ₂ , the no-signal detection circuit (8) generates an "L" level switching control signal indicating that there is no signal, and switches the selection circuit (7) to the contact b side. The vertical counter (4) is reset according to the _second frequency division output signal φ ₂ and then
Counting again, and when it reaches 262.5H, the third divided output signal φ
₃ is generated. Since the third frequency-divided output signal φ ₃ is applied to the reset terminal R of the counter (4) through the selection circuit (7), the vertical counter (4) sequentially performs the self-reset operation thereafter, and then the predetermined period ( 262.5H) vertical drive pulse is generated at the output terminal (15).

The vertical drive pulse is amplified by an amplifier (16) and then supplied to a vertical deflection coil (17) of a cathode ray tube (13) as a vertical deflection current.

On the other hand, the vertical drive pulse is applied to the character display memory (9) as a trigger signal that determines the operation start time. Then, the character display memory (9) starts its operation accordingly, and starts the read operation based on the clock signal supplied from the horizontal AFC circuit (3).
An image signal having text information is generated. Then, the image signal is added to the luminance signal applied to the terminal (11) in the addition circuit (10), and the luminance signal after the addition is subtracted in the subtraction circuit (12).
Applied to. Then, the luminance signal and the terminal (18),
Color difference signals (RY, MY, B- from (19) and (20)
Y) and the primary color signals (R, G, B) are applied to the cathode ray tube (13). Therefore, according to the circuit of FIG. 1, the character information can be generated at the correct position on the TV screen even when there is no signal.

The character information in the embodiment of FIG. 1 is represented in black and white.

Now, the first frequency division output signal φ ₁ applied from the vertical counter (4) to the sync separation circuit (1) is the sync separation circuit (1).
It is for switching the vertical separation sensitivity of. That is, the sensitivity at around 262.5H where the vertical sync signal is expected to come from the outside is increased to improve the sync separation capability.
This is shown in FIG. Now, assuming that the third frequency-divided output signal φ ₃ of 262.5H cycle is generated in the phase as shown in FIG. 2 (a), the sync separation circuit (1) is provided in the phase as shown in FIG. 2 (b).
The sensitivity of is changing. In this state, it is assumed that the composite synchronizing signal in the video signal is applied to the input terminal (2) for the purpose of displaying the video signal from the VTR or the like on the above-mentioned screen which is only the character information. For example, if the vertical sync signal in the composite sync signal has a phase as shown in FIG. 2 (c), the sync separation circuit (1) has a low sensitivity as is clear from the phase relationship with FIG. 2 (b). Located in the period. Therefore, in this state, the vertical synchronizing signal cannot be taken in permanently.

Therefore, in the present invention, the horizontal sync detection circuit (14) detects the presence or absence of a composite sync signal coming from the outside,
If "presence" is detected, the no-signal detection circuit (8) is driven accordingly and the vertical counter (4) can be synchronized with a new vertical synchronization signal from the outside. That is,
The horizontal sync detection circuit (14) compares the phase of the horizontal sync signal from the sync separation circuit (1) with the flyback pulse from the horizontal deflection circuit (5), and if the phases match, "L". A level output signal is generated, and if they do not match, an "H" level output signal is generated. Therefore, when the video signal as described above arrives, the separated horizontal synchronizing signal is applied to the horizontal AFC circuit (3), and the output signal synchronized with it is applied to the horizontal deflection circuit (5). Then, the flyback pulse and the horizontal sync signal having the same phase are applied to the horizontal sync detection circuit (14), so that an "L" level output signal is generated and applied to the no-signal detection circuit (8). When the "L" level signal is applied, the detection output of the no-signal detection circuit (8) is inverted to generate the "H" level switching control signal indicating the presence of the signal, and the selection circuit (7) is activated. Switch to the contact a side. Then 26
The vertical counter (4), which has been performing the self-reset operation at 2.5H, becomes the self-reset operation with the second frequency-divided output signal φ ₂ having a period of 297H shown in FIG. In this case, since the vertical counter (4) is not reset at 262.5H, the first divided output signal φ ₁ is generated between 260.5H and 264H and the second divided output signal φ ₁ is generated.
It is applied to the sync separation circuit (1) as shown in FIG.
Then, if this state continues for several vertical periods (four times in the case of FIG. 2), the vertical synchronizing signal of FIG. 2C and the period of high sensitivity of FIG. As shown in FIG. 2 (f), the vertical sync signal separated in synchronization can be taken in, and the vertical counter (4) can be reset accordingly.

FIG. 3 is a circuit diagram showing a specific circuit example of the no-signal detection circuit (8) of FIG. 1, in which the vertical sync signal from the sync separation circuit (1) applied to the terminal (21) is It is applied to the set inputs of the second flip-flops (22) and (23).
The output signal of the selection circuit (7) is applied to the terminal (25) of the AND gate (24) controlled by the output of the first flip-flop (22), and the output signal of the AND gate (24) is the second signal. Applied to the reset input of the flip-flop (23). Therefore, the Q output terminal (26) of the second flip-flop (23) is at “H” level when there is a signal and “L” when there is no signal.
The discriminant output of the level is obtained.

The fourth input signal φ ₄ is applied from the terminal (27) to the reset input of the first flip-flop (22), which returns the first flip-flop (22) to the initial state, and Any type may be used as long as it occurs within a fixed period after the counter (4) is reset.

FIG. 4 is a circuit diagram showing a specific circuit example of the horizontal sync detection circuit (14) of FIG. 1, in which a negative horizontal sync signal is applied to the first input terminal (28) and a second input terminal (29). A negative horizontal flyback pulse is applied to the output terminal (30) to obtain the detection output. In FIG. 4, the phase of the horizontal synchronization row signal is disturbed and only the flyback pulse is shown in the second line.
When applied to the input terminal (29), the transistor (31) is turned on, so that the transistors (32) and (33) are turned off. When the transistor (32) turns off, the transistor (35) forming the current mirror circuit ( 34 ) turns off. Then, the capacitor (36) is discharged through the resistor (37), and when the voltage at the point A falls below the reference voltage of the reference power supply (38), the output terminal (30) of the comparator (39) is at the “H” level. The detection output of is obtained. Further, when the phases of the horizontal synchronizing signal and the flyback pulse match, the transistors (31) and (40) are turned off, so that the transistors (32) and (3
3) turns on, the transistor (41) turns on, and the transistor (42) turns off. Then, a current equal to the current flowing through the collector-emitter paths of the transistors (32) and (41) flows from the collector of the transistor (35) to the capacitor (36), and the voltage at the point A rises. When the voltage at point A rises above the reference voltage of the reference power supply (38),
An "L" level detection output is obtained at the output terminal (30) of the comparator (39).

(G) Effect of the Invention As described above, according to the present invention, it is possible to display character information and the like at a predetermined position on a television screen, and immediately synchronize with the vertical phase of a new video signal. It is possible to provide a vertical deflection circuit capable of performing the above.
Particularly, according to the present invention, it is possible to deal with the video signal having a special vertical synchronizing signal for preventing dubbing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 (a) to (f) are waveform diagrams for use in explaining FIG. 1,
3 and 4 are circuit diagrams showing the specific circuit example of FIG. (1) …… Synchronous separation circuit, (4) …… Vertical counter,
(7) …… Selection circuit, (8) …… No signal detection circuit, (1
4) ...... Horizontal sync detection circuit.

Claims (3)

[Claims] 1. A vertical deflection circuit for generating a vertical drive pulse using a vertical sync signal obtained from a sync separation circuit, the sensitivity for generating a drive pulse according to a reset signal and controlling the sensitivity of the sync separation circuit. A vertical counter that generates a control signal, a reset signal selection circuit that generates a reset signal that switches the vertical counter to a self-reset operation or an external reset operation, and a reset signal that detects the absence of a vertical synchronization signal that comes from the outside. A no-signal detection circuit that controls the selection circuit to make the vertical counter perform a self-reset operation, and a detection unit that detects arrival of a video signal from the outside are provided, and the no-signal detection circuit is in a self-reset operation state. The vertical counter is switched to an external reset operation according to the output signal of the detection means. A vertical deflection circuit, characterized in that. 2. The vertical counter includes a first frequency-divided output signal which is the sensitivity control signal, and a third frequency-divided output signal which has a normal vertical period and is used for a self-reset operation.
A second frequency division output signal having a frequency lower than that of the third frequency division output signal is generated, and the reset signal selection circuit generates one of the vertical synchronization signal obtained from the synchronization separation circuit and the second frequency division output signal. An OR gate to be selected, an output signal of the OR gate, and the third signal
2. The vertical deflection circuit according to claim 1, comprising a switch for selecting one of the divided output signal. 3. The detecting means compares the phase of the horizontal synchronizing signal from the outside with the output signal of the horizontal deflection circuit and detects the arrival of the video signal from the outside according to the difference. The vertical deflection circuit according to claim 1 or 2.