JPH07114471B2 - Solid-state imaging device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a solid-state imaging device, and more particularly to a CCD (Charge Comp
The present invention relates to a solid-state imaging device that reads out a video signal from a led device) or a CPD (Charge Priming Device).

[Background of the Invention]

As shown in FIG. 1, the operation principle of a conventional CCD type solid-state image pickup device is as follows: a photosensitive unit 1 composed of photo diodes 2 arranged in a matrix, and a vertical direction for reading an optical signal accumulated in the photo diode 2 through a FET 5. , 1N in the horizontal direction, a CCD group 3 in the horizontal direction, and an amplifier 4 for amplifying and outputting the charge amount signal from the CCD group 3. Note that φ
_H1 , φ _H2 , φ _{Vo to} φ _V2 are clock pulses for signal transfer.

The amplifier 4 and its surroundings are components mounted on the circuit configuration and the image pickup device chip as shown in FIG. 8 is a small electrostatic capacitance (Co) for converting the charge amount Q _S which is the output signal of the CCD group 3 into a voltage amount, and 21 is the charge amount Q _S and the voltage V ₀ ( = Q _S / C ₀ ) low-impedance source-follower MOS-type FET, 22
Is a MOS type FET for releasing and resetting the electric charge Q _S of the electrostatic capacitance 8 to the outside, 7 is a chip of the image pickup device, 23 and 23 'are terminals on the chip (pads for wire bonding), 6
Is a package, 24 and 24 'are pin terminals of the package, 25 is an external wiring, 9 is a parasitic capacitance of the external wiring 25, 10 is a signal processing unit, and 26 is a pull-down resistor.

A case where the video signal is read in FIGS. 1 and 2 will be described with reference to FIG.

The charges accumulated in each of the photodiodes 2 in one frame period are transferred to the CCD groups 11, 12 ... 1N during the vertical blanking period by the clock pulses φ _{V0 to} φ _V2 , and then during the horizontal blanking period. Are transferred to CCD group 3 while transferring line by line. The charges transferred to the CCD group 3 are sequentially transferred to the electrostatic capacitance 8 by the clock pulse φ _{H2 as} shown in FIG.
When the reset signal φ _R is added, the output voltage V ₀ (= Q _S /
C ₀ ).

The charge Q _S ^(l) transferred to the electrostatic capacitance 8 by the l-th clock pulse of φ _H2 generates a voltage V ₀ ^(l) at both ends of the electrostatic capacitance 8 and then is reset by the reset signal φ _R. Is released to. In addition, Vo ^(l) above is connected to the pin terminal 2 through FET21, terminal 23 '.
Output from 4 '. The charge Q _S ^{(l + 1)} transferred to the electrostatic capacitance 8 by the next (l + 1) th clock pulse after φ _H2 is also V
Outputs ₀ ^{(l + 1)} . The charges transferred by the clock pulse φ _{H2 in} this way become a hold pulse train of a voltage proportional to the charges, and are passed through the external wiring 25 to the signal processing unit.
Sent to 10. Further, the modulation component is taken out by the low-pass filter in the signal processing unit 10 and becomes a video signal.

In the above operation, the smaller the electrostatic capacitance 8 of the amplifier 4 is, the larger voltage (V ₀ = Q _S / C ₀ ) is obtained. Therefore, the gate of the FET 21 that constitutes the main component of the electrostatic capacitance 8 is obtained. Make the area as small as possible. However, when the area is made small, the output impedance (R) of the source follower becomes as large as several tens of kΩ or more, so that the RC circuit configured with the parasitic capacitance 9 (C) causes a problem of deterioration of the signal frequency band. In order to solve this problem, it is sufficient to reduce the influence of the parasitic capacitance 9. Therefore, conventionally, as shown in FIG. 4, a transistor (or J-FET) is provided at the pin end 24 'of the package 6 for housing the fixed image pickup device. By adding an emitter follower (or source follower) composed of a single unit 31 in close proximity, a low output impedance is achieved and the effect of the parasitic capacitance 9 is reduced. Further, in order to eliminate the influence of the parasitic capacitance 32 generated in the pin or socket of the image pickup device or the single transistor, a method of incorporating two stages of source followers by the MOS type FET 33 in the chip 7 of the image pickup device to obtain a low output impedance is used. (For example, SONY new product bulletin ICX016AK
Refer to "CCD image sensor").

However, i) The capacitance of the parasitic capacitance 32 is as large as several pF to several tens of pF, and it is not possible to reduce the output impedance to several KΩ or less.
Due to the difficulty of the performance of the MOS FET, the signal frequency band is 10 MHz.
It becomes narrower. It should be noted that the current 40
When 0 pixels are lined up, the frequency band is 14 MHz, and when 800 pixels are lined up in the future, 28 MHz band is required.
This is an important issue. ii) MOS type FET requires a large bias current, resulting in high power consumption.
As a result, dark current white spots are generated due to heat generation. ii
i) Since the number of circuit mounting parts other than packages increases, the production cost of the image camera is increased and the reliability is reduced.
iv) Induced noise generated from element driving pulse signals leaks from the parasitic capacitance to the signal, and the S / N ratio decreases.
There are problems such as.

[Object of the Invention]

An object of the present invention is to solve such a conventional problem and to provide a solid-state imaging device capable of obtaining a wide-angle video signal with low power consumption by a simple and inexpensive method without mounting any external parts. To provide.

[Outline of Invention]

In order to achieve the above object, the fixed image pickup device of the present invention sequentially accumulates continuous pulsed signal charges in the electrostatic capacitance of the amplifier input terminal, amplifies the signal voltage generated between the electrostatic capacitance terminals, and outputs the amplified signal voltage. In a solid-state imaging device having an amplifier and a package in which the amplifier is mounted in a chip shape, a chip of an integrated circuit composed of a single transistor or a plurality of transistors or J-FETs is provided in the package at a position close to the amplifier. It is characterized by being implemented in.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram of a solid-state imaging device showing an embodiment of the present invention.

In FIG. 5, 41 is a transistor (or J-FE).
T) It is a single chip and is different from FIG. 4 showing the configuration of the conventional solid-state image pickup device in that the above-mentioned chip 41 is mounted in the package 6 in the vicinity of the source follower output terminal 23 ′ of the amplifier 4. . When mounting the chip 41 in the same package 6, the base of the chip 41 (or J-FE
When T, the distance between the gate terminal (pad) 42 and the output terminal (pad) 23 'of the source follower is set as close as possible in order to reduce the parasitic capacitance generated therebetween. Also, work such as wire bonding for connecting between the chips 41 or between the chip 41 and the package terminal 24 'is easy, and in order to prevent contact between the lead wires, in the case of a collector or an emitter (or J-FET, , The drain or source) and the lead wires 43, 43 'do not intersect.

By mounting the chip 41 as described above, the load capacitance of the source follower of the amplifier 4 (parasitic capacitance generated in the base of the transistor, which is the parasitic capacitance 32 in FIG. 4) can be ignored, so that the output impedance of the source follower is reduced. Even if the value is several tens of KΩ, a signal with a wide frequency band can be obtained. Also, by mounting the single transistor in the same package as the chip of the image pickup device, the number of circuit mounting parts of the image camera is reduced, and the manufacturing cost can be reduced.

Furthermore, since the parasitic capacitance that affects the frequency band of the signal is so small that it can be ignored, a large bias current for lowering the output impedance of the source follower can be reduced, so that the power consumption can be reduced.

Although the source follower of the amplifier 4 has a single stage as shown in FIG. 5, it has been described as an example, but the same effect can be obtained in the case of two stages as shown in FIG. .

〔The invention's effect〕

As described above, according to the present invention, a buffer component such as a transistor is mounted in the same package as the chip of the image sensor by a simple and inexpensive method, so that a wideband video signal with low power consumption can be obtained. can get.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the operation principle of the CCD type solid-state imaging device,
FIG. 2 is a circuit diagram of an amplifier and its periphery, FIG. 3 is an operation time chart of FIG. 2, FIG. 4 is a block diagram of a conventional fixed image pickup device, and FIG. 5 is an embodiment of the present invention. It is a block diagram of a fixed imaging device. 1 ... Photosensitive area, 2 ... Photodiode, 3,11,12 ... IN: CC
D group, 4 ... Amplifier, 5,21,22,23 ... FET, 6 ... Package, 7 ... Chip of image sensor, 8 ... Capacitance, 9,32
...... Parasitic capacitance, 10 ...... Signal processing part, 23,23 ', 42 ...... Terminal (pad), 24,24' ...... Pin terminal, 25 ...... External wiring, 2
6 …… pull-down resistor, 41 …… transistor chip, 43,
43 ′ …… Lead wire.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takeshi Ogino 1410 Inada, Katsuta City, Ibaraki Prefecture, Tokai Plant, Hitachi, Ltd. (56) References JP-A-56-116373 (JP, A) JP-A-58- 220574 (JP, A)

Claims (1)

[Claims] 1. An electrostatic capacitance for sequentially accumulating continuous pulsed signal charges and an amplifier for sequentially amplifying and outputting a signal voltage generated between the electrostatic capacitance terminals are mounted in a chip form. In a solid-state imaging device having a package, a single transistor or a chip having a J-FET mounted thereon is mounted on the package at a position close to the amplifier mounted on the chip mounted in the package. A solid-state imaging device, wherein lead wires for connecting a plurality of output terminals of an amplifier and a plurality of input terminals of a chip on which the single transistor or J-FET is mounted are connected so as not to cross each other. .