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JPH0711640B2 - Active matrix substrate - Google Patents
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JPH0711640B2 - Active matrix substrate - Google Patents

Active matrix substrate

Info

Publication number
JPH0711640B2
JPH0711640B2 JP16943788A JP16943788A JPH0711640B2 JP H0711640 B2 JPH0711640 B2 JP H0711640B2 JP 16943788 A JP16943788 A JP 16943788A JP 16943788 A JP16943788 A JP 16943788A JP H0711640 B2 JPH0711640 B2 JP H0711640B2
Authority
JP
Japan
Prior art keywords
active matrix
signal line
metal film
signal lines
matrix substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16943788A
Other languages
Japanese (ja)
Other versions
JPH0219839A (en
Inventor
均 野田
博司 高原
守 竹田
一郎 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16943788A priority Critical patent/JPH0711640B2/en
Publication of JPH0219839A publication Critical patent/JPH0219839A/en
Publication of JPH0711640B2 publication Critical patent/JPH0711640B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306Details
    • G02F1/1309Repairing; Testing
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136204Arrangements to prevent high voltage or static electricity failures
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136254Checking; Testing

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、液晶表示パネルに用いられるアクティブマト
リックス基板に関するものである。
Description: TECHNICAL FIELD The present invention relates to an active matrix substrate used for a liquid crystal display panel.

従来の技術 近年、産業機器の小型化にともない従来からの表示装置
に代わる薄型平面表示装置が要望されている。種々ある
平面表示装置の中で液晶を用いた表示装置は、消費電力
が少なく、フルカラー表示が容易である点などから注目
されている。特に、表示画素の一つ一つにスイッチング
素子を設けたアクティブマトリックス型液晶表示パネル
は表示画質が優れているため携帯用のテレビなどに応用
されている。
2. Description of the Related Art In recent years, with the miniaturization of industrial equipment, there has been a demand for a thin flat display device that replaces a conventional display device. Among various types of flat panel display devices, a display device using liquid crystal is drawing attention because it consumes less power and is easy to perform full-color display. In particular, an active matrix type liquid crystal display panel in which a switching element is provided in each of the display pixels has excellent display image quality and is therefore applied to portable televisions and the like.

第4図は従来のアクティブマトリックス基板の構成を示
す等価回路図である。第4図において、51は薄膜トラン
ジスタ、52は信号線をショート状態にするための金属膜
パターン、X1〜Xmは走査信号線、Y1〜Ynは映像信号線で
ある。ところが、アクティブマトリックス基板では、基
板の製造工程中に基板に帯電する静電気によってスイッ
チング素子や走査信号線と映像信号線の交差部分の絶縁
膜が破壊され、ショート状態になってしまうという問題
点があった。この静電気による絶縁膜の破壊防止対策と
して、従来では第4図に示すようにアクティブマトリッ
クス基板の全ての端子を金属膜パターン52でショートし
ておく方法が用いられていた。また、特開昭61−48978
号公報に見られるようにアクティブマトリックス基板の
走査信号線と映像信号線の片側だけをショートする方法
も提案されている。第5図にこの方法によるアクティブ
マトリックス基板の構成図を示す。
FIG. 4 is an equivalent circuit diagram showing a configuration of a conventional active matrix substrate. In FIG. 4, 51 is a thin film transistor, 52 is a metal film pattern for making signal lines short-circuited, X1 to Xm are scanning signal lines, and Y1 to Yn are video signal lines. However, the active matrix substrate has a problem in that the static electricity charged on the substrate during the substrate manufacturing process destroys the insulating film at the intersections of the switching elements and the scanning signal lines and the video signal lines, resulting in a short circuit. It was As a measure for preventing the breakdown of the insulating film due to this static electricity, conventionally, as shown in FIG. 4, a method of short-circuiting all the terminals of the active matrix substrate with the metal film pattern 52 has been used. In addition, JP-A-61-48978
As disclosed in Japanese Patent Laid-Open Publication No. 2003-242242, a method of short-circuiting only one side of the scanning signal line and the video signal line of the active matrix substrate has been proposed. FIG. 5 shows a block diagram of an active matrix substrate by this method.

発明が解決しようとする課題 しかしながら、第4図に示したような従来の静電気によ
る絶縁膜の破壊防止方法では、全ての端子がショートさ
れているためアクティブマトリックス基板の完成後、シ
ョート部分を切断するまで信号線の断線による断線欠
陥、隣合う走査信号線どうしや映像信号線どうしのショ
ート欠陥、走査信号線と映像信号線のショートといった
ショート欠陥を検査することはできなかった。また、第
5図に示す特開昭61−48978号公報による方法では断線
欠陥の検査は行えるものの、やはり信号線のショート部
分を切断するまでは基板のショート欠陥の検査は行えな
かった。
However, in the conventional method for preventing the breakdown of the insulating film due to static electricity as shown in FIG. 4, since all the terminals are short-circuited, the short-circuited portion is cut after the completion of the active matrix substrate. Up to now, it has not been possible to inspect for short-circuit defects such as disconnection defects due to disconnection of signal lines, short-circuit defects between adjacent scanning signal lines or video signal lines, and short circuits between scanning signal lines and video signal lines. In addition, although the method according to Japanese Patent Laid-Open No. 61-48978 shown in FIG. 5 can inspect for a disconnection defect, the inspection of a substrate for a short circuit defect cannot be performed until the short portion of the signal line is cut.

本発明はかかる点に鑑みてなされたもので、静電気によ
る絶縁膜の破壊を防止し、欠陥検査が行えるアクティブ
マトリックス基板を提供することを目的としている。
The present invention has been made in view of the above points, and an object thereof is to provide an active matrix substrate capable of preventing damage to an insulating film due to static electricity and performing defect inspection.

課題を解決するための手段 本発明は上記した問題点を解決するために、アクティブ
マトリックス基板のスイッチング素子の走査信号線、映
像信号線を1本おきに複数本ずつガラス基板上に生成し
た金属膜で接続し、かつ、信号線の入力端子の外側に形
成した共通電極パターンと複数本ずつ接続した信号線群
をコンデンサで接続するように構成したものである。
Means for Solving the Problems In order to solve the above-described problems, the present invention provides a metal film formed on a glass substrate by a plurality of scanning signal lines and video signal lines of switching elements of an active matrix substrate. And the common electrode pattern formed outside the input terminal of the signal line and a plurality of signal line groups connected to each other are connected by a capacitor.

作用 本発明は上記した構成により、アクティブマトリックス
基板における静電気による絶縁膜の破壊を防止すると共
に、信号線の断線欠陥検査と複数本ずつ接続した走査信
号線群と映像信号線群間のショート欠陥検査を行うこと
を可能とする。
Effect of the Invention The present invention has the above-described configuration to prevent the breakdown of the insulating film due to static electricity in the active matrix substrate, and also to perform a disconnection defect inspection of the signal lines and a short defect inspection between the scanning signal line group and the video signal line group connected by a plurality of lines. It is possible to do.

実施例 以下、本発明の一実施例のアクティブマトリックス基板
について図面を参照しながら説明する。
Example Hereinafter, an active matrix substrate of an example of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例におけるアクティブマトリッ
クス基板の構成図である。第1図において1は薄膜トラ
ンジスタ、2は走査信号線および映像信号線の入力端
子、3は走査信号線および映像信号線を複数本ずつショ
ートするための金属膜パターン、4は信号線の入力端子
の外側に共通電極として金属膜で形成した共通電極パタ
ーン、5は信号線を複数本ずつショートさせた金属膜パ
ターン3と共通電極パターン4を接続するコンデンサ、
X1〜Xmは走査信号線、Y1〜Ynは映像信号線である。本実
施例では第1図に示すように走査信号線と映像信号線は
1本おきに金属膜パターン3に接続し、コンデンサ5を
介して共通電極パターン4に接続されている。
FIG. 1 is a block diagram of an active matrix substrate in one embodiment of the present invention. In FIG. 1, 1 is a thin film transistor, 2 is an input terminal for scanning signal lines and video signal lines, 3 is a metal film pattern for short-circuiting a plurality of scanning signal lines and video signal lines, and 4 is an input terminal for signal lines. A common electrode pattern 5 formed of a metal film as a common electrode on the outside is a capacitor for connecting the metal film pattern 3 and the common electrode pattern 4 in which a plurality of signal lines are short-circuited,
X1 to Xm are scanning signal lines, and Y1 to Yn are video signal lines. In this embodiment, as shown in FIG. 1, every other scanning signal line and video signal line is connected to the metal film pattern 3 and is connected to the common electrode pattern 4 via the capacitor 5.

第2図は金属膜パターン2と共通電極金属膜パターン3
を第1図のA部の構造図であり、第3図は第2図のa−
a′部における略断面図である。第2図、第3図で本実
施例の構造を説明する。信号線の入力端子2をガラス基
板10上に形成するときに同時に信号線をショートさせる
金属膜パターン3も形成しておく。次にスイッチング素
子を形成するときに同時に金属膜パターン3上に絶縁膜
11を形成する。そして、最後に共通電極パターン4を信
号線の補強膜とする金属膜12を形成するときに同時に形
成する。このように構成することでフォトマスクの枚数
を増やすことなく静電気による絶縁膜破壊の防止対策を
行うことができる。また、第2図のb部で示す信号線と
金属膜パターン3の接続部分は検査終了後切断しやすい
ように補強金属膜12を形成していない。
FIG. 2 shows a metal film pattern 2 and a common electrode metal film pattern 3
FIG. 3 is a structural diagram of part A in FIG. 1, and FIG. 3 is a- in FIG.
It is a schematic sectional drawing in a'part. The structure of this embodiment will be described with reference to FIGS. At the same time when the signal line input terminal 2 is formed on the glass substrate 10, a metal film pattern 3 for short-circuiting the signal line is also formed. When the switching element is formed next, an insulating film is formed on the metal film pattern 3 at the same time.
Forming 11. Finally, the common electrode pattern 4 is formed at the same time when the metal film 12 that uses the signal line reinforcing film is formed. With this configuration, it is possible to take measures to prevent the breakdown of the insulating film due to static electricity without increasing the number of photomasks. The connecting portion between the signal line and the metal film pattern 3 shown in part b of FIG. 2 is not formed with the reinforcing metal film 12 so as to be easily cut after the inspection.

次に本実施例による欠陥検査方法について説明する。信
号線の断線検査は、走査信号線、映像信号線とも片側の
端子は接続されていないので、金属膜パターン3と入力
端子2プローブ針を接続し、抵抗値を測定することで検
査することができる。隣合う信号線どうしのショート欠
陥検査は信号線が1本おきに金属膜パターン3に接続さ
れているため金属膜パターン3にプローブ針を接続し、
抵抗値を測定することで当該ブロックの中でのショート
欠陥検査を行うことができる。また走査信号線と映像信
号線間のショート欠陥検査は、各々の金属膜パターン3
はコンデンサ5を介して接続しているので電気的に絶縁
されており走査信号線側の金属膜パターンと映像信号線
側の金属膜パターンにプローブ針を接続し、抵抗値を測
定することで当該ブロックの中でのショート欠陥検査を
行うことができる。
Next, the defect inspection method according to this embodiment will be described. The signal line disconnection inspection can be performed by connecting the metal film pattern 3 to the input terminal 2 probe needle and measuring the resistance value, because neither the scanning signal line nor the video signal line is connected to one terminal. it can. For short-circuit defect inspection between adjacent signal lines, every other signal line is connected to the metal film pattern 3, so a probe needle is connected to the metal film pattern 3.
By measuring the resistance value, it is possible to perform a short defect inspection in the block. The short defect inspection between the scanning signal line and the video signal line is performed for each metal film pattern 3
Are electrically insulated from each other because they are connected via a capacitor 5, and a probe needle is connected to the metal film pattern on the scanning signal line side and the metal film pattern on the video signal line side to measure the resistance value. It is possible to perform a short defect inspection in a block.

発明の効果 以上の説明のように本発明は、アクティブマトリックス
基板のスイッチング素子の信号線を一本おきに複数本ず
つガラス基板上に生成した金属膜で接続し、かつ、信号
線の入力端子の外側に形成した金属膜のパターンと前記
複数本ずつ接続した信号線群をコンデンサで接続するこ
とで、静電気による絶縁膜破壊の保護を行うと共に、走
査信号線、映像信号線の断線欠陥検査やショート欠陥検
査を行うことが可能であるというすぐれた効果を有す
る。
EFFECTS OF THE INVENTION As described above, according to the present invention, the signal lines of the switching elements of the active matrix substrate are connected to each other by a plurality of metal films formed on the glass substrate, and the input terminals of the signal lines are connected. The metal film pattern formed on the outside and the signal line group connected to each of the above multiple lines are connected by a capacitor to protect the insulation film from being destroyed by static electricity, and to inspect for disconnection defects of the scanning signal line and the video signal line and short-circuit. It has an excellent effect that defect inspection can be performed.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例におけるアクティブマトリッ
クス基板の構成図、第2図は第1図のA部の構造図、第
3図は第2図のa−a′部における略断面図、第4図、
第5図は従来のアクティブマトリックス基板の構成を示
す構成図である。 1……薄膜トランジスタ、2……入力端子、3……金属
膜パターン、4……共通電極パターン、5……コンデン
サ、X1〜Xm……走査信号線、Y1〜Yn……映像信号線。
FIG. 1 is a configuration diagram of an active matrix substrate in one embodiment of the present invention, FIG. 2 is a structural diagram of a portion A in FIG. 1, and FIG. 3 is a schematic cross-sectional view in aa 'portion in FIG. Figure 4,
FIG. 5 is a configuration diagram showing a configuration of a conventional active matrix substrate. 1 ... Thin film transistor, 2 ... Input terminal, 3 ... Metal film pattern, 4 ... Common electrode pattern, 5 ... Capacitor, X1 to Xm ... Scan signal line, Y1 to Yn ... Video signal line.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 山下 一郎 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (56)参考文献 特開 昭59−91479(JP,A) 特開 昭62−297820(JP,A) 特開 昭63−292113(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ichiro Yamashita 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP 59-91479 (JP, A) JP 62-297820 (JP, A) JP-A-63-292113 (JP, A)

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】ガラス基板上にスイッチング素子をマトリ
ックス状に配置したアクティブマトリックス基板であっ
て、前記スイッチング素子の信号線を1本おきに複数本
ずつ前記ガラス基板上に生成した金属膜で接続し、か
つ、前記信号線の入力端子の外側に形成した金属膜のパ
ターンと前記複数本ずつ接続した信号線群をコンデンサ
で接続したことを特徴とするアクティブマトリックス基
板。
1. An active matrix substrate in which switching elements are arranged in a matrix on a glass substrate, and a plurality of every other signal lines of the switching elements are connected by a metal film formed on the glass substrate. An active matrix substrate, wherein a pattern of a metal film formed outside the input terminal of the signal line and a group of signal lines connected to each of the plurality of signal lines are connected by a capacitor.
【請求項2】信号線の入力端子の外側に形成した金属膜
のパターンは、前記信号線のパターン幅より十分太くし
て共通電極としたことを特徴とする請求項(1)記載の
アクティブマトリックス基板。
2. The active matrix according to claim 1, wherein the pattern of the metal film formed outside the input terminal of the signal line is made sufficiently thicker than the pattern width of the signal line to form a common electrode. substrate.
【請求項3】スイッチング素子が二端子素子、あるい
は、薄膜トランジスタで構成されていることを特徴とす
る請求項(1)記載のアクティブマトリックス基板。
3. The active matrix substrate according to claim 1, wherein the switching element is a two-terminal element or a thin film transistor.
JP16943788A 1988-07-07 1988-07-07 Active matrix substrate Expired - Fee Related JPH0711640B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16943788A JPH0711640B2 (en) 1988-07-07 1988-07-07 Active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16943788A JPH0711640B2 (en) 1988-07-07 1988-07-07 Active matrix substrate

Publications (2)

Publication Number Publication Date
JPH0219839A JPH0219839A (en) 1990-01-23
JPH0711640B2 true JPH0711640B2 (en) 1995-02-08

Family

ID=15886587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16943788A Expired - Fee Related JPH0711640B2 (en) 1988-07-07 1988-07-07 Active matrix substrate

Country Status (1)

Country Link
JP (1) JPH0711640B2 (en)

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* Cited by examiner, † Cited by third party
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JP2937029B2 (en) * 1994-09-08 1999-08-23 ヤマハ株式会社 Tone generator
DE69840523D1 (en) * 1997-01-13 2009-03-19 Hyundai Electronics America IMPROVED PROTECTION FOR ACTIVE-MATRIX INDICATORS FOR ELECTROSTATIC DISCHARGES AND TESCHEMA
JP2006267545A (en) * 2005-03-24 2006-10-05 Sanyo Epson Imaging Devices Corp Electrooptical apparatus and electronic equipment
JP5738995B2 (en) * 2011-07-19 2015-06-24 シャープ株式会社 Method for manufacturing element substrate

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