JPH0711785B2 - Evaluation device and evaluation method for semiconductor device incorporating MPU - Google Patents

Description

TECHNICAL FIELD The present invention relates to an apparatus and method for evaluating an LSI having a built-in MPU (microprocessor) such as a one-chip microcomputer manufactured by an MPU core built-in LSI or a custom LSI. Is.

(Prior Art) With the increase in the degree of integration of LSIs, the entire system, which was conventionally composed of several chips, is being integrated into one chip LSI. For example, if a microcomputer system consisting of MPU, ROM, RAM, peripheral logic circuits, etc. is realized by a single-chip LSI, the address bus,
The data bus etc. may not be taken out to the outside. It becomes very difficult to evaluate such a one-chip microcomputer LSI in an actual use state.

Even in such an LSI, it is necessary to externally observe the address bus and the data bus in some way in the development stage in order to trace the execution state of the MPU.

Therefore, one possible method is to develop an variation chip that cuts out and outputs the address bus and data bus to the outside, but not only is it costly to newly develop the LSI, but for example, in an 8-bit CPU system. Generally, it is very uneconomical because the number of pins is increased by 16 addresses and 8 data buses, totaling 24 pins.

(Purpose) The present invention enables the evaluation of a one-chip semiconductor device containing an MPU in an actual use state without increasing the number of pins even if the address bus and the data bus are not output to the outside. It is an object of the present invention to provide an apparatus and method for doing the above.

(Structure) The present invention is an apparatus and method for evaluating a semiconductor device using a reference clock and an instruction signal.

The evaluation device of the present invention is a breadboard device having a circuit equivalent to the semiconductor device to be evaluated which has a built-in MPU and capable of extracting at least an instruction signal and an address signal to the outside, and is output from the semiconductor device to be evaluated. A mismatch circuit that detects a mismatch between the instruction signal and the instruction signal output from the breadboard, a synchronous clock generation circuit that supplies the same clock signal to the semiconductor device to be evaluated and the breadboard device, and the mismatch circuit are both A system pause circuit for stopping the generation of the clock signal of the synchronous clock generation circuit upon receiving the output signal of the mismatch circuit when the mismatch of the instruction signal is detected.

The evaluation method of the present invention, a semiconductor device under development with a built-in MPU and a breadboard device that has a circuit equivalent to this semiconductor device and performs a normal operation are operated in synchronization, and the instruction signal of the semiconductor device and the The method is characterized by comparing with an instruction signal of a breadboard device.

Here, the "instruction signal" is a signal whose period changes due to an instruction. Although the name of this instruction signal differs depending on the model, for example, a SYNC signal, a LiC signal, or a ▲ ▼ signal corresponds to this instruction signal.

Examples will be specifically described below.

FIG. 1 shows an example of an evaluation device for carrying out the present invention.

Reference numeral 2 is a 1-chip microcomputer LSI under development, which has the configuration shown in FIG. The instruction signal output terminal of LSI2 is Exclusive NOR (hereinafter, EX
(Referred to as NOR) is connected to one input side of the circuit 10, and the reference clock output terminal is connected to the synchronous clock generator 12.

FIG. 2 shows an example of SLI2.

14 is MPU, 16 is ROM storing programs, 18 is RA
M and 20 are peripheral logic circuits, 22 is an address bus, and 24 is a data bus. The reference clock and the instruction signal are taken out from the MPU 14 via the I / O circuit 26 by using the empty pin in the actual use state.

The SYNC signal as an example of the instruction signal represents an instruction fetch cycle, and is output as shown in FIG. 3, for example. When the instruction is classified, it is classified into 2 to 7 cycles in synchronization with the SYNC signal.

Referring back to FIG. 1 again, 4 is a breadboard device, which has the same specifications as the SLI2, including MPU6, which has the same specifications as the MPU built into SLI2, RAM, ROM, and peripheral logic circuits. Is provided. The instruction signal is taken out from the MPU6 and the address and data can be observed by the external terminal. The instruction signal output terminal of MPU6 is connected to the other input side of the EX NOR circuit 10.

In general, the breadboard device 4 having the same specifications as the SLI2 is prototyped at the stage of designing the circuit of the SLI2 for the purpose of confirming normal operation.

A system pause circuit 8 receives an instruction signal from the SLI 2 and an instruction signal from the MPU 6 of the breadboard device via the EX NOR circuit 10. The system pause circuit 8 generates a pause signal when both instruction signals do not match. The pause signal output terminal is connected to the input terminal of the synchronous clock generating circuit 12.

The synchronous clock generation circuit 12 inputs the reference clock from the SLI2 to generate a clock signal, and stops the generation of the clock signal when the pause signal from the system pause circuit 8 is input. The synchronous clock generating circuit 12 may also be of a type in which a clock signal is generated by an oscillating circuit without inputting a reference clock from SLI2, as shown in FIG. The synchronous clock output terminal is connected to the clock input terminal of SLI2 and the clock input terminal of MPU6 of the breadboard device 4.

FIG. 4 shows an example of the system pause circuit 8 and the synchronous clock generating circuit 12 in FIG. However, in this example, the synchronous clock generating circuit 12 does not input the reference clock from the SLI2, and the oscillator circuit generates the clock signal.

This circuit consists of two monostable multivibrators 30, 32,
It is provided with two NAND gates 34 and 36 and an output buffer circuit 38. The output from the EX NOR circuit 10 is input to the input terminal. The reset terminals R of the monostable multivibrators 30, 32 function as the system pause circuit 8. Also, NAND gates 34 and 36 and monostable multivibrator 30 and 32
An oscillator circuit as the synchronous clock generating circuit 12 is constituted by the above. The generated clock signal is connected to the monostable multivibrator 30, 32 and capacitors C ₁ , C ₂ and resistance
It is determined by R ₁ and R ₂ as shown in FIG.

In the circuit of FIG. 4, as shown in FIG. 5, when the signal input from the EX NOR circuit 10 is at a high level, the oscillator circuit operates and a clock signal is generated.
When the signal input from the OR circuit 10 becomes low level, the operation of the oscillation circuit stops and the clock signal is not generated.

The oscillator circuit is not limited to that shown in FIG.

Next, the operation of this embodiment will be described.

SLI2 by the synchronous clock from the synchronous clock generation circuit 12
And the breadboard device 4 are operated in synchronism, the respective MPUs 14, 6 execute the programs sent from the respective ROMs and generate instruction signals unique to the programs.

If SLI2 is normal, the instruction signals from both MPUs 14 and 6 match, the output of the EX NOM circuit 10 becomes high level, and the clock signal continues to be output from the synchronous clock generation circuit 12.

If there is an error in SLI2, there will be a mismatch in both instruction signals during the program. At this time, EX N
Since the output of the OR circuit 10 becomes low level and the generation of the clock signal from the synchronous clock generation circuit 12 is stopped, the runaway of the SLI2 is programmed by observing the address and data of the breadboard device 4 side at that time. You can easily determine where it happened.

In the SLI2 used in this embodiment, only two pins for the reference clock and the instruction signal are added for evaluation at the maximum. This is extremely small compared to the increase in the number of pins for fetching addresses and data. Further, the reference clock and the instruction signal may be used in actual use.

SLI2 in Fig. 2 is the system pause circuit 8, EX for evaluation.
The NOR circuit 10 and the synchronous clock generation circuit 12 are not included. However, these evaluation circuits can be formed in the same chip as the microcomputer. In that case, the operation for evaluation becomes easier.

Further, by providing a single step circuit in the SLI chip and adding a single step pin, it becomes possible to compare the operation of each step with a breadboard device.

(Effects) According to the present invention, it is possible to monitor the operating state of the MPU in the actual use state even in the configuration in which the address bus and the data bus are not taken out to the outside by the SLI with built-in MPU.

Also, because the comparison is performed using a breadboard device,
You can easily and quickly determine the runaway address of the development SLI. On the other hand, if a human observes the instruction signal using a device such as an oscilloscope or a logic analyzer and tries to monitor whether the development SLI MPU is operating correctly according to the program,
It is very inefficient and makes many mistakes.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an evaluation device for implementing the present invention, FIG. 2 is a block diagram showing an example of a one-chip SLI evaluated in the same embodiment, and FIG. 3 is a reference clock and an instruction signal. FIG. 4 is a waveform diagram showing the SYNC signal, FIG. 4 is a block circuit diagram showing an example of the system pause circuit and the synchronous clock generation circuit in one embodiment, and FIG. 5 is a waveform diagram showing the operation of FIG. 2 ... SLI under development, 4 ... Breadboard device, 6,14 ... MPU, 8 ... System pause circuit, 10 ... EX NOR circuit, 12 ... Synchronous clock generation circuit.

Claims (2)

[Claims] 1. A breadboard device having a circuit equivalent to a semiconductor device to be evaluated, which incorporates an MPU, and capable of extracting at least an instruction signal and an address signal to the outside, and an instruction signal output from the semiconductor device to be evaluated. And a mismatch circuit for detecting a mismatch between the instruction signal output from the breadboard, a synchronous clock generation circuit that supplies the same clock signal to the semiconductor device to be evaluated and the breadboard device, and the mismatch circuit is both instruction signals. And a system pause circuit for stopping the generation of the clock signal of the synchronous clock generation circuit when receiving the output signal of the non-coincidence circuit when the non-coincidence is detected. 2. A semiconductor device having a built-in MPU and a breadboard device having a circuit equivalent to this semiconductor device and performing a normal operation are operated in synchronization with each other, and an instruction signal of the semiconductor device and an instruction of the breadboard device are operated. A method for evaluating a semiconductor device, which comprises comparing with a signal.