JPH07117915B2 - Cache memory system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system which is located between a main memory and a processor and adjusts the time difference between the access time of the main memory and the cycle time of the processor.

[0002]

2. Description of the Related Art In recent years, cache memory systems have begun to be introduced in systems equipped with a microprocessor (MPU). MP with built-in cache memory
U is a static RAM whose cache memory is
Some of them are composed of (hereinafter referred to as “SRAM”) and some are composed of dynamic RAM (hereinafter referred to as “DRAM”).

Typical examples of the SRAM are a CMOS 6Tr (transistor) type as shown in FIG. 14 and an E / R type as shown in FIG.

The CMOS 6Tr type cell is a flip-flop circuit in which two inverter circuits 1 each composed of a MOS are stacked and connected, and a connection / separation between this flip-flop circuit and a data line (bit line) is performed. -It is composed of two transfer gates 3 that operate according to the potential of the ground line.

The E / R type cell is an enhancement type cell 2.
It is composed of a flip-flop circuit composed of N-channel MOS type FETs (hereinafter referred to as "NMOS") 5 and a resistor 7 serving as a load of the NMOS 5, and two transfer gates 3. In this E / R type cell, the resistor 7 is formed of polysilicon having a high specific resistance and the area occupied by the resistor 7 is made small. Therefore, the static type cell has high integration and high speed. Suitable for

On the other hand, the DRAM has a typical 4Tr (transistor) type shown in FIG.
The 1Tr (transistor) capacitance type shown in FIG.

The 4Tr type cell has a configuration in which the resistors 7 of the E / R type cell shown in FIG. 15 are removed. In such a configuration, since the two data lines are used complementarily, it is possible to operate at a relatively high speed.

The 1Tr capacitance type cell is constructed by connecting a storage capacitor 9 and a transfer gate 3 in series, and is connected to one data line. Therefore, this 1Tr capacitance type cell is composed of minimum necessary elements and signal lines, and is most suitable for high integration.

Such cells correspond to SRs, respectively.
It is used in AM and DRAM, and the characteristics of the respective cells are compared as shown in FIG.

Referring to FIG. 18, a 6Tr type SRAM
Has a significantly larger occupied area than the E / R type SRAM. Therefore, it is not suitable for a large capacity memory.
Therefore, hereinafter, the SRAM refers to an E / R type SRAM.

The 4Tr DRAM has a simple manufacturing process and a small access time, and its occupied area is almost the same as that of the E / R type SRAM. However, the dynamic type requires a refresh operation. For this reason, the system configuration becomes complicated and is difficult to use as compared with the E / R type SRAM. Further, the occupied area is larger than that of the 1Tr DRAM which similarly requires the refresh operation, which is disadvantageous for high integration. Therefore, the DRAM is hereinafter referred to as a 1Tr type DRAM.

On the other hand, comparing the cells of the SRAM and the DRAM, as shown in FIG.
The access time is about 2 to 3 times faster than that of DRAM, but the occupied area is about 5 to 10 times larger than that of DRAM.

[0013]

As described above, in the MPU having the built-in cache memory, the cells of the cache memory are constituted by only one of the SRAM or DRAM described above.

For example, when the cache memory is composed only of SRAM, the data processing can be performed at high speed due to the fast access time. On the other hand, in the same area, the capacity is smaller than that of DRAM. This reduces the hit rate of the cache memory and increases the frequency of access to the main memory. Therefore, there is a problem that the processing efficiency is lowered.

On the other hand, when the cache memory is composed only of DRAM, the capacity can be increased and the hit rate can be increased. On the other hand, the access time becomes longer than that of SRAM. Therefore, there is a problem in that it takes time to read the instructions and operand data stored in the cache memory, and the processing time of each instruction becomes long.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide an SRAM and a D.
A cache that mixes RAM and achieves large capacity and high speed without increasing the size of the configuration, and contributes to improvement in processing efficiency and processing time of the processor without increasing size of the processor. To provide a memory system.

[0017]

In order to achieve the above object, the invention according to claim 1 is a DRAM (dynamic type) which holds a subset of information stored in a main memory and a tag address corresponding to the subset. Random access memory), a first cache memory, and an SRAM
A tag address corresponding to the information held in the data memory unit, which is made up of a static memory type random access memory and holds a subset of the information held in the first cache memory and an SRAM A memory stage that includes a tag memory unit that holds, a first register that holds an access address for accessing the information held in the data memory unit,
A second register holding the tag memory read from the tag memory unit, a third register holding the information read from the data memory unit, and an access address held in the first register And a tag address held in the second register, and outputs a hit signal when the two match and a miss signal when the two do not match, and held in the first register A part of the information held in the third register according to a part of the access address that has been selected, and a selector that gives the selected information to the first cache memory; and a comparison result of the comparator, A load stage having a control logic for controlling data access to the main memory according to a comparison result, the memory stage and the load stage The first, constituted by a second cache memory in which the second and third registers are operated by pipelining.

[0018]

In the above structure, according to the present invention, the cache memory system is hierarchized, and the first cache memory has a large capacity and the second cache memory has a pipeline structure at a high speed without increasing the size of the structure. I try to achieve this.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

First, before explaining an embodiment of the present invention,
The configuration of a cache memory system of a reference example related to the present invention will be described with reference to FIGS.

As shown in FIG. 2, the cache memory system 11 shown in this reference example is integrated with an MPU (microprocessor) 13 into one chip.

Before describing this reference example, the cache memory will be briefly described.

The cache memory is a high-speed memory placed between the processor and the main memory, and a subset of the information in the main memory is stored and accessed. Therefore, when the frequently accessed information is stored in the cache memory and the hit rate becomes high, the effect of the cache memory is exerted.

Such a cache memory system is
As shown in FIG. 1, a data memory unit 15 that stores and holds a subset of information stored in a main memory (not shown).
And a tag memory unit 17 that stores and holds a tag address corresponding to each piece of information of the subset, and two modules having different functions.

The cache memory system of this reference example is
The tag memory unit 17 is composed of SRAM, and the data memory unit 15 is composed of DRAM. The tag memory unit 17 and the data memory unit 15 correspond to a 32-bit address space (a0 to a31), and have a block length of 16 bytes and a direct mapping method of 256 entries.

Such a cache memory system is
The tag memory unit 17 and the data memory unit 15 are provided with 32-bit addresses (a0 ...
It is accessed by an 8-bit address (a20 to a27) of a31). The 20-bit address read from the tag memory unit 17 by this address is 3 by the comparator 19.
20-bit address (a0-a1) of 2-bit address
Compared with 9).

If both addresses match in the comparison result, the 16-byte data read from the data memory unit 15 corresponding to the address read from the tag memory unit 17 (shown by hatching in FIG. 1). -Ta (shown with diagonal lines in Figure 1)
Is confirmed to be the desired data, the hit signal is given from the comparator 19 to the control logic 21. As a result, a status signal indicating a hit is given from the control logic 21 to the MPU. The 16-byte data read from the data memory unit 15 is selected as 1-byte data by the selector 23 according to the 4-bit address (a28 to a31) of the 32-bit address, and M
Given to PU. The timing of such a read operation is shown in FIG.

On the other hand, if the two addresses do not match, the comparator 19 outputs to the control logic 21 a miss signal indicating that the data read from the data memory section 15 is not the desired data. To be done. As a result, the control logic 21 accesses the main memory for desired data that is not stored in the data memory unit 15.

As described above, the hit signal and the miss signal are
It serves as a signal indicating whether or not the desired data to be read is stored in the data memory section 15. Therefore, the operation after the data read operation from the data memory unit 15 is different depending on whether the hit signal or the miss signal is output. Therefore, the hit signal and the miss signal are required to be speeded up. In order to output the hit signal and the miss signal at high speed, it is necessary to speed up the address output of the tag memory unit 17. Therefore, speeding up of the tag memory unit 17 is required.

On the other hand, the capacities of the data memory unit 15 and the tag memory unit 17 are as follows. Data memory section
128 bits / entry × 256 entries = 32780
Bit tag memory unit 20 bits / entry × 256 entries = 5120 bits As described above, the data memory unit 15 needs to have a capacity six times or more that of the tag memory unit 17. However, the data memory unit 15 is not required to have high speed as compared with the tag memory unit 17.

Therefore, in this reference example, the data memory unit 15 is composed of DRAM and the tag memory unit 17 is SRA.
Since it is composed of M, it is possible to achieve the above-mentioned increase in capacity of the data memory unit 15 and increase in speed of the tag memory unit 17 without increasing the occupied area. As a result, data processing can be performed efficiently and at high speed.

The reference example shown in FIG. 4 is for optimizing a separate cache memory system. The separate cache memory system divides the cache memory into two parts, an instruction cache and a data cache, and holds a machine language instruction for each instruction and
It is a system that holds memory operands for data.

The advantage of this separate cache memory system is that the MPU instruction fetch and operand access do not conflict on one data bus.
It is to be able to operate U smoothly. In addition, access to the instruction cache memory of the MPU and data
Each of them can be optimized due to the difference in characteristics from the access to the cache memory.

Here, in the Neumann type computer, since the instruction is processed step by step to execute the program, the instruction is frequently fetched sequentially at consecutive addresses. On the other hand, the memory operands are rarely accessed in a predetermined order.
With this in mind, in this reference example, as shown in FIG. 4, in a separate cache memory system, the instruction cache memory 31 is composed of DRAM, and the data cache memory 33 is It is composed of SRAM so that it can be integrated into one chip together with the MPU 35.

The instruction cache memory 31 is constructed as shown in FIG. In FIG. 5, the tag memory unit 3
Either one of the addresses A and B read from 7 is selected by the selector 39 and compared with the address given by the MPU by the comparator 41, and a hit signal or a miss signal is output according to the comparison result.

On the other hand, since the data memory unit 43 is often accessed sequentially at consecutive addresses, the block size is increased and the stored instruction is read by the static column mode access method. I'm trying to put it out.

This static column mode is a system in which the potential of the data line (bit line) of the cell is kept constant for an arbitrary clock period. In this mode, when a read operation is first performed, while the column (row) address is being accessed, the data is read only by changing the row (column) address without performing the read operation. It

Of the four sets of instructions a0, a1, b0, b1 read from the data memory unit 43, one of them is selected by the selector 45 and given to the instruction decoder 47 to be decoded. FIG. 6 shows a tag memory unit 37 and a data memory unit 43.
The read timing of is shown.

As described above, by accessing the instruction from the data memory unit 43 by the static column mode, the access time can be shortened even though it is a DRAM. Further, since it is composed of DRAM, it is possible to increase the capacity.

On the other hand, the data cache memory 33 is constructed as shown in FIG. In FIG. 7, the operand data read from the data memory section 49 is the data.
Position adjustment such as right shift of data and code extension are performed by the data position adjustment circuit 51 and the code extension circuit 53, and given to the arithmetic unit 55.

When such an operation is performed by pipeline processing, in order to reduce the number of stages of the pipeline,
It must be executed at high speed in one cycle including processing such as data position adjustment and code extension. Further, since the read operation of the operand data must be synchronized with the clock cycle of the MPU, high speed is required. Therefore, by configuring the data cache memory with SRAM, high-speed access of operand data becomes possible. As described above, in this reference example, since the instruction cache memory and the data cache memory are optimized, the capacity and the data are increased without increasing the occupied area.
The processing speed can be increased.

Next, an embodiment of the invention described in claim 1 will be described with reference to FIG.

This embodiment is an optimization of the structure in a hierarchical cache memory system.

In the cache memory system, MP
When the access gap between U and the main memory is large, it is possible to divide the cache memory itself into hierarchies. Therefore, as shown in FIG. 8, the cache memory system shown in this embodiment has the first cache memory 61.
And the second cache memory 63 are divided into one chip.

The second cache memory 63 is a cache memory directly accessed by the MPU and is required to have high speed so that it can be accessed in synchronization with the clock cycle of the MPU. Therefore, the second cache memory 63
Is configured as shown in FIG. 9, and the tag memory unit 6
5 and the data memory unit 67 are composed of SRAM. Further, the tag memory unit 65 and the data memory unit 67 are used as memory stages, and the comparator 69, the control Rossic 71 and the selector 73 are used as load stages.
Registers 75, 77 and 79 for temporarily holding information input / output between both stages are provided between the stages to form a pipeline structure. The second cache memory 63 has 3
This is a direct mapping method corresponding to a 2-bit address space and having a block size of 4 bytes and 64 entries.

In such a structure, the read operation is performed by pipeline processing as shown in FIG. Therefore, in the second cache memory 63, the tag memory unit 65 and the data memory unit 67 are composed of SRAM, and the pipeline structure is adopted, so that high-speed access is possible.

On the other hand, the first cache memory 61 is
It is accessed when desired data is not stored in the entry of the cache memory 63. Even in this access, if the desired data is not stored in the first cache memory 61, the first cache memory 61 accesses the main memory. Therefore, the first cache memory 61 is required to have a high hit rate and a low access frequency to the main memory.

Therefore, according to this embodiment, a block size of 64 bytes corresponds to 1 in a 32-bit address space.
The 28-entry direct mapping method, the 11th
In the first cache memory configured as shown in the figure, the tag memory unit 81 and the data memory unit 83 are DRAM.
I am trying to configure it. As a result, it is possible to increase the capacity of the tag memory unit 81 and the data memory unit 83 and increase the hit rate.

Further, the first cache memory 61 does not have a pipeline structure and is adapted to update the entry at the timing shown in FIG. 12 in synchronization with the relatively slow memory cycle of the main memory. There is. This can simplify the configuration.

The first cache memory 61 to the second cache memory 61
The data can be transferred to the cache memory 63 at high speed by using the high-speed access mode of the DRAM such as the static column mode described above.

Therefore, the first cache memory 61 is composed of DRAM, and the second cache memory 63 is SRA.
By using M and a pipeline structure, a hierarchical cache memory system capable of high-speed data processing can be realized.

Note that such a hierarchical cache memory system may be integrated with the MPU 85 into one chip as shown in FIG.

[0053]

As described above, according to the present invention, the cache memory system is hierarchized, the first cache memory is composed of DRAM, the second cache memory is composed of SRAM, and the pipeline is used. Since the structure is adopted, the access speed can be increased without increasing the size of the structure. As a result, it is possible to provide a cache memory system that contributes to improvement in processing efficiency and processing speed in the processor.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a cache memory system according to a reference example related to the present invention.

FIG. 2 is a diagram showing a configuration of a cache memory system according to a reference example related to the present invention.

FIG. 3 is a diagram showing an operation timing of the system shown in FIG.

FIG. 4 is a diagram showing a configuration of a cache memory system according to a reference example related to the present invention.

FIG. 5 is a diagram showing a configuration of a cache memory system according to a reference example related to the present invention.

FIG. 6 is a diagram showing an operation example of the system shown in FIG.

FIG. 7 is a diagram showing a configuration of a cache memory system according to a reference example related to the present invention.

FIG. 8 is a diagram showing a configuration of a cache memory system according to an embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a cache memory system according to an embodiment of the present invention.

10 is a diagram showing a timing of pipeline operation of the system shown in FIG.

FIG. 11 is a diagram showing a configuration of a cache memory system according to an embodiment of the present invention.

FIG. 12 is a diagram showing a timing of updating the system shown in FIG. 11.

FIG. 13 is a diagram showing one system of the system shown in FIG.

FIG. 14 is a diagram showing a configuration of a conventional memory cell.

FIG. 15 is a diagram showing a configuration of a conventional memory cell.

FIG. 16 is a diagram showing a configuration of a conventional memory cell.

FIG. 17 is a diagram showing a configuration of a conventional memory cell.

FIG. 18 is a diagram showing a characteristic comparison of the memory cells shown in FIGS. 14 to 17;

FIG. 19 is a diagram showing a characteristic comparison of the memory cells shown in FIGS.

[Explanation of symbols]

 11 cache memory system 13 MPU (microprocessor) 15 data memory unit 17 tag memory unit 31 instruction cache memory 33 data cache memory 61 first cache memory 63 second cache memory

Claims (1)

[Claims] 1. A DRAM holding a subset of information stored in a main memory and a tag address corresponding to the subset.
A first cache memory composed of (dynamic random access memory), and data containing SRAM (static random access memory) holding a subset of information held in the first cache memory Memory part and SRAM
A memory stage having a tag memory unit for holding a tag address corresponding to the information held in the data memory unit; and a first memory stage holding an access address for accessing the information held in the data memory unit. A register, a second register that holds the tag memory read from the tag memory unit, a third register that holds the information read from the data memory unit, and a first register that holds the information. A part of the access address stored in the second register is compared with the tag address held in the second register, and a hit signal is output when the two match, and a miss signal is output when the two do not match; and the first comparator. According to a part of the access address held in the register, the third
Selecting a part of the information held in the register, and receiving the comparison result of the selector and the comparator which gives the selected information to the first cache memory, and stores the data in the main memory according to the comparison result. A load stage having a control logic for access control, the memory stage and the load stage, and a second cache memory in which the first, second and third registers operate in a pipeline manner. A cache memory system having.