JPH07117918B2 - Data processing system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple virtual address space type data processing system having an address translation buffer (TLB).

[Prior Art] Conventionally, in a processing system using virtual addressing in a multiple virtual storage space, an address translation buffer (TLB) is used to perform address translation for obtaining a real address from a virtual address space and a logical address at high speed. Is well known.

Address translation is performed using a segment table and a page table, which are translation tables defined by the system for each virtual address space. Each entry of the TLB has a field that stores the segment table origin (STO) defined in the segment table descriptor (STD), which is the origin on the main memory of the segment table, and the segment table A field is provided for storing the defined common segment bit (C). In the conversion by the TLB, the success of the conversion to the real address (TLB hit) is determined by the contents of the STO and C fields. At this time, when accessing the address space, the contents of the STO field are compared with the STO in the STD used to convert the virtual address of the space to be accessed to the real address, and if they match, it is determined that the conversion was successful. However, when the content of the C field is '1', that is, when the segment table is a segment table common to all address spaces, the content of the STO field in the TLB entry and the STO in the STD are It is determined that the conversion is successful without making a comparison.

Further, in the TLB entry field, for example, in a virtual computer system, as shown in Japanese Patent Publication No. 57-23347, a VM-ID field is provided as the guest virtual computer (guest VM) identification information, We are trying to improve

In the conventional computer architecture, when the TLB conversion is performed to access the address space, private control information (private control bit) defined in the STD used for converting the virtual address of the address space to the real address is used. ) Indicates that the address space is private, the TL indexed for access to that address space.
Even if the translation pair in the B entry is a common segment translation pair, address translation by using the translation pair is not permitted.

In a processing system that realizes such an architecture, when the conversion pair by the TLB index is a common segment conversion pair for private space access, the conversion pair is not used and the segment table and page on the main memory are not used. The table index must always be converted.

[Problems to be Solved by the Invention] In the above-mentioned conventional technique, when accessing a private space,
When the TLB, especially the TLB index conversion pair composed of multiple rows is a common segment conversion pair, the conversion pair is not used as described above, and the segment table in the main memory is used.
The page table index must always be converted. Therefore, when accesses to the private space are continuous within the same page, conversion is frequently performed by the indexes of the segment table and page table in the main memory, resulting in extra overhead in processing performance.

An object of the present invention is to provide a data processing system capable of reducing the overhead caused by frequent conversions by the indexes of the segment table and page table on the main memory.

Another object of the present invention is to provide a data processing system having means for registering a private space access address translation pair in a TLB.

[Means for Solving the Problems] In order to achieve the above object, a data processing system according to the present invention holds an address translation pair and a common segment bit, and is configured by at least one row indexed by a part of a logical address. In a virtual address space type data processing system having an address translation buffer, a private space control bit defined in a segment table descriptor used for translation from a virtual address to a real address is stored in each entry of the address translation buffer. Field is provided, and when accessing the address space, the private space control bit defined in the segment table descriptor used for converting the virtual address of the address space into the real address and the private space control bit field of the address translation buffer are defined. The address of the private space control bit field and the common segment bit field in the same entry of the address translation buffer. Indicates that the logical value '1' is not registered at the same time.

In this data processing system, preferably, during the private space access in which the private space control bit defined in the segment table descriptor used for the conversion from the virtual address to the real address has a logical value of “1”,
If the entry indexed from the address translation buffer has an entry with a common segment bit having a logical value of '1', the translation pair of the private space access for the entry is set to a logical value of the private space control bit of '1'. 'With registration means to register with. Alternatively, for a multi-row address translation buffer, when the private space access in which the private space control bit defined in the segment table descriptor used for translation from the virtual address to the real address has a logical value of "1",
When an entry whose common segment bit has a logical value of "1" exists in the plurality of entries indexed from the address translation buffer, an invalidation unit that invalidates all the entries of the column to which the entry belongs, 1 of
Registration means for registering the conversion pair of the private space access for the entry together with the logical value '1' of the private space control bit.

[Operation] When the address translation buffer (TLB) is referenced for virtual address space access, the private space control bits defined in the STD used to translate the virtual address of the address space into the real address are indexed. The contents of the private space control bit field in the TLB entry are compared, and a match between them is taken as a condition for successful address translation.

On the other hand, address translation in which both the private space control bit field and the common segment bit field have a logical value of "1" is not allowed.

Therefore, when accessing the private space, if the common segment bit field of the indexed TLB entry has a logical value of '1', the private space control bit concerned and the value of the private space control bit field of the indexed TLB entry are Does not match, and address conversion is performed with reference to the segment table and page table on the main memory.

Therefore, the address translation pair obtained by this address translation is registered in the TLB together with the logical value "1" of the private space control bit. After registration, the private space address can be translated by using this translation pair in the TLB.

In order to register the conversion pair in the private space, it is detected that the indexed conversion pair is a common segment conversion pair, and the entry or all the indexed entries including the entry are invalidated, Register a private space address translation pair in one of the entries.

As described above, when accessing the private space, if the indexed TLB entry is a common segment translation pair,
As the conversion was unsuccessful, the address in the main memory is converted by the segment and page table, and the conversion pair obtained by this is registered together with the private space control bit, so that the access to the private space continues in the same page. Even in such a case, the address conversion by the TLB is successful, the frequent occurrence of the address conversion due to the table reference in the main memory can be avoided, and the processing performance of the data processing system can be improved.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows a relevant part of the present invention in a multiple virtual address space type data processing system. The system portion of FIG. 1 includes an instruction execution unit 1 that executes individual instructions,
The register groups 5 to 9 in which predetermined values are respectively set by the instruction execution unit 1, the TLB 3, and the register groups 5 to 9
And according to the information from the address converter (not shown)
A write control unit 2 for controlling data writing of the TLB 3,
The TLB hit determination unit 4 determines a TLB conversion success, that is, a TLB hit at the time of space access.

The register 5 is a VM mode register (G register) in the virtual computer system, and is set to '1' in the guest VM mode. Registers 6 and 7 are registers that hold a part of the contents of the segment table descriptor (STD). That is, the register 6 is a private space control register (P
Register), and is set to '1' when the virtual address space to be accessed is a private space. Register 7 is the segment table base point (STO) in the STD.
Segment table origin register (STO
Register). Further, the register 8 is a real mode register (R register) which indicates whether the TLB index is performed with a virtual address or a real address, and the register 9 is an address register which holds an effective address.
The address register 9 has, for example, 31 bits. The upper 1st to 19th bits form a page address and are subjected to address conversion, and the 20th to 31st bits are bits common to the real address.

When an access request to the address space is issued, the instruction execution unit 1 sets predetermined data in the G register 5, P register 6, STO register 7, R register 8 and address register 9, respectively. After that, a reference request is issued to TLB3.

TLB3 adopts the set associative method. That is, it has one or a plurality of entries selected by the column address via the column address decoder 10. Each entry is called a row, and this row is an index or registration target. In this embodiment shown in FIG. 1, the number of columns
Although the TLB configuration has 512 rows and one row, that is, 512 entries, other configurations such as a plurality of rows can be easily inferred.

Each entry of TLB3 has a valid field (V), guest field (G), private space control field (P), common segment field (C), segment origin field (STO), virtual address field (VA), real address mode. It is composed of a field (R) and an absolute address field (PA). The number of bits in each field is shown in “()”.

The V field indicates whether this entry is valid or invalid 1
This is a bit field and indicates "1" when enabled and "0" when disabled. The G field is address translation information indicating whether the entry corresponds to a host or a guest VM in the virtual computer system.
This field is set to "1" for guest VM and "0" for host. The P field is a field indicating whether or not the entry defines a private space translation pair. When the entry is '1', the entry is an address translation pair in the private space. Indicates that it is not a private space. The R field is a 1-bit field indicating whether the translated address of the entry is a real address or a virtual address, and indicates a virtual address when it is '0' and a real address when it is '1'. The C field indicates that the entry is an address translation pair using a common segment when this field is "1". When the common segment bit in the segment table used for address translation is "1", this field is "1". The STO field represents the segment table starting point address in the segment descriptor when the address of the entry is translated. VA field is TL
It is a bit other than the column address in the page frame address of B access, and in FIG. 1, it is a 10-bit field for storing bits 1 to 10. PA field is the page frame address of the real address
Stores 19 bits.

The TLB hit determination unit 4 includes comparison circuits 11 to 15 and OR gates 16 and 1.
7, AND gate 18, and inverter 19. The comparison circuit 11 compares the G field of TLB3 with the contents of the G register 5, and outputs "1" when they match. The comparison circuit 12 is
Compare the P field of TLB3 with the contents of P register 6,
Outputs '1' when they match. Further, the comparison circuit 13 compares the STO, the comparison circuit 14 compares the VA field with a page frame address other than the column address of the access address register 9, and the comparison circuit 15 compares the real address mode. Outputs "1". TLB
The TLB hit condition in the hit determination unit 4 is that the V field of the TLB entry is "1", the contents of the TLB G field and the G register 5 match, the contents of the TLB R field and the R register 8 match, the TLB VA field and the address. Page frame address part other than column address in register 9 matches, TLB C field is '1', or STO field of TLB matches the contents of STO register 7, TLB P field matches the contents of P register.

When all of the above conditions (1) to (3) are satisfied, the TLB hit 20 becomes "1", and when not satisfied, the TLB miss 21 becomes "1". The TLB hit 20 and PA field output 22 are transferred to a cache control unit (not shown), and the TLB miss 21 is transferred to an address translation control unit (not shown). As can be seen from the above condition, when the space to be accessed is a private space, the conversion pair of the indexed TLB entry is also a conversion pair of the private space, which is the condition for the TLB hit.

The TLB write control unit 2 controls TLB registration and TLB invalidation by address translation. When TLB is registered, TLB3 G, ST
The contents of G register 5, STO register 7, P register 6, address register 9, and R register 8 are stored in the O, P, VA, and R fields, respectively. The values C and PA transferred from the address conversion unit are stored in the C field and the PA field, respectively.

Since the address translation unit does not allow translation in which the common segment bit is '1' when translating a virtual address in the private space into a real address, the P and C fields in the TLB entry may be '1' at the same time. Absent.

Therefore, when accessing the private space (value of P register 6 is "1"), if the indexed TLB entry is a common segment conversion pair (when C field is "1"), the corresponding P field is always Since it is "0", the value of the P register 6 does not match the P field, and a TLB miss is always generated. Therefore, as described above, the fact is notified to the address translation control unit, the address translation is newly performed by the segment table and the page table in the main memory, and the translation pair thus obtained is written in the relevant entry of TLB3. . At the time of this writing, the value "1" of the P register 6 is written in the P field. After that, for the access to the private space that indexes the TLB entry, the value of the P register 6 and the value of the P field match, so the TLB hit condition is satisfied. As a result, even when the private space is continuously accessed, the conversion by the segment table and page table indexes in the main memory is not always performed, and extra overhead in processing performance can be avoided. it can.

When TLB3 has multiple rows, when a TLB entry with a C field of "1" exists in the column of the indexed TLB when accessing the private space, only that one TLB entry is used as a new translation pair and associated fields. Replace with information. Alternatively, once, all TLB entries belonging to the column are invalidated (that is, "0" is written in the V field), and then one TLB entry is
Write the new transform pair and the contents of each associated field. At this time, the V field is "1", the P field is "1", and the C field is "0". The former method has an advantage that the TLB usage efficiency is improved because all entries in the column are not invalidated. On the other hand, the latter method has an advantage that invalidation processing is easy because all entries in the same column are invalidated.

According to the present invention, when accessing the private space, even if the indexed TLB entry is a common segment translation pair, the translation pair is not used, and the TLB entry is not used.
It is possible to register the P field as "1" in the. The conversion of the segment table and page table in the main memory is performed only at the time of registration in the TLB, and the conversion overhead can be reduced and the processing performance can be improved.

[Effect of the Invention] In the present invention, a field for storing private space control information defined in STD is provided in the TLB entry, and in the TLB access, the content of the field and the private space control information in STD are compared, Since matching is used as a condition for successful address translation, even if the indexed TLB entry is a common segment translation pair, the translation pair of the entry is not used for address translation. In addition, again
A new conversion pair can be registered.

Therefore, the TLB index result at the time of private space access, the conversion pair indexed is the common segment conversion pair,
When the access to the private space is continuous, it is possible to improve the processing performance without always performing the conversion by the index of the segment table and the page table in the main memory and generating the extra overhead in the processing performance. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, particularly a TLB and a TLB hit determination unit. 1 ... Instruction execution unit, 2 ... TLB write control unit, 3 ... TLB, 4 ... TL
B hit determination section, 5 ... guest register, 6 ... private space control register, 7 ... STO register, 8 ... real address mode register, 9 ... address register, 10 ...
Column address decoder.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tomonori Yamamoto 1 Horiyamashita, Hadano City, Kanagawa Pref., Kanagawa Factory, Hiritsu Seisakusho Co., Ltd. (56) Reference JP-A-63-231550 (JP, A)

Claims (2)

[Claims] 1. A virtual address space type data processing system having an address translation buffer, which holds an address translation pair and a common segment bit, and comprises at least one row indexed by a part of a logical address. Each entry of is provided with a field to store the private space control bit defined in the segment table descriptor used to convert the virtual address to the real address, and at the time of access to the address space, from the virtual address of the address space An address that compares the private space control bit defined in the segment table descriptor used for conversion to a real address with the value of the private space control bit field of the address conversion buffer, and makes the match between them a condition for successful address conversion. conversion And a registration control unit for controlling registration of the address translation pair, the private space control bit, and the common segment bit for each entry of the address translation buffer, wherein the registration control unit is a private entry within the same entry. The registration of the private space control bit and the common segment bit for each entry of the address translation buffer is controlled so that the logical value "1" is not registered in the space control bit field and the common segment bit field at the same time, and the virtual address is controlled. To a real address, the private segment control bit defined in the segment table descriptor has a logical value of "1". When accessing the private space, the common segment is included in the entry indexed from the address translation buffer. When there is an entry whose bit is the logical value "1", the registration control means replaces the conversion pair registered in the entry with the conversion pair of the private space access and the logical value "1" of the private space control bit. A data processing system characterized by being registered in the entry together with ". 2. A virtual address space type data processing system having an address translation buffer which holds an address translation pair and a common segment bit, and which is composed of a plurality of rows indexed by a part of a logical address. Each entry of is provided with a field to store the private space control bit defined in the segment table descriptor used for the conversion from the virtual address to the real address, and when accessing the address space, the virtual address of the address space An address that compares the private space control bit defined in the segment table descriptor used for conversion to a real address with the value of the private space control bit field of the address conversion buffer, and makes the match of both conditions a condition for successful address conversion. Conversion success judgment Means, registration control means for controlling registration of the address translation pair and private space control bit and the common segment bit for each entry of the address translation buffer, and segment table descriptor used for translation from virtual address to real address When the private space access in which the private space control bit defined in 1 is a logical value "1", there is an entry in which the common segment bit is a logical value "1" in the plurality of entries indexed from the address translation buffer. In this case, the registration control means has invalidation means for invalidating all the entries of the column to which the entry belongs, and the registration control means simultaneously applies the private space control bit field and the common segment bit field in the same entry. Logical value "1" is not registered A private space control bit for controlling each entry of the address translation buffer and the registration of the common segment bit, and a private space control defined in a segment table descriptor used for translation from a virtual address to a real address. When a private space access in which a bit has a logical value of "1" is made and there is an entry having a common segment bit of a logical value of "1" in the plurality of entries indexed from the address translation buffer, the registration control means The data processing system is characterized in that the conversion pair of the private space access is registered together with the logical value "1" of the private space control bit for one entry of the column which is invalidated by the invalidation means.