JPH07117919B2 - Cache memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device, and more particularly to a cache memory device for indexing a plurality of cache memories to determine request data and controlling replacement of the cache memories. Regarding

[Prior Art] Usually, one cache memory (hereinafter, also simply referred to as cache) includes a data array section that holds a part of the data in the main memory, and an address array that manages the address of the registered data in this data array section. It is composed of parts.

Conventionally, in a cache memory composed of a plurality of levels, it is determined by which index of a plurality of address array units the desired request data exists in the data array unit, and the data is read from the plurality of data array units according to the result. The requested data was obtained by selecting the issued data.

Furthermore, when the requested data does not exist in all the cache memories, the replacement algorithm circuit using the LRU (Least-Recently-Used) algorithm or the like determines the cache memory to be replaced.

[Problems to be Solved by the Invention] In the above-described conventional cache memory device, the selection circuit is used to select the data array in which the requested data exists after determining in which data array section the requested data exists. Is required. Therefore, there is a drawback that the gate delay until indexing the cache memory or obtaining the requested data becomes large and the machine cycle of the system cannot be shortened.

Further, since a replacement algorithm circuit for the cache memory is required, there is a drawback that it hinders miniaturization of the device.

[Means for Solving the Problem] A cache memory device according to a first aspect of the present invention holds a plurality of address / data pairs each of which comprises an address and memory data corresponding to the address. First to Nth cache memories given a priority of (N ≧ 2), means for simultaneously indexing the first to Nth cache memories, and no request data exists in the first cache memory In this case, the address / data pair existing in another cache memory other than the first cache memory is replaced with the address / data pair in the first cache memory, and the request data is always obtained from the first cache memory. And means.

A cache memory device according to a second aspect of the present invention holds a plurality of address / data pairs each consisting of an address and memory data corresponding to the address, and the first to Nth (N ≧ 2) to the instruction address index. Number of cache memories to which priority levels of 1 and N to 1 to N for the operand address index are individually assigned, means for simultaneously indexing the N number of cache memories, instruction address index and operand address index In each of the indexes, when the requested data does not exist in the cache memory having the first priority, the address / data pair existing in the cache memory other than the cache memory having the first priority and the first Replace the address / data pair of the cache memory with the priority of 1,
And means for always obtaining the requested data from the first cache memory having the first priority assigned individually for each instruction address or operand address index.

A cache memory device according to a third aspect of the present invention includes first to Nth (N ≧ 2) cache memories each of which holds a plurality of address / data pairs each of which includes an address and memory data corresponding to the address. Means for continuously indexing from the first cache memory to the Nth cache memory until request data exists; and when request data does not exist in the first cache memory, the means other than the first cache memory Means for replacing the address / data pair existing in another cache memory with the address / data pair of the first cache memory and always obtaining the requested data from the first cache memory.

A cache memory device according to a fourth aspect of the present invention comprises first to Nth (N ≧ 2) cache memories each of which holds a plurality of address / data pairs each of which includes an address and memory data corresponding to the address. It has means for continuously indexing from the first cache memory to the Nth cache memory until the requested data exists, and means for obtaining the requested data from the cache memory where the requested data exists.

A cache memory device according to a fifth aspect of the present invention holds a plurality of address / data pairs each consisting of an address and memory data corresponding to the address, and the first to Nth (N ≧ 2) priority levels are set. Given first to Nth cache memory, and the requested data does not exist in the first cache memory,
When request data exists in a cache memory other than the first cache memory, the first cache memory is configured so that the address / data pair including the request data is replaced by the first cache memory. To the cache memory in which the address / data pair including the requested data exists, the address / data pairs of all the cache memories having the priority order are replaced according to the priority order, and the requested data is always sent from the first cache memory. It has a means for obtaining and a means for selecting the address / data pair of the cache memory having the lowest priority as a replacement target when the requested data does not exist in all the cache memories.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a cache memory device according to a first embodiment of the present invention.

In FIG. 1, PAR100 is a real address register that receives a real address for indexing the address array section and the data array section of the cache, and AA110 to 113 are address array sections that manage the addresses of the data array section of the cache, A
AW120 to 123 are write registers to AA110 to 113 respectively, selectors 130 to 133 are selectors for selecting input data to AAW120 to 123 respectively, and CMP140 to 143 are outputs of PAR100.
A comparator for comparing the outputs of the AA110 to 113, a cache control circuit 200 is a control circuit that controls the cache according to the output results of the CMPs 140 to 143, and a FF201 is a cache control circuit.
A flip-flop that receives a portion of the control signal from 200,
DA210-213 is a data array section of a cache that holds a part of data in a main memory (not shown), DAW220-223 are write registers to DA210-213, selectors 230-2
33 is a selector that selects the input data to the DAWs 220 to 223, a selector 240 is a selector that selects the part of the block data read from the DA 210 that the requester requested, and a DAR 250 is the selector 240 that is selected. A data array read register that receives read data from the DA 210.

The AA 110 to 113 manage the block address of the data array unit that registers data in units of blocks. In this embodiment, the cache block size is 64 bytes, and AA1
10 to 113 are accessed by the lower address of the out-of-block address part ignoring the lower 6 bits (in-block address) of the real address of PAR100, and the remaining out-of-block address is stored in AA110 to 113 as a key address. It is registered.

DAs 210 to 213 register block data at address positions corresponding to AA 110 to 113, respectively. That is, each DA 210-213 corresponding to AA 110-113 holds the address / data pair of the cache memory.

Data is read from the cache memory in the size of the data requested by the request source and sent to the request source. In this embodiment, the size of this data is 8 bytes. DA210
Up to 213 are indexed by the real address part of PAR100, which is the same as the AA index address, and 64-byte data is read from each.
The 64-byte data read from the DA210 is output to the selector 240, and the address portion ignoring the lower 3 bits (8-byte internal address) of the block address portion of the real address of PAR100 ignores the 64-byte data. The 8-byte data requested by the request source is selected and the request data is sent from the DAR250 to the request source.

A cache memory for one level is constructed by one address array and a corresponding data array. The cache memory of this embodiment is a four-level cache memory having four levels of address arrays and four data arrays, respectively. The AA 110 to 113 and the DA 210 to 213 correspond to the levels 0 to 3, respectively, and the first to the fourth priorities are assigned to the levels 0 to 3, respectively. Also,
The same block data will not be registered twice in the entire cache memory.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to FIG.

When the real address is set in PAR100, AA110-113 and DA210-213 are simultaneously indexed in the lower address part of the out-of-block address. The key address is read from the AA 110 to 113 and sent to the CMPs 140 to 143, respectively. CMP140 ~ 1
At 43, the remaining address portions of the out-of-block addresses corresponding to the key address portion of PAR 100 are simultaneously compared, and the comparison result is output to the cache control circuit 200. When CMP140-143 detect a match, logical "1",
When a mismatch is detected, a logical "0" is output.

Now, assume that the requested data exists in the cache memory having the first priority, that is, the level 0 cache memory.

That is, the CMP 140 outputs a logical “1” and detects that the requested data exists in the DA 210. At this time, the cache control circuit
200 sets FF201 to logical "1" to indicate that the requested data exists in the cache memory having the first priority. At the same time, block data including request data is read from DA 210 and sent to selector 240, and PAR1
The 8-byte request data is selected by the 8-byte data designation address portion of the 00 block address.
It is set to DAR250. The request data set in the DAR250 is sent to the request source together with the FF201 signal indicating that the contents of the DAR250 are valid.

Next, suppose that the requested data does not exist in the cache memory having the first priority, that is, the cache memory of level 0, and the requested data exists in the cache memory of level 2, for example.

In this case, the CMP 142 outputs a logic "1" and detects that the requested data exists in the DA 212. Therefore, the cache control circuit 200 sets a logical "0" in the FF 201 to indicate that the requested data does not exist in the cache memory having the first priority. The output of this FF201 notifies the request source that the data set in the DAR250 is invalid data.

At this time, the cache control circuit 200 simultaneously operates AA 110, 112 and D
Instruct to replace the block data with the key address of the corresponding address position in A210, 212. That is, AA110,1
For 12, the selectors 130 and 132 are controlled so that the key address read from AA110 is set in AAW122 and the key address read from AA112 is set in AAW120. Then, the data set in AAW120, 122 is changed to AA110, 1
Write to 12 applicable address locations. For the DAs 210 and 212, the selectors 230 and 232 are controlled to set the block data read from the DA 210 in the DAW 222 and the block data read from the DA 212 in the DAW 220. And DAW
The data set in 220 and 222 are written in the corresponding address positions of DA 210 and 212, respectively.

This completes the replacement processing of the address / data pairs in the level 0 and level 2 cache memories. This replacement process is simultaneously executed in parallel for both the address array and the data array.

When the replacement process is completed, the cache memory is indexed again. Request data is DA21 with first priority
Since it exists in 0, the requested data is set in DAR250 and FF
201 is set to a logic "1" indicating that the contents of DAR250 are valid and sent to the requesting sources respectively.

Also, even when the requested data exists in the level 1 and level 3 cache memories, the level having the first priority is executed in exactly the same manner as the replacement of the address / data pair of the level 0 cache memory. Request data is fixedly supplied from the cache memory of 0.

Referring to FIG. 2, the cache memory device according to the second embodiment of the present invention has the same configuration as that shown in FIG. 1 except that an I / O 101 and a selector 235 are added. Have.

The I / O 101 is a flag register that indicates whether it is an instruction address index or an operand address index. The cache control circuit 200a outputs the output results of the CMPs 140 to 143 and the I / O 1
It controls the cache according to the output result of 01. The selector 235 is a selector that selects read data from the DA 210 and DA 213. The selector 240a selects the part of the block data output from the selector 235 that is requested by the request source.

One of the 64-byte data read from DA210 and DA213 is selected by the selector 235 and output to the selector 240a, and the lower 3 bits (8-byte address) of the block address part of the real address of PAR100. The 8-byte data requested by the request source out of the 64-byte data is selected by the address section ignoring the, and the request data is sent from the DAR250 to the request source.

AA110 to 113 and DA210 to 213 respectively correspond to levels 0 to 3, and in the case of the instruction address index, the first to fourth priorities are given respectively corresponding to levels 0 to 3 and the operand address On the contrary, in case of index, level 3 ~
Corresponding to 0, the first to fourth priorities are given respectively.

Next, the operation of the second embodiment of the present invention will be described in detail with reference to FIG.

When the instruction address index or operand address index is set in the I / O 101 and the real address is set in the PAR 100 at the same time, AA110 to 113 and DA210 to 213 in the lower address part of the out-of-block address Indexed at the same time. The key address is read from the AA 110 to 113 and sent to the CMPs 140 to 143, respectively. PAR for CMP140-143
The remaining address parts of the out-of-block addresses corresponding to the key address part of 100 are simultaneously compared, and the comparison result is output to the cache control circuit 200a. CMP140 ~
143 outputs a logic "1" when a match is detected and outputs a logic "0" when a mismatch is detected.

Suppose now that the I / O 101 points to the instruction address index, and the requested data exists in the cache memory having the first priority, that is, the requested data exists in the DA 210.

Therefore, the CMP 140 outputs a logic "1" to notify the cache control circuit 200a that the DA 210 has the requested data.
At this time, the cache control circuit 200a sets a logical "1" in the FF 201 to indicate that the requested data exists in the cache memory having the first priority. At the same time, DA2
Block data including request data is read from 10, selected by the selector 235, and sent to the selector 240a. In the selector 240a, 8-byte request data is selected by the 8-byte data designated address portion of the address in the block of PAR100 and set in the DAR250. DAR2
The request data set in 50 is sent to the request source together with the signal of FF201 indicating that the contents of DAR250 are valid.

The operation when there is no requested data in the cache memory having the first priority is the same as that of the above-described first embodiment, and therefore its explanation is omitted.

Generally, because of the locality of the program, the instruction word and the operand are likely to exist in memory independently, and both the instruction word and the operand are next accessed next to the data currently being accessed. Data is likely to exist. Therefore, by controlling as described above, it is possible to increase the possibility that the command word requested is registered in the DA210, and the requested data can be supplied faster than the DA210. That is, it becomes possible to centrally register the command words that are likely to be accessed in the DA 210.

On the other hand, when the instruction of the operand address index is set in the I / O 101, the instruction is notified to the cache control circuit 200a, and the cache control circuit 200a informs the DA 210 where the instruction words are concentrated, that is, the contents of level 0. The control is switched so that the operand to be sought is fixedly supplied from DA 213, that is, level 3 so as not to destroy the above.

The subsequent operation is the same as that for the index of the instruction address. When it is detected that the requested data exists in DA213, the requested data is read from DA213 to DAR250, and DA213 is read.
There is no required data in other DA210, 211 or 212,
That is, when it is detected that the data exists in the level 0, the level 1 or the level 2, the replacement process with the address / data pair of the cache memory of the level 3 is performed, and then the level 3 of the first priority is used. Request data is fixedly supplied from the cache memory. By controlling in this way, it becomes possible to centrally register operands that are likely to be accessed in DA213.

Referring to FIG. 3, the cache memory device according to the third embodiment of the present invention is different from that shown in FIG. 1 except that a selector 135 and a selector 235a are added and a CMP 140a is provided instead of the CMPs 140-143. It has a configuration similar to that shown in FIG.

The selector 135 is a selector that selects the outputs of AA110 to 113. CMP140a selected by PAR100 output and selector 135
Compare with the output of any of AA110-113. The cache control circuit 200b controls the cache according to the output result of the CMP 140a. Selector 235a selects the output of DA 210-213. Selector 240b is DA210 selected by selector 235a
Of the block data read from any of the items ˜213, the data of the part requested by the request source is selected.

64-byte data read from DA210-213 is a selector
It is selected by 235a and output to the selector 240b. By the address part that ignores the lower 3 bits (8-byte address) of the in-block address part of the real address of PAR100, 6
The 8-byte data requested by the request source is selected from the 4-byte data, and the request data is sent from the DAR250 to the request source.

AA110 to 113 and DA210 to 213 correspond to levels 0 to 3, respectively, and the index is tried in order of levels 0, 1, 2, and 3.
The levels 0 to 3 correspond to the first to fourth cache memories, respectively.

Next, the operation of the third embodiment of the present invention will be described in detail with reference to FIG.

When the real address is set in PAR100, AA110-113 and DA210-213 are accessed in the lower address part of the out-of-block address. The key address is read from the AA 110 to 113 and output to the selector 135, and the cache control circuit 200
b instructs to select the output of AA110. CMP140a,
The remaining address part of the address outside the block corresponding to the key address part of PAR100 and AA1 selected by the selector 135
The 10 outputs are compared, and the comparison result is the cache control circuit 200b.
Output to. CMP140a is logical "1" when a match is detected
If a mismatch is detected, a logical "0" is output.

Now suppose that the requested data exists in the first cache memory.

That is, the CMP 140a outputs a logical "1" and detects that the requested data exists in the DA 210. At this time, the cache control circuit 200b sets a logical "1" in the FF 201 to indicate that the requested data exists in the first cache memory. At this time, at the same time, the block data including the requested data is read from the DA 210, selected by the selector 235a according to the instruction from the cache control circuit 200b, and sent to the selector 240b. In the selector 240b, 8-byte request data is selected by the 8-byte data designation address portion of the address in the block of PAR100 and set in the DAR250. The request data set in the DAR250 is sent to the request source together with the FF201 signal indicating that the contents of the DAR250 are valid.

Next, suppose that the requested data does not exist in the first cache memory, for example, the requested data exists in the level 2 cache memory.

In this case, the CMP 140a outputs logic "0" and detects that the requested data does not exist in the DA 210. Therefore, the cache control circuit 200b sets a logical "0" in the FF 201 to indicate that the requested data does not exist in the first cache memory. The output of this FF201 notifies the request source that the data set in the DAR250 is invalid data.

At the same time, the cache control circuit 200b operates the selectors 135 and 2
35b instructs to select AA111, DA211. Then, again the output of PAR100 and the output of AA111 are compared by CMP140a, and C
The MP140a outputs logic "0" and detects that the requested data does not exist in the DA211.

The cache control circuit 200b switches the outputs of the selectors 135 and 235a and repeats the index in order until the CMP 140a outputs a logical "1" and detects the cache memory in which the requested data exists.

Then, when the selectors 135 and 235a select AA112 and DA212, respectively, the CMP 140a outputs a logic "1", detects that the requested data exists in the DA212, and notifies the cache control circuit 200b to that effect.

The cache control circuit 200b instructs the AA 110, 112 and DA 210, 212 to replace the block data with the key address at the corresponding address position. That is, the selectors 130 and 132 are controlled for the AA 110 and 112, the key address read from the AA 110 is set in the AAW 122, and the key address read from the AA 112 and selected by the selector 135 is set in the AAW 120. Then, the data set in the AAWs 120 and 122 are written to the corresponding address positions of the AA 110 and 112, respectively. D
DA210 is controlled by controlling selectors 230 and 232 for A210 and 212.
Set the block data read from the DAW222 to D
The block data read from A212 and selected by the selector 235a is set in the DAW220. Then, the data set in the DAWs 220 and 222 are written in the corresponding address positions of the DAs 210 and 212, respectively.

This completes the replacement processing of the address / data pairs in the level 0 and level 2 cache memories. This replacement process is simultaneously executed in parallel for both the address array and the data array.

When the replacement process is completed, the index from the first cache memory is performed again. Since the requested data exists in DA210 of the first cache memory, similar to the above description,
The requested data is set in the DAR250, and the FF201 is set to a logical "1" indicating that the contents of the DAR250 are valid and sent to the requesting sources.

Further, even when the requested data is present in the level 1 and level 3 cache memories, it is indexed in the same way from the first cache memory until the requested data is found, and when the requested data is found, it is the first cache memory. After performing the replacement process with the level-0 address / data pair, the requested data is fixedly supplied from the first cache memory.

Referring to FIG. 4, a cache memory device according to a fourth embodiment of the present invention includes selectors 130-133 and a selector 23.
0-233 is deleted, AAW120a is replaced by DAA120-123 instead of DA
It has the same configuration as that shown in FIG. 3 except that a DAW 220a is provided instead of W220-223.

AAW120a is a write register for AA110-113. DAW
220a is a write register to DA210-213.

Next, the operation of the third embodiment of the present invention will be described in detail with reference to FIG.

Now suppose that the requested data exists in the first cache memory.

That is, the CMP 140a outputs a logical "1" and detects that the requested data exists in the DA 210. At this time, the cache control circuit 200c sets a logical "1" in the FF 201 to indicate that the requested data exists in the cache memory currently indexing. At this time, at the same time, the block data including the requested data is read from the DA 210, selected by the selector 235a according to the instruction from the cache control circuit 200c, and sent to the selector 240b. In the selector 240b, the 8-byte request data is selected by the 8-byte data designation address portion of the address in the block of PAR100, and the DAR250
Is set to. The requested data set in DAR250 is D
It is sent to the request source together with the signal of FF201 indicating that the contents of AR250 are valid.

Next, it is assumed that the requested data does not exist in the first cache memory and the requested data exists in the level 2 cache memory, for example. In this case, the CMP 140a outputs logic "0" and detects that the requested data does not exist in the DA 210. Therefore, the cache control circuit 200c sets a logical "0" in the FF 201 to indicate that the requested data does not exist in the first cache memory. By the output of this FF201, DAR2
The requester is notified that the data set in 50 is invalid data.

At the same time, the cache control circuit 200c operates the selectors 135 and 235.
Instruct a to select AA111, DA211. And again
The CMP140a compares the output of PAR100 with the output of AA111,
140a outputs logic "0" and detects that the requested data does not exist in DA211.

The cache control circuit 200b switches the outputs of the selectors 135 and 235a and repeats the index in order until the CMP 140a outputs a logical "1" and detects the cache memory in which the requested data exists.

When the selectors 135 and 235a select AA112 and DA212, respectively, the CMP 140a outputs a logic "1", detects that the requested data exists in the DA212, and notifies the cache control circuit 200c to that effect. The cache control circuit 200c is FF2
01 is set to logic "1", and at the same time, the requested data in the output data from DA212 selected by the selector 235a is set to D
Set it in AR250 and send it to the request source.

Further, even when the requested data exists in the cache memories of the level 1 and the level 3, the index data is indexed in order from the first cache memory until the requested data is found, and the requested data is supplied from the cache memory in which the requested data exists.

Referring to FIG. 5, the cache memory device according to the fifth embodiment of the present invention includes selectors 131 to 133 and a selector 23.
It has a configuration similar to that shown in FIG. 1 except that 1-233 have been deleted.

Next, the operation of the fifth embodiment of the present invention will be described with reference to FIG.

The operation when the requested data exists in the cache memory having the first priority, that is, the level 0 cache memory is the same as that described with reference to FIG.

Next, the cache memory having the first priority, that is,
The requested data does not exist in the level 0 cache memory,
For example, assume that the requested data exists in the level 2 cache memory.

In this case, the CMP 142 outputs a logic "1" and detects that the requested data exists in the DA 212. Therefore, the cache control circuit 200d sets a logical "0" in the FF 201 to indicate that the requested data does not exist in the cache memory having the first priority. The output of this FF201 notifies the request source that the data set in the DAR250 is invalid data.

At this time, the cache control circuit 200d determines that the key address and block data (address / data pair of the level 2 cache memory) at the corresponding address positions of AA112 and DA212 are at the corresponding address positions of AA110 and DA210 (level 0). The following control is performed so that they are respectively replaced (as address / data pairs in the cache memory).

That is, all cache memories having priority levels from the level 0 cache memory having the first priority to the level 2 cache memory in which the requested data exists, that is, the level 0 cache memory having the first priority Cache memory (AA110, DA210), Level 1 cache memory with second priority (AA111, DA211), Level 2 cache memory with third priority (AA112, DA21)
The address data pairs (key address and block data) on the same index address in 2) are replaced according to this priority.

First, address data pairs of levels 0 to 2 are simultaneously read out, and the key address of AA112 and the block data of DA212 including the requested data are newly selected as the address data pair having the first priority and the selector 130 and the selector. 2
It is set to AAW120 and DAW220 through 30 respectively.
The key address of AA110 and the block data of DA210 are stored in AAW121 and DAW221, respectively, and the key address of AA111 and DA21.
The block data of 1 is set in AAW122 and DAW222, respectively. Then, the contents of the AAWs 120 to 122 and DAWs 220 to 222 are written in the corresponding address positions of the AA 110 to 112 and DA 210 to 212, respectively, and the replacement process of the cache memory between level 0 and level 2 is completed.

By this replacement processing, the requested data has been registered in the level 0 cache memory, and the cache index is performed again, so that the requested data is read out to the DAR250, and it is displayed that there is valid data in the DAR250.
It is sent to the request source together with the flag.

Further, the requested data does not exist in the level 0 cache memory having the first priority, and the level 1 or level 3
In the same way, even if the requested data exists in the cache memory of, the replacement processing according to the priority order is performed among all the cache memories from the level 0 cache memory to the level 1 cache memory or the level 3 cache memory. After that, DA21 of the level 0 cache memory
Request data is fixedly supplied from 0.

In this way, it is not necessary to select the cache memory in which the request data is registered and then select the cache memory in which the request data is registered to obtain the request data.

Further, the replacement algorithm according to the priorities among the level 0 to level 3 cache memories in this embodiment exactly matches the LRU algorithm, and the level 0 cache memory having the first priority is replaced by the level 0 cache memory. Address data pairs registered up to the level 3 cache memory having the priority of 4 are always registered in the order of the most recently used address data pair to the least recently used address data pair. To be kept as.

Therefore, when there is no address / data pair including the requested data in all the level 0 to level 3 cache memories and it is necessary to rewrite any address / data pair of the level 0 to level 3 cache memories. In the LRU
It is necessary to select the rewrite level by the replacement algorithm circuit that uses an algorithm, etc., and the cache memory of level 3, which has the lowest priority, is always AA.
Address / data pairs of 113 and DA213 can be automatically determined as the rewrite target.

At this time, a block data transfer request is issued to the main memory by the real address held in PAR100. Then, when the block data fetched from the main memory is registered, the replacement process according to the priority order is performed.

First, the upper part of the out-of-block address corresponding to the key address of the real address on PAR100 that issued the block data transfer request to the main memory is set in AAW120 as the key address with the new first priority, AA at the same time
The key address read from 110 to 112 is AAW1
Set to 21-123. On the other hand, the block data retrieved from the main memory is set in the DAW220 as block data having a new first priority, and at the same time DA210 to DA2
The block data read from 12 are DAW221 ~
Set to 223. And AAW120 ~ 123 and DAW220 ~ 2
23 address / data pairs are AA110-113 and DA2 respectively
The data is written in the corresponding address position of 10 to 213, the requested data is read from the DA210 to the DAR250, and sent to the request source.

By the above processing, the level 3 cache memory AA113,
The lowest priority address registered in DA213
The data pair is automatically rewritten.

[Effects of the Invention] As described above, according to the present invention, it is determined in which data array the requested data is registered by indexing the address array and selecting the data array according to the result to obtain the requested data. By eliminating the processing and simplifying the requested data index path from the cache memory that determines the machine cycle, the gate delay is greatly reduced,
This has the effect of shortening the machine cycle of the system.
According to the second aspect of the present invention, the instruction word index and the operand address index are independently assigned to the cache memory, so that the instruction word and the operand independently have the first priority. There is also an effect that the data can be centrally registered in the cache memory and the requested data can be supplied faster than the cache memory having the first priority. Further, in the fifth aspect of the present invention, since the replacement algorithm circuit of the cache memory is not required, the amount of hardware can be significantly reduced and the system can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a cache memory device according to a first embodiment of the present invention, FIG. 2 is a block diagram showing a cache memory device according to a second embodiment of the present invention, and FIG. 3 is a block diagram showing the present invention. 3 is a block diagram showing a cache memory device according to a third embodiment, FIG. 4 is a block diagram showing a cache memory device according to a fourth embodiment of the present invention, and FIG. 5 is a cache memory device according to a fifth embodiment of the present invention. It is a block diagram showing. 100 ... Real address register (PAR), 101 ... I / O flag register (I / O), 110-113 ... Address array (AA), 120-12
3,120a… AA write register (AAW), 130 to 133… selector, 135… selector, 140 to 143,140a… comparator (CMP), 200,20
0a, 200b, 200c, 200d ... Cache control circuit, 201 ... Flip-flop (FF), 210-213 ... Data array (DA), 220
223, 220a ... DA write register (DAW), 235, 235a ... Selector, 240, 240a, 240b ... Selector, 250 ... Data array read register (DAR).

Claims (5)

[Claims] 1. A first to an N-th, each of which holds a plurality of address-data pairs each of which comprises an address and memory data corresponding to the address, and which is given a first to N-th (N ≧ 2) priority order. Cache memory, means for simultaneously indexing the first to Nth cache memories, and if the requested data does not exist in the first cache memory, it exists in a cache memory other than the first cache memory. And a means for replacing the address / data pair to be replaced with the address / data pair of the first cache memory so as to always obtain the requested data from the first cache memory. 2. The first to Nth (N ≧ 2) to the instruction address index, each holding a plurality of address / data pairs each consisting of an address and memory data corresponding to the address.
Number of cache memories to which the first priority order and the first to Nth priority orders for the operand address index are individually assigned, a means for indexing the N cache memories at the same time, and a first priority order When the requested data does not exist in the cache memory, the address / data pair existing in another cache memory other than the cache memory having the first priority and the address / data pair of the cache memory having the first priority. And a means for obtaining request data from a first cache memory having a first priority assigned individually for each instruction address or operand address index. 3. First to Nth (N ≧ 2) cache memories each holding a plurality of address / data pairs each consisting of an address and memory data corresponding to the address, and the first until the requested data exists. Means for continuously indexing from one cache memory to the Nth cache memory, and an address existing in a cache memory other than the first cache memory when requested data does not exist in the first cache memory A cache memory device having means for replacing a data pair with an address / data pair of the first cache memory and always obtaining request data from the first cache memory. 4. First to Nth (N ≧ 2) cache memories each holding a plurality of address / data pairs each consisting of an address and memory data corresponding to the address, and the first until the request data exists. A cache memory device comprising: means for continuously indexing from the first cache memory to the Nth cache memory; and means for obtaining request data from a cache memory in which request data exists. 5. A first to an N-th, each of which holds a plurality of address-data pairs, each of which comprises an address and memory data corresponding to the address, and which is given a first to N-th (N ≧ 2) priority order. No request data exists in the cache memory and the first cache memory,
When request data exists in a cache memory other than the first cache memory, the first cache memory is configured so that the address / data pair including the request data is replaced by the first cache memory. To the cache memory in which the address / data pair including the requested data exists, the address / data pairs of all the cache memories having the priority order are replaced according to the priority order, and the requested data is always sent from the first cache memory. A cache memory device comprising means for obtaining and a means for selecting an address / data pair of a cache memory having the lowest priority as a replacement target when requested data does not exist in all the cache memories.