JPH07117951B2 - Micro computer - Google Patents

Description

The present invention relates to a microcomputer, and more specifically to a microcomputer having a function of generating a pulse signal such as a pulse for driving a pulse motor.

[Prior art]

Conventionally, when a pulse signal is generated by a microcomputer for the purpose of driving a pulse motor, for example, processing of the pulse signal by software processing of the CPU, specifically, the waveform of each elementary pulse forming the pulse signal The composition and the generation interval are controlled.

[Problems to be solved by the invention]

However, for example, when the pulse motor is rotated at a high speed, it is necessary to synthesize the waveforms of the elementary pulses at an extremely high frequency and to control the generation timing and output. For this reason, the CPU has little room to perform other software-like processing. Therefore, even if there is an interrupt request or the like with a very high degree of urgency, it cannot be responded immediately, and so-called real-time responsiveness deteriorates.

The present invention has been made in view of such circumstances,
Even if you do almost no software processing by the CPU,
An object of the present invention is to propose a microcomputer capable of generating a pulse signal by combining and outputting elementary pulses of arbitrary waveforms at arbitrary time intervals.

[Means for solving problems]

The microcomputer of the present invention stores in advance a data sequence of various patterns and various pattern data sequences of waveforms at the generation intervals of the elementary pulses forming the pulse signal in the memory, and sequentially from the set start address. Data of the generation interval is given to the timer, and each time is elapsed, and each time the time is completed, waveform data is sequentially read from the set start address and the elementary pulse is synthesized and output.

The present invention, in a microcomputer for outputting a pulse signal, a memory storing a series of generation interval data defining the waveform data of elementary pulses constituting the pulse signal and the generation interval thereof, and the series of generation interval data described above. A first register in which an arbitrary start address in the memory is set, a first address counter which sequentially generates addresses from the start address set in the first register, and an arbitrary in the memory of the waveform data Second register in which the start address of the first address counter is set, a second address counter that sequentially generates addresses from the start address set in the second register, and an address generation interval of the first address counter It includes a timer register to which data is set, and A timer for generating next-order addresses in the first address counter and the second address counter, a pulse signal generation circuit for generating and outputting a pulse signal from given waveform data, and a second address counter for generating A dedicated bus for transferring waveform data of an address from the memory to the pulse signal generating circuit.

[Action]

In the microcomputer of the present invention, by setting the start address of the data of the generation interval of each elementary pulse forming the pulse signal and the start address of the waveform data, the elementary pulse of any waveform is synthesized at any time interval. It is possible to output and generate a pulse signal.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing its embodiments.

The figure is a block diagram showing a configuration of a main part of a microcomputer according to the present invention.

In the figure, reference numeral 1 is a memory, specifically a RAM, for storing a waveform data sequence of elementary pulses for driving a pulse motor and its generation interval data sequence.

The waveform data sequence and the generation interval data sequence are, for example, waveforms and generations of each elementary pulse of a series of pulse signal patterns corresponding to various situations such as starting, stopping, constant speed operation, and speed change of the pulse motor. This is a data string of intervals. Therefore, various patterns of drive control can be performed by appropriately combining the two according to the operating status of the pulse motor.

RAM1 is, for example, a CPU via an internal bus not shown.
Etc., the data can be rewritten as necessary, and the real-time bus 2 dedicated to the function of generating pulse signals is connected. The waveform data and the generation interval data are sent to the real-time bus 2. .

In addition, the address register 3 is attached to the RAM1. this
The RAM address register 3 stores the RAM address given from the generation interval data address counter 6 and the waveform data address counter 8 to be described later via the real-time bus 2, and the RAM 1 address stored in the RAM address register 3 is accessed. RAM1
The data of the corresponding address is transmitted from the to the real time bus 2.

Reference numeral 4 in the figure is a reload timer, which is composed of a system clock generation circuit 41, an up counter 42, a timer register 43, and the like. The reload timer 4 counts the system clock generated by the system clock generation circuit 41 by the up counter 42, and the count value is counted by the timer register 43.
When the value matches the value set in, the up counter 42 outputs the time counting end signal EC. The clock end signal EC is a gate provided between the up-counter 42 and the generation interval data address counter 6 and the timer register 43 which will be described later.
Is given to 44.

The gate 44 is opened by the timing end signal EC to set the set value of the timer register 43 in the up counter 42.

In the figure, reference numeral 5 is a generation interval data start address register which is a first register, and is a register for the CPU to set any address of the generation interval data string stored in the RAM 1 as a start address. Further, the start address of the occurrence interval data set in the occurrence interval data start address register 5 is the gate 51.
Is given to the generation interval data address counter 6 which is the first address counter.

The occurrence interval data address counter 6 sequentially generates the addresses of the occurrence interval data from the start address of the occurrence interval data given from the occurrence interval data start address register 5 as described above. The address generation by the generation interval data address counter 6 is performed each time a signal is given from the up counter 42, and is transmitted to the real-time bus 2. Then, the address of the occurrence interval data sent from the occurrence interval data address counter 6 to the real-time bus 2 is temporarily held in the RAM address register 3.

Therefore, first, the start address of the occurrence interval data set in the occurrence interval data start address register 5 is held in the RAM address register 3 from the occurrence interval data address counter 6 via the real-time bus 2 and corresponds to this address. The occurrence interval data stored in RAM1 is read and held in the timer register 43. Then, the time corresponding to the occurrence interval data held in the timer register 43 is measured by the reload timer 4, and at the time when this time measurement is finished, a signal is given from the up counter 42 to the occurrence interval data address counter 6. The generation interval data address counter 6 generates an address of the next generation interval data.

By repeating such processing, each time the time interval defined by each generation interval data elapses starting from the generation interval data corresponding to the start address set in the generation interval data start address register 5, Sequential occurrence interval data is read from RAM1.

In the figure, 7 is a waveform data start address register which is a second register, and the start address of the waveform data is
Set by CPU. The start address of the waveform data set in the waveform data start address register 7 is given to the waveform data address counter 8 which is the second address counter through the gate 81.

The waveform data address counter 8 sequentially generates the waveform data address from the waveform data start address set in the above-mentioned waveform data start address register 7 and sends it to the real-time bus 2. The address of the waveform data sent to the real-time bus 2 is temporarily held in the RAM address register 3 and the RA address corresponding to this is held.
The waveform data of the address M1 is sent to the real-time bus 2.

Reference numeral 9 denotes a waveform data output buffer, which is a buffer memory for temporarily storing the waveform data sent from the RAM 1 via the realm time bus 2. The waveform data stored in the waveform data output buffer 9 is given to the waveform data output register 10 via the gate 91. The gate 91 is controlled to be opened / closed by the time counting end signal EC output from the up counter 42.

The waveform data output register 10 is the waveform data output buffer 9
The up counter 42 supplies the waveform data stored in 1 to the timing gate 91 which has output the timing end signal EC, and further supplies this to the pulse signal generation circuit 11.

The pulse signal generation circuit 11 synthesizes the digital waveform data given from the waveform data output register 10 into an analog elementary pulse signal and outputs it to the outside, for example, to the control circuit of the pulse motor.

Therefore, when the reload timer 4 finishes elapse of the time corresponding to one generation interval data, the waveform data address counter 8 is provided with the time counting end signal EC from the up counter 42, which causes the waveform data address counter 8 to move to the next order. Generate waveform data address. The address of the waveform data generated by the waveform data address counter 8 is temporarily stored in the RAM address register 3 via the real-time bus 2, and the waveform data of the corresponding address of the RAM 1 is sent to the real-time bus 2. Then, the waveform data sent to the real-time bus 2 is stored in the waveform data output buffer 9, and when the up-counter 42 outputs the timing end signal EC, the gate data is output.
When 91 is opened, it is given to and stored in the waveform data output register 10. This allows the waveform data output register
The waveform data as digital data stored in 10 is given to the pulse signal generation circuit 11 and output to the outside as an analog elementary pulse signal.

In the figure, 12 is a real-time bus control circuit, which controls transfer of various signals by the real-time bus 2.

The operation of the microcomputer of the present invention configured as above will be described below.

First, the CPU sets the generation interval data start address register 5 and the waveform data start address register 7, respectively. Both start addresses depend on the current operating state of the pulse motor to be controlled (stopped state, accelerating, decelerating, constant speed operation, etc.), the target state, and the time to achieve that state. Are set respectively.

Then, the generation interval data of the RAM 1 corresponding to the start address of the generation interval data set in the generation interval data start address register 5 is held in the timer register 43, and the time defined by the generation interval data is counted by the reload timer 4. To be done. Upon completion of this time counting, the next interval address is generated from the generation interval data address counter 6, and the corresponding generation interval data of the RAM 1 is sent to the timer register 43 again and held therein.

On the other hand, each time the reload timer 4 finishes counting the time, the waveform data address counter 8 sequentially generates the waveform data addresses starting from the waveform data start address set in the waveform data start address register 7. As a result, the waveform data in the RAM 1 corresponding to each waveform data is read out, applied to the pulse signal generation circuit 11 via the waveform data output buffer 9 and the waveform data output register 10, and output as an analog elementary pulse signal.

As described above, in the microcomputer of the present invention, the time interval determined by the generation interval data is measured by the reload timer 4, and the waveform data is sequentially read from the RAM 1 and the elementary pulse is synthesized and output each time the time measurement ends. Therefore, the generation interval data and the waveform data of various patterns are stored in the RAM 1, and the respective start addresses set in the generation interval data start address register 5 and the waveform data start address register 7 are appropriately set. By selectively setting, a pulse signal for controlling the pulse motor can be generated in response to various situations.

In the above embodiment, the example of generating and outputting the pulse signal for driving the pulse motor has been described in detail, but this is an example, and the present invention can be applied to various control objects that are pulse-driven by the pulse signal. Microcomputer is applicable.

〔effect〕

As described above, according to the microcomputer of the present invention,
Since it is possible to generate a pulse signal with an arbitrary waveform and an arbitrary interval for driving a pulse motor etc. with almost no software processing by the CPU, CP
The load on the software side of U is reduced, and it becomes possible to immediately respond to interrupt requests with high urgency.

[Brief description of drawings]

The figure is a block diagram showing a configuration of a main part of a microcomputer according to the present invention. 1 ... RAM, 2 ... Real timer bus, 4 ... Reload timer, 5 ... Generation interval data start address register, 6 ... Generation interval data address counter, 7 ... Waveform data start address register, 8 ... Waveform Data address counter, 11 ... Pulse signal generation circuit

Claims (1)

[Claims] 1. A microcomputer for outputting a pulse signal, comprising: a memory storing waveform data of elementary pulses constituting the pulse signal and a series of occurrence interval data defining an occurrence period thereof; and a memory of the series of occurrence interval data. A first register in which an arbitrary start address in the memory is set, a first address counter which sequentially generates addresses from the start address set in the first register, and the waveform data in the memory A second register in which an arbitrary start address is set, a second address counter which sequentially generates addresses from the start address set in the second register, and an address which is generated by the first address counter Includes a timer register to which interval data is set, A timer for generating next-order addresses in the first address counter and the second address counter, a pulse signal generation circuit for generating and outputting a pulse signal from given waveform data, and the first and second A memory address register for holding the output of the address counter and accessing the memory; and a waveform of the address generated by the second address counter while transferring the outputs of the first and second address counters to the memory address register. A bus having a dedicated function for generating a pulse signal, which transfers data from the memory to the pulse signal generating circuit, and a microcomputer.