JPH07118151B2 - Envelope detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] A signal read from a magnetic medium such as a magnetic disk device, which is an external storage device of an information processing system, contains many high frequency components, and its waveform is distorted. The present invention relates to an envelope detector that continuously reads out such a waveform and detects an envelope by following a high frequency.

[Prior Art] FIG. 2 is a block diagram showing a conventional envelope detector. 1 is an AC signal source such as a magnetic head for reading digital information from a magnetic disk device, 2 and 3 are comparators, 4 and 5 are flip-flops, 6 is an up / down counter, 7 is a D / A converter,
8 is an integrator.

When the AC signal from the AC signal source 1 is input to the comparator 2 as a comparison input signal, it is compared with another comparison input, zero volt (earth), and when the AC signal crosses the earth level, the so-called zero crossing is performed by the comparator 2. The output is inverted. The output of the comparator 2 is converted to a logic level by the flip-flop 4, and the logic level of the same cycle as the input AC signal is output to the terminal (A) as clock pulses of "0" and "1".

At the same time, the AC signal from the AC signal source 1 is also input to the other comparator 3 as a comparison input, and the output of the integrator 8 output as an envelope signal is used as the comparator 3
Is fed back as the other comparison input, and both are compared to determine whether the peak value of the AC signal is larger or smaller than the fed back envelope signal.

If the output of the comparator 3 is positive when the peak value of the AC signal is smaller than the envelope signal, the output of the comparator 3 is inverted and becomes negative when the peak value of the AC signal is larger than the envelope signal. The flip-flop 5 is for converting the output of the comparator 3 into a logic level. When the output of the comparator 3 is positive, a logic "1",
When it is negative, a logic "0" is output to the terminal (B). The output signal of the flip-flop 5 controls the counting direction of the up / down counter 6 connected to the next stage. When the terminal (B) is logical "1", that is, the peak value of the input AC signal is the envelope signal. When it is smaller, the up / down counter 6 operates up, and the terminal (A)
The clock pulses output to are counted and added. The D / A converter 7 converts the output of the up / down counter 6 output in parallel digital code into an analog value, integrates it with a constant time constant in the integrator 8, and then, as an envelope signal of the input AC signal, the terminal ( At the same time as outputting to C), it is fed back to the comparator 3 and sequentially compared with the peak value of the input AC signal.

On the contrary, in the comparator 3, when the peak value of the input AC signal is larger than the envelope signal fed back from the integrator 8, the output of the flip-flop 5 is set to logic "0", and the up-down counter 6 is set to the down-count operation. The clock pulse input from the terminal (A) is subtracted by counting, and the digital amount of the value obtained by subtracting from the immediately preceding level is output to the D / A converter 7. The D / A converter 7 converts the analog value and then the integrator 8 integrates and outputs the envelope signal reduced from the level immediately before to the terminal (C). At the same time, it is fed back to the comparator 3 and compared with the input AC signal. , So that the difference disappears.

By repeating the above operation, a DC output that always follows the envelope of the input AC signal can be obtained from the output terminal (C).

[Problems to be solved by the invention]

Thus, the envelope detector according to the prior art is
Since the DC output signal corresponding to the envelope is digitally processed by using the up / down counter 6 and the D / A converter 7, in order to improve the detection accuracy of the envelope, the up / down counter 6 and the D / A converter 7 can be used. It is necessary to increase the number of bits of the A converter 7, which is expensive.

Further, when the frequency of the input AC signal becomes high, it becomes difficult for the D / A converter 7 to follow up, so the frequency range is restricted by the performance of the D / A converter 7.

The technical problem of the present invention is to solve such a problem in the conventional envelope detector, and to make it possible to accurately detect the envelope even with a high-frequency AC signal by an inexpensive circuit configuration with a minimum number of parts. Especially.

[Means for solving problems]

The technical measures according to the present invention taken to solve this problem include a first comparator for comparing a plus peak of a high frequency signal with an envelope of the positive side fed back, and a negative peak of the high frequency signal and a feedback. A second comparator for comparing the negative side envelopes, and a third comparator for producing and outputting a true clock signal and a complementary clock signal having opposite phases by zero crossing from the high frequency signal, Provided in the next stage of each of the second comparators,
A plurality of flip-flops that output up / down signals in synchronization with the true and complementary clock signals, and a plus obtained by integrating the up / down signals that are provided after the flip-flops. A feedback unit that feeds back the side envelope to the first comparator and the minus side envelope to the second comparator, the plus side envelope is input to the positive input terminal, and the minus side envelope is input to the negative input terminal. The configuration has at least an operational amplifier.

[Action]

According to this technical means, the positive and negative envelopes fed back from the respective integrators and the positive and negative peaks of the input high frequency signal are respectively compared in the comparator, and the positive envelope is more than the positive peak. If it is larger, a down pulse is output, and if it is smaller, an up pulse is output. When the negative envelope is larger than the negative peak, the down pulse is output, and when the negative envelope is smaller, the up pulse is output. Then, output from the corresponding flip-flop to the integrator provided in the next stage, so that the output of the integrator increases in the case of an up pulse, and the output of the integrator decreases in the case of a down pulse. As a result, the positive and negative envelope voltages following the positive peak value and the negative peak value of the input high frequency signal are obtained. Therefore, by inputting the positive envelope voltage to the positive input terminal of the operational amplifier and the negative envelope voltage to the negative input terminal of the operational amplifier, even if the offset voltage is superimposed on the input high frequency signal, it is not affected. The one-amplitude envelope of the input high frequency signal can be accurately detected.

〔Example〕

Next, practical examples of how the envelope detector according to the present invention is embodied will be described. FIG. 1 is a circuit diagram showing an embodiment of an envelope detector according to the present invention. Reference numeral 9 is a high frequency signal source such as a read signal from a floppy disk device, 10 is a comparator for comparing the positive peak value of the high frequency signal with the envelope, 11 is a comparator for comparing the negative peak value of the high frequency signal with the envelope, 12 Is a comparator for generating a clock signal from a high frequency signal by zero crossing. 13 and 14
Is a flip-flop and integrator for generating up-down pulses for positive envelope detection, 15 and
Reference numeral 16 is also a flip-flop and an integrator for negative envelope detection. Reference numerals 17 and 18 are flip-flops for generating a clock signal for timing comparison, and 19 is an operational amplifier.

The high-frequency signal input from the high-frequency signal source 9 is first compared with the ground level in the comparator 12, and when the high-frequency signal crosses the ground level, the output is inverted, so-called zero-cross, and the clock signal is output as a true output having opposite phases. It is output as a and auxiliary output b. The output signal line of the true output a is connected to the S input terminal of the SR flip-flop 17 and the R input terminal of the SR flip-flop 18 and the clock signal terminal of the D flip-flop 13 provided in the next stage. There is. The output signal line of the complementary output b is S-
It is connected to the R input terminal of the R flip-flop 17, the S input terminal of the SR flip-flop 18, and the clock signal terminal of the D flip-flop 15. Therefore these
The operations of the S / R flip-flops 17 and 18 are opposite, and the output signals c and d have opposite phases.

At the same time, the high-frequency signal input from the high-frequency signal source 9 is input to the positive input terminal of the comparator 10, and the output signal g of the integrator 14 is fed back to the negative input terminal of the comparator 10 to compare them. At this time, the output signal d of the SR flip-flop 18 is input to the enable terminal e of the comparator 10, and the comparator is used for a half cycle of the logic "1" of the clock signal.
10 is made to function, and its function is stopped for half cycle of logic "0". That is, since the cycle of the high frequency signal from the high frequency signal source 9 and the cycle of the clock signal are the same, the comparator 10 compares only the positive half cycle of the high frequency signal with the feedback signal g of the integrator 14.

When the peak value of the high-frequency signal is lower than the feedback signal g, the output signal f from the comparator 10 becomes positive and is output to the D flip-flop 13, and the true output a from the comparator 12 is used as a clock signal to output the output a. An up signal is output from the D flip-flop 13 to the integrator 14 in synchronism with. The integrator 14 integrates the up signal, increases its output signal g, feeds it back to the comparator 10, and compares it again with the high frequency signal. On the contrary, when the peak value of the high frequency signal is larger than the feedback signal g, the output signal f of the comparator 10
Becomes negative, a down signal is output from the D flip-flop 13, and the down signal is integrated by the integrator 14 to reduce the output signal g. By repeating the above operation, the output signal g exhibits a positive half-wave envelope of the high frequency signal.

With a configuration and operation similar to the above, a comparator for high frequency signals
11 is connected to the negative input, the output signal j of the integrator 16 is fed back and connected to the positive input, and when comparing the two, the output c of the S / R flip-flop 17 is connected to the enable terminal of the comparator 11. . Therefore, when the output c is the logic "1", the comparator 11 functions, and when the output c is the logic "0", the function is stopped, but the phase of the output c is inverted with respect to the output d.
In the comparator 11, the negative half cycle of the high frequency signal is compared with the feedback signal j. Since the input terminals of the high frequency signal and the feedback signal j in the comparator 11 are reversely connected to those in the case of the comparator 10, when the feedback signal is larger than the high frequency signal (that is, the absolute value is small), the output signal i is positive. Output to the D flip-flop 15. In the D flip-flop 15, the comparator
Although the signal i is transferred to its output in synchronization with the complementary output b of 12, the output is taken out from the inverted terminal of the D flip-flop 13. The output from 15 becomes a down signal in the flip-flop 13. In the integrator 16,
The down signal is integrated to try to reduce its output signal j. On the contrary, when the high frequency signal is smaller than the feedback signal, the up signal is output from the D flip-flop 15 and the result output signal j integrated by the integrator 16 becomes the peak value of the high frequency signal as in the above operation. We will match and show the negative half-wave envelope of the high frequency signal.

The positive and negative waveforms of a high-frequency signal are generally symmetrical, and although the absolute values of their envelopes are the same, the zero level may be offset and unbalanced. Therefore, the positive envelope signal g is connected to the negative input terminal k of the operational amplifier 19, and the negative envelope signal j is connected to the positive input terminal m of the operational amplifier 19. Now, the voltage of the envelope signal g to which the offset voltage Voff is added is V + Voff, the voltage of the envelope signal j is -V + Voff, and the output voltage of the operational amplifier 19 is Vout.
The resistance value of resistors 20 and 21 is 20kΩ, and the resistance value of resistors 22 and 23 is 10k
If Ω, the potential at the negative input k is (V + Voff) / 3. The operational amplifier has a function of making the negative input terminal and the positive input terminal have the same potential, and the negative input terminal k and the positive input terminal m have the same potential. Therefore, when the current flowing through the resistor 22 is I, 10I = Vout− (V + Voff) / 3 20I = 4V / 3−2Voff / 3 From the above, I = V / 15−Voff / 30 10 (V / 15−Voff / 30 ) = Vout− (V + Voff) / 3 Therefore, Vout = V From this, the output voltage Vout of the operational amplifier 19 can detect the voltage V that matches the one-amplitude envelope of the high-frequency signal regardless of the presence or absence of the offset voltage Voff. it can.

〔The invention's effect〕

As described above, according to the present invention, a comparator, a flip-flop, and an integrator are used to detect the envelope of a high-frequency signal without using an up-down counter or a D / A converter. It can be realized with an inexpensive circuit configuration and the limit of the frequency of response can be increased.

Further, by providing an operational amplifier in which the positive envelope signal is connected to the negative input and the negative envelope signal is connected to the positive input, the envelope of the high frequency signal can be accurately detected regardless of the presence or absence of the offset voltage for the high frequency signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an envelope detector according to the present invention, and FIG. 2 is a block diagram showing a conventional envelope detector. In the figure, 1 and 9 are high-frequency signal sources, 2, 3, 10, 11, and 12
Are comparators, 4, 5, 13, 15, 17, and 18 are flip-flops, 8, 14, and 16 are integrators, and 19 is an operational amplifier.

Claims (1)

[Claims] 1. A first comparator for comparing a plus peak of a high frequency signal with a fed back plus side envelope, and a second comparator for comparing a minus peak of the high frequency signal with a fed back minus side envelope. And a third comparator for producing and outputting a true clock signal and a complementary clock signal having opposite phases from the high-frequency signal by zero crossing, and provided in the next stage of each of the first and second comparators,
A plurality of flip-flops that output up / down signals in synchronization with the true and complementary clock signals, and a plus obtained by integrating the up / down signals that are provided after the flip-flops. A feedback unit that feeds back the side envelope to the first comparator and the minus side envelope to the second comparator, the plus side envelope is input to the positive input terminal, and the minus side envelope is input to the negative input terminal. An envelope detector comprising at least an operational amplifier.