JPH07118191B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a row or column address area that is not a power of 2 in an image memory device or the like.

[Conventional technology]

Conventionally, in a semiconductor memory device, the memory cell array is configured to have a power of 2 for both rows and columns, and the number of addresses of corresponding rows and columns is configured as a power of 2.

FIG. 5 is a block diagram of an example of a conventional 256K-bit dynamic random access memory (hereinafter referred to as DRAM). The memory cell array 501 has a structure of 512 rows × 512 columns,
Rows and columns are selected by the row address decoder 502 and the column address decoder 503, respectively. Address terminals A0 to A8 are connected to the address buffer 504, and the controller 50
The row address strobe signal (below ▲
Row address and column address strobe signal (hereinafter referred to as ▲ ▼) are time-divisionally latched by a row address decoder.
502 and column address decoder 503.
The input / output buffer 506 is controlled by the controller 505.
A write enable signal (hereinafter referred to as ▲ ▼) to the memory cell array 501 via the IO bus and ▲ ▼ bus.
When is low level, writing is performed, and when it is high level, reading is performed and data is input / output to / from an input / output terminal (hereinafter referred to as I / O).

When the memory configured as described above has a memory configuration that is not a power of 2, for example, for an image signal, many problems occur. For simplicity, let's consider the case where the number of lines is 400. The number of address signals required to select 400 rows is 9 bits. However, if 9 bits are used, 512 rows can be selected, so there are combinations of address signals that indicate rows that do not exist. When activating the memory and reading data, for example, the sense amplifier (hereinafter SA) is naturally activated without the word line rising, the column switch (hereinafter YSW) is turned on, and the read amplifier is turned on. It will be activated. However, since the word line is not rising, the digit line level remains at the reference level, and SA
There is a danger that a large current will flow because the level of is not fixed. This also applies to the read amplifier. Even if the column address is not a power of 2, it can be easily estimated that a large current may flow in the input / output buffer 506.

[Problems to be Solved by the Invention]

In the conventional semiconductor memory device described above, when the memory cell array configuration is not a power of 2, the word line rises because it operates in a normal sequence even if a nonexistent row address or column address is input. And YSW are turned on, the SA performs a large current in the I / O buffer, and the time constant driven by the other decoder changes, causing an unexpected operation sequence and malfunction. There is a drawback that

An object of the present invention is to provide a large memory cell array, input / output buffer, etc. even if a combination of address signals that does not physically exist is input when the number of addresses in the memory cell array structure or the corresponding row or column is not a power of 2. It is an object of the present invention to provide a semiconductor memory device capable of preventing a malfunction without passing a current.

[Means for Solving the Problems]

The structure of the present invention corresponds to a memory array in which at least one of rows and columns of a memory cell array is not a power of 2 in a semiconductor memory device in which data is randomly written and read by an address signal input from the outside and the address signal. Determining means for determining whether or not a row or column physically exists, an internal address signal generating circuit for generating an internal address signal, and an address signal generated by the internal address signal generating circuit according to the determination result of the determining means. It is characterized by further comprising address selecting means for selecting the address signal from the outside, and switching means for switching the operation sequence between a normal cycle and an alternative cycle according to the determination result of the determining means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The memory cell array 101 has a structure of 400 rows × 400 columns,
The 400 rows are selected by the row address decoder 102, and the 400 columns are selected by the column address decoder 103. The column address decoder 103 receives the column address signal from the address buffer 104, and the row address decoder 102 receives the row address signal from the address buffer 104 or the refresh address signal from the refresh counter 107 via the address selector 108. To do. In this example, a refresh address counter is used as the internal address generation circuit.

An external address signal is input to the address buffer 104 from the address terminals (hereinafter referred to as A0 to A8), and the controller 10
By the control of 5, the row address at the falling edge of ▲ ▼,
Latch the column addresses at the falling edge of ▲ ▼.
Further, the address signal is determined, and if the combination of addresses does not physically exist in the row or column of the memory cell array, the nonexistent address signal (hereinafter referred to as NA) is set to low level. This NA is input to the address selector 108, the transfer gate 109, and the input / output buffer 106, and the address selector 108 selects either the row address signal from the address buffer 104 or the refresh address signal from the refresh counter 107, Output to the row address decoder 102. When NA is high level, it selects the row address, and when it is low level, it selects the refresh address. The refresh counter 107 generates only the existing row address as the refresh address and counts up each time the refresh address is used. The transfer gate 109 gates the column selection signal from the column address decoder 103 by the NA, and when the NA is low level, the transfer gate is turned off to deselect the column. The output buffer 106 is disabled when NA is low, and the read amplifier or write amplifier is deactivated.

FIG. 2 is a circuit example of the address buffer of FIG.
The row address is set by the row address latch circuit 201.
It is latched in synchronization with the falling edge of ▼. This row address latch circuit 201 includes nine D-type flip-flops (hereinafter D
F), and the reverse phase signal of ▲ ▼ is input to each clock of DF. The column address is latched by the column address latch circuit 202 in synchronization with the falling edge of ▲ ▼. The column address latch circuit 202 has exactly the same configuration as the row address latch circuit 201, and the reverse phase signal of ▲ ▼ is input to the clock input of each DF that constitutes the column address latch circuit 202. The signals latched by the row address latch circuit 201 and the column address latch circuit 202 are output as row and column address signals.
The row address determination circuit 203, the column address determination circuit 204,
It is determined whether or not the row and column address signals are physically present, and after being logically determined by the NOR circuit 205, output as NA.

In this embodiment, since the memory configuration is 400 rows × 400 columns,
A0 is the least significant bit (least significant bit,
LSB) and A8 are the most significant bits (most significant bit, MSB), the 400th row (or column) is 11000111 (LSB), so A8 and A8
When 7 is high level and any one of A4, A5, A6 is high level, it becomes 400 or more. Therefore, the logical product of A7, A8 and the logical sum of A4, A5, A6 are both row and column addresses. Output the logical product of the results. If the address does not exist in either row or column, NA becomes low level.

Next, the operation will be described. When a combination of address signals in which rows or columns of the memory cell array are physically present is input to the addresses A0 to 8, row address signals captured in synchronization with ▲ ▼ and columns captured in synchronization with ▲ ▼ When ▲ ▼ is at a high level, the memory cell array 101 indicated by the address signal is read, and data is output from the I / O. When ▲ ▼ is at a low level, the data input to the I / O is written.

When a combination of address signals in which no rows or columns of the memory cell array physically exist is input to the addresses A0 to 8, NA becomes low level, so the transfer gate
109 is turned off, the input / output buffer 106 is disabled, the address selector 108 selects the refresh signal from the refresh counter 107, and the row address decoder 10
Enter in 2. The memory cell array 101 raises the word line in the row indicated by the refresh counter 107, activates SA, and performs a refresh operation. The input / output buffer 106 is disabled and the YSW is closed, so that it remains in the standby state.

As described above, according to the present embodiment, at least one of the row and the column of the memory cell array is not a power of 2, and the corresponding address number is not a power of 2. Also, by performing a refresh cycle that is normally performed, it is possible to prevent a large current in the SA and the input / output buffer.

FIG. 3 is a block diagram of the second embodiment of the present invention. In this embodiment, an AND gate circuit 110 is used instead of the transfer gate 109 of the first embodiment. This gate circuit 110 is similar to that of FIG.
Is controlled by the nonexistent address signal NA from the column address decoder. When the NA is at the high level, the selection signal from the column address decoder 103 is passed as it is. When the NA is at the low level, all the selection signals from the column address decoder 103 are fixed at the low level. To do.

An address signal is input to the row address decoder 102 from the address selector 108, and one of 400 word lines (hereinafter referred to as WL1 to 400) of the memory cell array is selected. The address selector 108 is controlled by the nonexistent row address signal NRA (hereinafter referred to as NRA) output from the address buffer 104, and outputs the row address signal when the NRA is at a high level and the refresh counter 107 when the NAR is at a low level. Each refresh address signal is selected and output to the row address decoder 102.

Address buffer 104 has A0 to 8 terminals with ▲ ▼,
The row address signal and the column address signal are latched in a time division manner in synchronization with the fall of ▲ ▼. Further, it judges whether or not the latched row and column address signals are present, and outputs NA and NRA. Regardless of the column address signal, the NRA becomes low level when the row address signal does not physically exist, and becomes high level when the row address signal exists. NA becomes low level when at least one of the row and column address signals is not physically present, and is high level when both are present. NRA is input as a select signal to the address selector 108, and NA is input as a control signal for the gate circuit 109 and an enable signal for the input / output buffer 106. The control circuit 105 includes ▲ ▼, ▲ ▼,
Each part is controlled by ▲ ▼, and the input / output buffer 106
Is an IO bus, ▲ ▼ bus for memory cell array 101
In the write cycle where ▲ ▼ is low level
Write the input data from I / O to the memory cell array, and
In the read cycle in which the ▼ is at the high level, the data in the memory cell array 101 is output to the I / O.

FIG. 4 is a circuit example of the address buffer 104 of FIG.

In this embodiment, when the row address is physically present and only the column address is not present, the memory cell array 101 is refreshed by the row address signals input from A0 to A8. It is not necessary to switch the row address to the refresh address even when the judgment of the address is delayed with respect to the judgment of the row address due to the delay of the input timing, the internal delay and its variation, etc. There are advantages such as preventing an increase in time.

Although the refresh counter circuit is used as the internal address generating circuit here, one dummy word line may be provided and an address for selecting the dummy word line may be supplied.

〔The invention's effect〕

As described above, according to the present invention, even if the rows and columns of the memory cell array configuration are not powers of 2 and the number of addresses corresponding thereto is not a power of 2, the addresses corresponding to the rows or columns of the memory cell array are physically It is determined whether or not it exists, and when a combination of address signals that do not physically exist is input, internally generated addresses are used to perform an alternative cycle such as a refresh cycle. There is an effect that a malfunction can be prevented without flowing a large current in the SA and the input / output buffer that occurs when a normal cycle is performed.

[Brief description of drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a circuit diagram of an example of the address buffer 104 of FIG. 1, and FIG. 3 is a block diagram of the second embodiment of the present invention. FIG. 4 is a circuit diagram of an example of the address buffer of FIG. 3, and FIG. 5 is a block diagram of an example of a conventional semiconductor memory device. 101,501 ...... Memory cell array, 104,504 ...... Address buffer, 102,502 ...... Row address decoder, 105,505 ......
Controller, 103,503 ... Column address decoder, 106,5
06 …… input / output buffer, 107 …… refresh counter, 108 …… address selector, 109 …… transfer gate, 110 …… gate circuit, 201 …… row address latch circuit, 202 …… column address latch circuit, 203 …… Row address determination circuit, 204 ... Column address determination circuit, 205 ... NOR circuit, 206, 207, 208 ... Inverter.

Claims (1)

[Claims] 1. A semiconductor memory device for randomly writing and reading data according to an address signal input from the outside, wherein at least one of a row and a column of a memory cell array is not a power of 2, and the address signal corresponds to the memory array. Determination means for determining whether or not a row or column physically exists; an internal address signal generation circuit for generating an internal address signal; and an address signal generated by the internal address signal generation circuit according to the determination result of the determination means, and 2. A semiconductor memory device comprising: an address selecting means for selecting an address signal from the outside; and a switching means for switching an operation sequence between a normal cycle and an alternative cycle according to the judgment result of the judging means.