JPH07118454B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a wiring structure of a semiconductor device such as a VLSI or the like.

[Outline of Invention]

The present invention is a method of manufacturing a semiconductor device such as a VLSI that performs multilayer wiring with a plurality of interlayer insulating films and wiring electrodes, wherein after forming the uppermost wiring layer of the multilayer wiring layers, the multilayer wiring layer is formed. The interlayer insulating film exposed as a mask is removed by RIE or the like, and then a passivation film is formed on the entire surface to reduce the stress generated by the insulating film and suppress the generation of voids in the Al wiring electrode. It is a thing.

[Conventional technology]

As the scale of semiconductor integrated circuits increases, the number of contacts (the number of through holes) for connecting conductors and the wiring length increase rapidly. Among LSIs, especially in the case of logic LSI (gate array), the wiring area occupies 50% of the chip area, and the number of gates accommodated in a chip of the same area depends on the wiring pitch of the multilayer wiring and the number of wiring layers. It is determined. When the number of gates exceeds 10,000, the number of required wirings increases rapidly, the number of gates increases as the number of multilayer wiring structures increases from 2 → 3 → 4. Therefore, the use of the multilayer wiring improves the degree of integration and the degree of freedom in wiring design. Further, the adoption of the multi-layered wiring can shorten the wiring length, reduce the wiring delay due to the wiring resistance and the wiring capacitance, and can be expected to achieve the effect of speeding up. In the future, it is expected that multilayer wiring will be adopted in earnest in order to suppress the expansion of the chip area due to the increase in the number of elements and to develop high-speed devices.

The multi-layer wiring is formed by repeating an interlayer insulating film on a Si substrate and a wiring metal. However, as the wiring is multi-layered, the step difference due to the wiring becomes larger. Further, the wiring and the interlayer insulating film cannot be made so thin in order to reduce the wiring resistance and the stray capacitance. Moreover, as the degree of integration increases and the number of wiring crossings and the number of through holes increase, the unevenness of the surface becomes severe. Therefore, a flattening technique for flattening the surface step is indispensable. There are three objects (methods) for planarization: metal wiring (various lift-off methods), interlayer insulating film (phosphorus glass flow, resin, etch back, bias sputtering) and through hole (tapering, selective deposition).

Multilayer wiring using Al vapor-deposited wiring film is most advantageous in terms of conductivity, ohmic contact with Si, lead bondability, workability, and economical efficiency, and is widely used. (Monthly Semiconductor World 1986.3, PP76-8
3) FIG. 1A shows an Al multi-layer wiring structure formed by a conventional manufacturing method. The three Al wiring layers 2, 4, 6 and the two interlayer insulating layers 3, 5 and the overpassivation layer 7 are formed on the Si substrate 1 in which the active region is formed, and the third Al layer 6 is the Si substrate. 1 is connected to a part.

[Problems to be solved by the invention]

When the Al wiring electrode becomes finer and further multi-layered due to the higher density and higher performance of the VLSI, there arises a problem that voids occur in the Al wiring layer due to the stress of the passivation film. In the electrode structure of FIG. 1A, three insulating layers 3, 5, and 7 are formed on the first Al layer 2 on the right side in an overlapping manner. Therefore, the three insulating layers exert excessive stress on the first Al layer, which causes voids in the Al layer. In particular, if the Al wiring layer is thin, it may be broken due to stress migration, which adversely affects the yield and reliability of the LSI.

[Means for solving problems]

The present invention is a method of manufacturing a semiconductor device such as a VLSI that performs multilayer wiring with a plurality of interlayer insulating films and wiring electrodes, wherein after forming the uppermost wiring layer of the multilayer wiring layers, the multilayer wiring layer is formed. The above problem was solved by removing the interlayer insulating film exposed as a mask by the RIE method or the like and then forming a passivation film over the entire surface.

[Action]

The stress generated by the passivation film depends on the film quality and film thickness. By optimizing each of these values, the stress that occurs can be reduced, but if even a passivation film that suppresses stress generation in such a way overlaps in multiple layers, a large amount of stress will be applied to the wiring electrodes below. Will be given. In the present invention, since such an insulating film overlapping the multilayer on the wiring electrode is removed, the problem that stress is applied to the lower electrode does not occur.

〔Example〕

As shown in FIG. 1A, a multilayer wiring structure having three layers of Al wiring layers 2, 4 and 6 on a Si substrate 1 is obtained by a conventional manufacturing method. The two interlayer insulating layers 3 and 5 are composed of a CVD SiO ₂ layer or a PSG layer, and the third insulating layer 7 of the overpassivation layer is composed of a plasma SiNx layer.

Next, RIE processing is performed on the entire surface using CHF ₃ / O ₂ system gas,
All the passivation film is removed by etching as shown in FIG. 1B. As a result of removing the passivation film using the Al wiring electrode as a mask, the passivation film remains only under and on the side portion of the Al wiring electrode.

Finally, as shown in FIG. 1C, an overpassivation film 8 such as a plasma SiNx film is formed on the entire surface, the overpassivation film 8 on the pad electrode is removed, and a window is opened.

The RIE process of FIG. 1B may be performed without forming the third insulating layer 7 of the overpassivation layer in FIG. 1A.

〔The invention's effect〕

The interlayer insulating film exists only when the Al wiring electrodes cross each other, and since the interlayer insulating film does not exist in the other portions,
Stress due to the interlayer insulating film does not occur in most of the Al wiring. Especially in the case of the Al wiring electrode of the first layer which receives stress of all passivation films, the Al of the second layer or more
In the place where the wiring electrode does not run, only the overpassivation film exists on the wiring electrode, so that the stress applied thereto is extremely low.

By the manufacturing method of the present invention, the stress due to the passivation film is not applied to the wiring electrode, so that the disconnection of the electrode does not occur and the yield and reliability of the semiconductor device are improved.

[Brief description of drawings]

1A, 1B and 1C show a method of manufacturing a semiconductor device of the present invention. 1 ... Substrate, 2 ... First Al layer 3 ... First insulating layer, 4 ... Second Al layer 5 ... Second insulating layer, 6 ... Third Al layer 7 ... Third insulating layer 8 ... Over Passivation film

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having multi-layered interconnections connected to each other through an inter-layer insulation film, wherein after forming an uppermost wiring of the multi-layered interconnections, the inter-layer insulation exposed by masking the multi-layered interconnections. A method of manufacturing a semiconductor device, comprising removing a film and then forming a passivation film.