JPH07118541B2 - Power MOS type field effect transistor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOS used in a switching device or the like.
Type field effect transistor (referred to as power MOSFET).

2. Description of the Related Art A power MOSFET is used in a wide range of fields as an ideal switching element because it is faster and has a higher breakdown resistance than a bipolar transistor which has been widely used as a power element in the past.

The basic cell of the conventional power MOSFET has a sectional structure as shown in FIG. 3, and will be described in detail below assuming that the illustrated power MOSFET is an N-channel type.

In this power MOSFET, P-type diffusion regions 2 for forming a channel region are separately formed in a large number of places in an N-type silicon substrate 1 having a low impurity concentration which serves as a drain region.
An N type source region 3 is formed in two parts of the shape diffusion region 2, and a gate oxide film 4 is formed on the surface of the silicon substrate 1 between the source regions 3 facing each other with the silicon substrate 1 part interposed therebetween. The gate electrode 5 is formed on the film 4, the interlayer insulating film 6 is further formed on the gate electrode 5, and the source electrode 7 is almost on the surface in the relationship of being connected to both the source region 3 and the P-type diffusion region 2. The drain electrode 8 is formed on the entire surface and is formed on the back surface of the silicon substrate 1.

In the power MOSFET having this structure, when a positive voltage is applied to the gate electrode 5 and a channel is formed at the interface between the P-type diffusion region 2 and the gate oxide film 4, electrons pass from the source region 3 to the drain region through the channel. Reaching the surface,
It flows from here toward the drain electrode 8 provided on the back surface.

FIG. 4 shows a schematic view of the power MOSFET viewed from the chip surface. An actual chip has a structure in which thousands of the fine basic cells shown in FIG. 3 are integrated.

In this power MOSFET, the gate electrode 5 is composed of a stripe-shaped portion indicated by a dotted line and a common connection portion commonly connecting one ends thereof, and a wire bonding pad region 9 for a gate electrode is formed in a part of the common connection portion. In addition, the source electrode 7 is formed on almost the entire surface of the silicon substrate and has a bonding pad region 10 for the source electrode in a part thereof. An interlayer insulating film is formed between the source electrode 7 and the gate electrode 5.

As described above, the conventional power MOSFET has a structure in which the source electrode and the gate electrode overlap with each other across the interlayer insulating film over most of the chip.

Problems to be Solved by the Invention In the power MOSFET having such a structure, a capacitor is formed by the source electrode, the gate electrode, and the interlayer insulating film sandwiched therebetween, and the capacitance between the gate and the source increases. Therefore, there are problems that the input power increases and the switching speed decreases.

The present invention solves such a problem, and an object thereof is to reduce the capacitance between the gate and the source, to reduce the input power and to improve the switching speed.

Means for Solving the Problems The power MOSFET of the present invention eliminates the above-mentioned problems, and a channel of a conductivity type opposite to that of the semiconductor substrate is formed in a large number of places of a semiconductor substrate of one conductivity type forming a drain region. A diffusion region for forming a region is formed, a source region of one conductivity type is formed in two parts in the diffusion region, and a gate insulating film is formed on the surface of the semiconductor substrate between the sources facing each other with the drain region interposed therebetween. , A gate electrode is formed in a stripe shape on the gate insulating film, an interlayer insulating film is formed on the gate electrode, and the source electrode is formed in a stripe shape so as to be connected to both the source region and the diffusion region. A drain electrode is formed on the back surface of the semiconductor substrate, and the gate electrode and the source electrode overlap each other in a stripe-shaped region. In the structure in which the source electrode is overlapped with the gate electrode with the interlayer insulating film sandwiched in a common connection portion commonly connecting one end of the stripe shape of the source electrode, and the area of the source electrode is widened in this portion. Is.

Function According to this structure, the area of the overlapping portion between the gate electrode and the source electrode is significantly reduced,
The source-to-source capacitance can be significantly reduced, and the gate-source short-circuit defects due to pinholes in the interlayer insulating film can be reduced. Moreover, since the area of the source electrode is large in the common connection portion of the source electrodes through which a large current flows, an increase in the electric resistance of the source electrode can be alleviated.

EXAMPLE An example of the power MOSFET of the present invention will be described with reference to the structural sectional perspective view of the basic cell shown in FIG. 1 and the schematic plan view of the chip shown in FIG.

In the N-channel power MOSFET shown in FIG. 1, P-type diffusion regions 2 for forming a channel region are separately formed at a large number of places in a low impurity concentration N-type silicon substrate 1 forming a drain region. An N type source region 3 is formed in two parts of the P type diffusion region 2. Then, a gate oxide film 4 is formed on the surface of the silicon substrate between the source regions 3 facing each other with the silicon substrate 1 portion interposed therebetween. A gate electrode 5 of polysilicon is formed in a stripe shape on the gate oxide film 4, and an interlayer insulating film 6 is formed on the gate electrode 5. Further, the source electrode 7 is connected to both the source region 3 and the P-type diffusion region 2.
Are formed in a stripe shape, and the drain electrode 8 is formed on the back surface of the silicon substrate 1.

The shape of the gate electrode 5 and the source electrode 7 as seen from the surface of the chip is a comb shape composed of a stripe-shaped portion and a common connecting portion commonly connecting one end of these as shown in FIG. Are located on opposite sides of each other, and the stripe-shaped portion of the gate electrode 5 and the source electrode 7, the common connection portion of the gate electrodes, the bonding pad region 9 for the gate electrode and the bonding pad region for the source electrode.
In No. 10, the gate electrode 5 and the source electrode 7 are not overlapped, and the stripe-shaped portions of the gate electrode are overlapped with the interlayer insulating film sandwiched only at the common connection portion of the source electrodes 7.

The gate electrode 5 is under the interlayer insulating film, and the interlayer insulating film is removed only on the bonding pad region 9 for the gate electrode to expose the gate electrode 5.

That is, most of the region where the gate electrode 5 and the source electrode 7 do not overlap each other is used, and the source electrode 7 is connected to the gate electrode 5 only at the common connection portion of the source electrodes where the currents flowing through the divided source electrodes are collected. The overlapped structure is used, and the area of the source electrode is widened in this region to reduce the resistance of the source electrode.

In the embodiments, both the source electrode and the source electrode have been described as comb-shaped, but the invention is not limited to this, and both may be fish-bone shaped, or a comb-shaped and fish-bone shaped combination. It may be one.

Effect of the Invention In the present invention, by significantly reducing the overlap area between the gate electrode and the source electrode of the power MOSFET,
The capacitance between the gate and the source and the input power can be significantly reduced as compared with the conventional case. As a result, the charging / discharging time of the gate electrode is shortened and the switching speed of the power MOSFET is accelerated. In addition, the short-circuit defect between the gate and the source, which has been caused by a pinhole or the like in the interlayer insulating film, can be significantly reduced, and the yield can be improved.

[Brief description of drawings]

1 is a structural sectional perspective view showing an embodiment of a basic cell of a power MOSFET of the present invention, FIG. 2 is a schematic plan view of a chip showing an embodiment of a power MOSFET of the present invention, and FIG. 3 is a conventional power FIG. 4 is a perspective view of the structure of a basic cell of a MOSFET, and FIG. 4 is a schematic plan view of a chip of a conventional power MOSFET. 1 ... Silicon substrate, 2 ... P-type diffusion region for channel formation, 3 ... Source region, 4 ... Gate oxide film, 5 ...
Gate electrode, 6 ... Interlayer insulating film, 7 ... Source electrode, 8
...... Drain electrode, 9 ...... Wire bonding pad area for gate electrode, 10 ...... Wire bonding pad area for source electrode.

Claims (2)

[Claims] 1. A diffusion region for forming a channel region having a conductivity type opposite to that of the semiconductor substrate is formed in a large number of locations of a conductivity type semiconductor substrate forming a drain region, and a conductivity region is formed in two portions in the diffusion region. -Shaped source region is formed, a gate insulating film is formed on the surface of the semiconductor substrate between the sources facing each other with the drain region interposed therebetween, and a gate electrode is formed in a stripe shape on the gate insulating film. An interlayer insulating film is formed thereon, a source electrode is formed in a stripe shape so as to be connected to both the source region and the diffusion region, a drain electrode is formed on the back surface of the semiconductor substrate, and the gate electrode is formed. And a common connection portion in which the source electrodes do not overlap each other in the stripe-shaped region and commonly connect one end of the source electrodes in the stripe shape. MOS field effect transistor for power, characterized in that said has a source electrode is the gate electrode overlap sandwiching the interlayer insulating film. 2. The power MOS field effect transistor according to claim 1, wherein the gate electrode is made of polysilicon.