JPH07118726B2 - Comparison device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator mainly used in a digital optical communication system for discriminating an input signal including an offset voltage from a high level signal or a low level signal.

[Conventional technology]

Optical communication is being widely used in various communication fields including a local area network (LAN) because of its excellent feature that it does not receive electromagnetic induction in a transmission path.

By the way, in each of the receiving sections of such an optical communication system, an optical receiving circuit for photoelectrically converting the optical signal and discriminating its logical level content is provided because it is necessary to demodulate the optical signal and grasp the data content thereof. Mandatory.

FIG. 3 shows an example of a conventional discrimination circuit used in such an optical receiving circuit.

As shown in the figure, this discrimination circuit is composed of a comparator 1 and a resistance voltage dividing circuit 2 for setting a comparison reference voltage, and a received signal input via a terminal 3, that is, a photoelectrically converted input. The signal Vin is the non-inverting input (+
Input), and the comparison reference voltage set by the voltage dividing circuit 2, that is, the threshold voltage Vth, is applied to the inverting input (-input) of the comparator 1.

FIG. 4 shows a preferable level relationship between the input signal Vin and the threshold voltage Vth. In such a discrimination circuit, the threshold voltage Vth is the offset of the input signal Vin as shown in FIG. It is preset to a level near the middle of the amplitude of the input signal Vin, taking into account voltage and amplitude.

As a result, from the terminal 4 (FIG. 3) of this discrimination circuit,
Based on the level comparison between the input signal Vin and the threshold voltage Vth by the comparator 1, a signal of logic “0” or logic “1” corresponding to the content of the logic level of the input signal Vin at any time,
The output signal Vout is taken out each time it is received.

[Problems to be solved by the invention]

In the discrimination circuit as shown in FIG. 3, the voltage dividing circuit 2
Since the threshold voltage Vth set by is semi-fixed, as shown in FIG. 4, the threshold voltage Vth and the input signal Vin are
When the level relationship with is kept good, accurate discrimination as described above is possible, but the offset voltage of the input signal Vin changes, and the input voltage with respect to the set threshold voltage Vth is input. When the signal Vin is input to the comparator 1 in the attitude shown in FIG. 5 (a) or FIG. 5 (b), for example, normal discrimination becomes impossible. That is, in such a discrimination circuit, each time the offset voltage of the input signal Vin changes, the threshold voltage Vth must be reset through the voltage dividing circuit 2 which is troublesome.

In optical communication, generally, the signal is attenuated as the length of the optical fiber is increased, and the amplitude of the received signal is also reduced. For example, due to such a phenomenon, the amplitude of the input signal Vin is Is smaller as shown in FIG. 6 (a), the offset voltage is, for example, 6th
The comparator 1 does not operate even if it is slightly displaced as shown in FIG. As a countermeasure, there is a method to prevent the phenomenon of amplification of the received signal by changing the current limiting resistance of the light emitting element (LED) on the transmission side according to the fiber length, but in this case also the replacement of the above resistance is necessary. There is an annoyance.

It is an object of the present invention to provide an optical receiver circuit which can discriminate its logic level contents without being influenced by an offset voltage of an input signal.

[Means for solving problems]

In this invention, the offset voltage ViL is included and the amplitude is (ViH
-ViL: ViH> ViL) In a comparator for discriminating an input signal of a high level or a low level, an integrating circuit for integrating the input signal, and an output of the integrating circuit is applied to an inverting input terminal, A comparator having a signal applied to a non-inverting input terminal via a resistor R6; and a feedback circuit connecting an output terminal of the comparator to a non-inverting input terminal of the comparator via a resistor R7, Set the resistance of resistors R6 and R7 to Vcc- (1+ (R7 / R6)) (ViH-ViL) <ViL <(ViH-ViL) R7 / R6 However, Vcc should satisfy the power supply voltage Vcc> ViH of the comparator. Characterized by the selection.

[Action]

By the level comparison by the comparator, the contents of the logical level can be discriminated regardless of the offset voltage of the received signal (input signal).

〔Example〕

 FIG. 1 shows an embodiment of the present invention.

In the embodiment circuit shown in FIG. 1, 10 is a photodiode for receiving an optical signal transmitted through an optical fiber (not shown) and converting it into an electric signal, and 11 is a photodiode for converting the converted electric signal. An amplifier that amplifies the signal as required, 12 is a resistor R ₄ and a capacitor for amplifying this amplified signal (received signal) S1.
An integrator circuit 13 that performs integration processing based on the time constant of C ₂ outputs the integration-processed signal S2 to the inverting input terminal (-terminal) and the positive feedback signal S3 to the reception signal S1 of its own output. These signals S2 are received by the inverting input terminal (+ terminal) respectively.
A signal S4 which is a comparison output of the comparator 13 is added to a data processing circuit (not shown) in the subsequent stage as a discrimination demodulation output by the optical receiving circuit of the embodiment.

In the circuit of the embodiment, the resistor R ₁ is a current-voltage conversion resistor that converts a current signal generated by photoelectric conversion by the photodiode 10 into a voltage signal, and the resistors R ₂ and R ₃ are the resistors described above. It is a biasing resistor for operating the amplifier 11 in a desired voltage range.

FIG. 2 is a time chart showing an operation example of the embodiment circuit shown in FIG. 1. The specific operation of the circuit will be described in detail below with reference to FIG.

Now, assume that an optical signal is transmitted to the photodiode 10 and a signal as shown in FIG. 2A, for example, is obtained as the amplified signal of the photoelectric conversion signal by the amplifier 11, that is, the received signal S1.

The input of these signals S1, which signal S2 applied to the inverting input terminal of the comparator 13 via the integrating circuit 12 is charged based on the integration time constant of the signal S1 (the time constant of the resistor R ₄ and the capacitor C ₂₎ The signal of the mode shown in FIG. 2 (b) due to repeated discharge, and the signal output from the other comparator 13 through which the comparison output S4 is positively fed back to the signal S1 and applied to the non-inverting input terminal of the same comparator 13. S3 is associated with resistors R ₆ and R ₇ , The signal has the form shown in FIG. 2 (c).

Therefore, the comparison output of the signals S2 and S3 is output from the comparator 13 which constitutes the discrimination circuit in the circuit of the embodiment.
As S4, the logic "0" level (ground level) or the logic "1" level (power supply voltage Vcc level) is shown in the mode shown in FIG. 2 (d) corresponding to the logic level content of the received signal S1.
Will be output.

Here, the voltage of the logical "1" level of the received signal S1 is
The operating characteristics of the circuit of this embodiment will be considered below, where H is H and the voltage of the logical "0" level (= offset voltage) is ViL.

(I). The comparison output S4 is also at the logic "0" level (ground level) during the period when the reception signal S1 is at the logic "0" level (voltage ViL). So in this case, Becomes

(B). In response to the rise of the received signal S1 from the logic "0" level to the logic "1" level (voltage ViH), the signal S
2 and S3 are S2 = ViL However, in order for the comparison output S4 to shift from the logic "0" level to the logic "1" level (power supply voltage Vcc level), S3> S2 must be satisfied. So in this case, Becomes Here, when (R ₇ / R ₆ ) = γ is set, γ (ViH−ViL)> ViL (4) By the way, in this equation (4),
(ViH-ViL) represents the amplitude of the received signal S1, and ViL represents the offset voltage of the signal S1.

(C). Corresponding to the period when the reception signal S1 is at the logic "1" level, the comparison output S4 is also at the logic "1" level (voltage Vcc), and the signal S3 is Becomes However, in order for this signal S3 to maintain such a state, S3> S2 must be satisfied. Therefore, in this case, the relationship of Vcc-ViH> 0 (6) is satisfied.

(D). In response to the fall of the received signal S1 from the logic "1" level to the logic level, the above signals S2 and S3 are respectively S2 = ViH. However, in order for the comparison output S4 to shift from the logic "1" level to the logic "0" level (ground level), S3> S2 must be satisfied. So in this case, ViL> Vcc- (1 + γ) (ViH-ViL) (7) However, γ = R ₇ / R ₆ .

As is clear from the above consideration, the relationship between the amplitude (ViH−ViL) of the received signal S1 and the offset voltage ViL is Vcc− (1 + γ) (ViH−ViL) <from the above equations (4) and (7). ViL <γ (ViH-ViL) ...
Is expressed as in (8), and the circuit constant γ of the circuit of the embodiment is set so that this expression (8) and the above expression (6) are satisfied.
By determining (= R ₇ / R ₆ ) and Vcc (power supply voltage), the above-mentioned operation characteristics are always stable without being affected by the amplitude and offset voltage of the reception signal (input signal) S1. You can see that it will be obtained.

FIG. 7 shows the above power supply voltage Vcc as 5 as a circuit constant.
The relation between the received signal amplitude (ViH-ViL) and the offset voltage ViL in the circuit of this embodiment when [V] and the constant γ as a parameter is shown.

That is, in FIG. 7, for example, the shaded area A is γ =
The operating region of the comparator 13 when 100, and the shaded regions A and B indicate the operating region of the comparator 13 when γ = 300. In FIG. If the received signal amplitude (ViH-ViL) and the offset voltage ViL are within these shaded areas (A or A + B) when the constant γ = 100 or γ = 300, the received signal can be discriminated by the comparator 13. It is shown that. Further, in FIG. 7, the threshold voltage of the comparator 13 is 2.
The operation area of the comparator 13 when it is fixedly set to 5 [V] is also shown as a shaded area C.

As is clear from FIG. 7, in the optical receiving circuit of this embodiment, such a characteristic becomes more prominent as the offset voltage varies and the received signal amplitude becomes smaller. Therefore, according to the optical receiving circuit, the logic level contents can be well discriminated without being affected by the amplitude and offset voltage of the received signal.

〔The invention's effect〕

According to the present invention, the logic level contents can be discriminated by a simple and simple structure without being influenced by the amplitude and offset voltage of the input signal, and the accurate demodulation of the transmitted data is realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing an operation example of the embodiment circuit shown in FIG. 1, and FIG. 3 is adopted in a conventional optical receiving circuit. FIG. 4 is a circuit diagram showing an example of the circuit, FIG. 4 is a time chart showing a good level relationship between the input signal and the threshold voltage in the circuit shown in FIG. 3, and FIG. 5 is inconvenient in the level relationship between the input signal and the threshold voltage. Chart showing the example
FIG. 7 is a time chart showing the level relationship between the input signal having a small amplitude and the threshold voltage, and FIG. 7 is a relationship between the received signal amplitude and the offset voltage when the constant .gamma. Of the embodiment circuit shown in FIG. 1 is used as a parameter. It is a graph which shows. 10 …… photodiode, 11 …… amplifier, 12 …… integrator circuit, 13 …… comparator.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04B 10/26 10/28 H04L 25/06 9199-5K

Claims (1)

[Claims] 1. An offset voltage ViL is included, and an amplitude is (ViH−
(ViL: ViH> ViL) In a comparator for discriminating an input signal of high level or low level, an integrating circuit for integrating the input signal, and an output of the integrating circuit is applied to an inverting input terminal of the input signal. A comparator applied to the non-inverting input terminal via a resistor R6, and a feedback circuit connecting the output terminal of the comparator to the non-inverting input terminal of the comparator via a resistor R7, Set the resistance of resistors R6 and R7 to Vcc- (1+ (R7 / R6)) (ViH-ViL) <ViL <(ViH-ViL) R7 / R6 However, Vcc should satisfy the power supply voltage Vcc> ViH of the comparator. A comparison device characterized by being selected.