JPH07120144B2 - Active matrix liquid crystal display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device including a transistor / capacitor array in each of pixels arranged in a matrix, and more specifically, The present invention relates to such an active matrix type liquid crystal display device having a self-scrolling function.

[Background of the Invention]

In recent years, an active matrix liquid crystal display device has been attracting attention as a large-capacity display device, and a display data reading function has been added to this, and a display device itself has been used as a RAM. An example of such a device is Japanese Patent Laid-Open No.
Those described in Japanese Patent No. 24892 can be mentioned.

However, in this display device, the scroll function of the display is not considered, and when scrolling is performed, the display data is once read to an external RAM, the scroll operation is performed (the display data is rearranged), and the display is performed again. There is a drawback that the processing speed becomes slow because it is necessary to input to the device.

[Object of the Invention]

An object of the present invention is, in an active matrix type liquid crystal display device having a data reading function, scrolling (up / down, left / right, diagonal direction) without using an external RAM and a scroll operation in the RAM, and only using a function that the user has. ) It is to provide an active matrix type liquid crystal display device capable of displaying.

[Outline of Invention]

According to the present invention, in an active matrix type liquid crystal device having a data reading function, the display data of the m-th row is read out and temporarily stored, and this is written in a different n-th row so that vertical scrolling can be performed by itself. Characterize. Similarly, the display data of the m-th row is read out,
It is characterized in that it is temporarily stored, shifted by 1 bit in the row direction, and then written in the same m-th row so that horizontal scrolling can be performed by itself. Further, it is characterized in that the above vertical scroll and horizontal scroll are combined to enable diagonal scroll by itself.

Example of Invention

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the embodiment shown in the figure, a transistor / capacitor array 1 for displaying and storing information, a sense amplifier 2 for reading the information stored in these arrays, a storage circuit 3 for temporarily storing the read information, The address controller 4 controls the read and write addresses of these pieces of information.

Normally, in order to write information in the transistor / capacitor array 1, the information to be written is stored in the storage circuit 3 in advance, and the write location is selected by the address controller 4. By performing this on the entire surface of the array 1, a single screen is displayed.

With the development of the information society, the demand for displaying binary images such as characters and figures is increasing. In these images, scroll display such as moving the entire image on the screen or partially moving the image is frequently performed.

For example, when the image is scrolled in the vertical direction of the screen, if the display content of the nth row of the transistor / capacitor array 1 is moved to the mth row, the information of the nth row is transferred to the sense amplifier 2. The information is read out via the memory and this information is stored in the temporary storage circuit 3. Next, the address controller 4 causes the transistor / capacitor array 1
The m-th row is selected and the information previously stored in the temporary storage circuit 3 is extracted and written. This operation may be repeated for the nth and subsequent rows so as to sequentially move to the mth and subsequent rows.

This will be described in detail with reference to FIG.

FIG. 2 is a circuit diagram showing a concrete circuit example of an embodiment of the present invention. In FIG. 2, reference numeral 5 is a display pixel defined by display electrodes, which are arranged in a matrix to form a display unit 6. Each display pixel 5 is composed of a MOS transistor 7 as a selection switch (switching element) forming a transistor / capacitor array and a capacitor 8, and a liquid crystal element (liquid crystal cell) 9 connected to each capacitor 8, each of which is It is a memory cell.

The operation electrode 10 commonly connecting the gates of the MOS transistors 7 in each row and the signal electrode 11 commonly connecting the drains of the MOS transistors 7 in each column are insulated and separated at each intersection,
They are arranged orthogonally.

An address controller 4 is connected to one end of the scanning electrode 10, and a 1-bit static latch 12 is connected to one end of the signal electrode 11 for each signal electrode via a connection MOS transistor 13. Selection of input information to this latch 12 MOS transistor 1
4, 15 are connected as shown.

To the other end of the signal electrode 11, one node A of the sense amplifier 2 including a gated flip-flop (transistors T _{1 to} T ₅ ) having a differential input is connected.

A dummy line 16 is connected to the other node A ′ of each sense amplifier 2, and a dummy cell 21 including a MOS transistor 17 and a capacitor 18 is connected to this dummy line 16. The gates of the MOS transistors 17 of the dummy cells in each column are commonly connected to the control line 19
It is connected to the.

Reference numeral 20 is a precharge voltage generator for writing a reference voltage in the dummy cell 21. The stray capacitance CA ′ of the dummy line 16 is set to be substantially equal to the stray capacitance CA of the signal electrode 11.

Writing information in this embodiment will be described. For writing, similarly to the conventional example, first, an information signal such as a binary figure having a high level "1" and a low level "0" is input to the drain of the input information selecting MOS transistor 15. At this time, the external information selection signal line 22 is set to the high level. The external information selection signal line 22 is an input information selection MOS transistor 1
Connected to the gate of 5, which latches the input information 1
Input to 2. Then, a signal is given to the information hold signal line 23 connected to each latch 12 to store the input information.

Here, the connection signal line 24 connected to the gate of each connection MOS transistor 13 is set to a high level and the input information is transferred to the signal electrode 11
Output to.

First, the address controller 4 sets the scan electrode 10 connected to the output terminal Y ₁ to a high level, and all the MOS transistors 7 connected on this line are made conductive. Then, the input information output to the signal electrode 11 of each column is accumulated in the capacitor 8 via the MOS transistor 7 of each cell, and the liquid crystal element 9 of each cell is turned on / off according to the input information. The address controller 4 sequentially selects this as the output terminals Y ₂ , ..., Y _n, and gives 1 according to the corresponding input information.
The screen can be displayed.

Next, scrolling according to this embodiment will be described. In this case, vertical (column) scrolling is performed,
Now, it is assumed that the second and subsequent lines are scrolled up by one line.

Generally, it is sufficient to newly write the read information in only one line up. However, even if the charge is stored in the capacitor 8 at the “1” level, the liquid crystal element 9 causes a leak or the like, so that the capacitor 8 is stored with time. The voltage will decrease. Therefore, even if the read voltage is lower than the initially written voltage, in the case of newly writing, the display operation cannot be sufficiently performed unless the initial voltage is written, that is, without refreshing.

First, the precharge voltage generator 20 charges the capacitor 18 of the dummy cell 21 to an intermediate potential between logic levels 1 and 0. Then, the clock C applied to the gate electrode of the MOS transistor T ₃ is set to a high potential to turn on the transistor T ₃ , thereby short-circuiting the nodes A and A ′ of the sense amplifier 2 and connecting the signal electrode 11 and the dummy line 16 to each other. Set to the same potential. As a result, the nodes A and A'of the sense amplifier 2 are in a balanced state near the threshold voltage.

Next, the clock C is set to a low potential and the clock φ is set to a high potential to operate the sense amplifier 2. At the same time, the scan electrode 10 and the control line 19 connected to the output terminal Y ₂ are set to high potential.

Therefore, the MOS transistor 7 becomes conductive, and a voltage change of a value obtained by capacitance-dividing the difference voltage between the voltage of the capacitor 8 and the voltage of the stray capacitance CA of the signal electrode 11 is generated in the signal electrode 11. Dummy cell
Since a voltage change similarly occurs between 21 and the dummy line 16,
The sense amplifier 2 follows the changes of the nodes A and A ', and one of them has a value close to V _DD and the other has a value close to V _SS .

At this time, the internal information selection signal line 25 commonly connecting the gates of the input information selection MOS transistors 14 is set to high level, and the output of the sense amplifier 2 is latched via the signal electrode 11.
Enter from 12 to the bottom.

The connection MOS transistor 13 is kept non-conductive, a signal is applied to the information hold signal line 23, and this information is latched.
Remember in 12.

Next, the clock φ is set to a low potential to bring the sense amplifier 2 into a non-operating state, the scan electrode 10 connected to the output terminal Y ₁ is set to a high potential, and each MOS transistor 7 in this row is brought into a conductive state. Here, the connection MOS transistor 13 is connected to the signal line 24
Is set to a high level to make it conductive. Then, the information stored in the latch 12 is output to the signal electrode 11 and stored in the capacitor 8 of the row of the selected output terminal Y ₁ . After that, the connection MOS transistor 13 is turned off, and the output terminal Y ₁
By setting the level to be low, the information in the second row can be moved to the first row.

By repeating the same operation thereafter, the entire screen or the required number of lines can be scrolled by one line.

Incidentally, the sense amplifier 2, the transistor T ₃ is in the OFF state, 'compares the potential of, A>A' Node A and A if further enhanced A, A <A 'if to a further lower A operation Thus, the signal voltage of the capacitor 8 is refreshed.

FIG. 3 is a block diagram showing a concrete configuration example of the address controller 4 in FIG. In the figure, 26 is a source address counter, 27 is a destination address counter, 28 is a selector, and 29 is an address decoder.

When performing normal writing, an address for instructing which row to write is input as an initial value to the source address counter 26, and the output of this source address counter 26 is output by the selector 28 by the selector 28. Then, this address is input to the address decoder 29. The source address counter 26 and the destination address counter 27 are up / down counters, which count with the clock CK, and the direction control signal line 30.
You can set the direction to count by.

When writing is performed in order from the first row to the nth row, the address indicating the first row is set to the source address counter.
After setting as an initial value to 26, when a signal indicating the count-up is applied to the direction control signal line 30 and the clock CK is input, the high level is sequentially output to the output terminals Y ₁ to Y _n .
Information can be written accordingly.

When performing the scrolling operation, for example, when n lines from the second line onward are scrolled to the first line onward, the address indicating the second line is set to the source address counter 26 and the address indicating the first line is set to the destination address counter 27. Initialize to. In this case, a signal is applied to the direction control signal line 30 so that the counter counts up, and the above-mentioned reading, storing and writing are performed.

In the case of reading, a signal for selecting a source address is applied to the address selector signal line 31. On the other hand, in the case of writing, a signal for selecting a destination address is applied to the address selector signal line 31.

A series of reading, storing, and writing is set as one cycle, and when this is repeated n times, scrolling is completed. In this case, the timing diagrams of the signals of the respective parts in FIGS. 2 and 3 are shown in FIG.
Shown in the figure.

Here, it is assumed that the source address and the destination address are set in advance, the address counters 26 and 27 are set so that the input direction control signal 30 is counted up at a low level, and the selector 28 is also set.
Selects the source address at the low level and the destination address at the high level.

Further, as is apparent from the above description, in the embodiment shown in FIG. 2, the refresh operation can be performed in the same manner as in the conventional case, and the information of the capacitor 8 can be transferred to the scan electrode 10-1.
If one is selected, the sense amplifier 2
It can also be read via.

As described above, in the present embodiment, since scrolling is automatically performed inside the display device, high-speed scrolling that solves the problem of slow display speed, which is a drawback of liquid crystal display, is possible.

FIG. 5 shows a second embodiment of the present invention. Similar to the first embodiment, this embodiment comprises a transistor / capacitor array 1, an address controller 4, a sense amplifier 2 and a temporary storage circuit 3.

In the present embodiment, the configuration of the temporary recording circuit 3 is for connection with a static latch 12 for temporarily storing the information of the previous embodiment.
MOS transistor 13, input information selection MOS transistor 14,
In addition to 15, a right shift MOS transistor 33 and a left shift MOS transistor 32 are provided for enabling the information stored in the latch 12 to be shifted in the left and right directions.

By shifting the information stored in a certain latch 12 in the temporary storage circuit 3 to the right or left and writing it in the other latch 12, horizontal (row) direction scrolling can be performed.

When the entire screen is scrolled right by one column, the scan electrodes connected to the output terminal Y ₁ are the same as in all the embodiments.
10 is set to a high level, and the information in this row is read out to the signal electrode 11 via the sense amplifier 2. Enter this information Select information MO
The S-transistor 14 is turned on, and the latch 12 is input from the lower side and stored.

In this case, similar to the previous embodiment, the connection MOS transistor 13
Is in a non-conducting state. Here, in order to make the right shift MOS transistor 33 conductive, a right shift signal line in which the gates of the right shift MOS transistors 33 are commonly connected
34 is high level. Then, the output of each latch 12 is output from the upper side, passes through the MOS transistor 33, and is connected to the input (lower side) of the latch 12 on the right side of each one.

When a hold signal is applied to the information hold signal line 23, the read information is shifted right by one from the latch 12 to the latch 12.

After that, when the connection signal line 24 is set to the high level and the connection MOS transistor 13 is turned on, the shifted information is stored in the capacitor 8 via the MOS transistor 7 connected to the output terminal Y ₁ . If this is done for all output terminals, horizontal scrolling can be executed. The timing chart in this case is shown in FIG. 6, and the timing chart of the left shift is shown in FIG.

When scrolling to the left, it can be realized by making the left shift MOS transistor 32 conductive in the same manner as described above.

In addition, the vertical scroll described in the first embodiment,
If the above horizontal scroll is combined, diagonal scrolling is also possible. In this case, the operation in which the shift operation is inserted between the storage and the writing of the series of read, storage, and write operations in the first embodiment may be one cycle.

As described above, the present invention has an effect that scrolling vertically and horizontally can be performed at high speed. This effect is important in a binary image display device.

〔The invention's effect〕

According to the present invention, since self-scrolling can be performed only by the own device without the help of an external device, the display data is read from the display device to the external RAM, and the scroll operation in the RAM (the rearrangement of the display data is performed). ) And inputting again to the display device, which does not require a procedure that spans external devices, enables high-speed scrolling, and generally eliminates the CPU display processing that performs the operation of the above procedure. The processing load of can be significantly reduced.

In addition, a display memory (RAM), which was required externally for scrolling, is no longer necessary, and a control circuit that controls the exchange of data between this memory and the display device is inevitably unnecessary, and the configuration is simple and inexpensive. In addition, high performance of the matrix type liquid crystal display device can be achieved.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a concrete circuit example of the embodiment of the present invention, and FIG. 3 is a concrete constitution of the address controller 4 in FIG. FIG. 4 is a circuit diagram showing another embodiment of the present invention, FIG. 6 is a circuit diagram of FIG. 5, and FIG. Timing chart of signals at each part when right shift is performed, FIG.
FIG. 9 is a timing chart of signals at respective parts when performing a left shift in the circuit shown in FIG. Explanation of reference numerals 1 ... Transistor / capacitor array, 2 ... Sense amplifier, 3 ... Temporary storage circuit, 4 ... Address controller, 7 ... Selection switch MOS transistor, 8 ...
Capacitor, 9 ... Liquid crystal element, 10 ... Scan electrode, 11 ...
Signal electrode, 12 …… Latch, 13 …… Connection MOS transistor, 14,15 …… Input information selection MOS transistor, 21 ……
Dummy cell, 26 ... Source address counter, 27 ... Destination address counter, 28 ... Selector,
29 …… Address decoder, 32 …… Left shift MOS transistor, 33 …… Right shift MOS transistor

Claims (2)

[Claims] 1. Each pixel arranged in a matrix includes a liquid crystal cell, a storage capacitor for applying a signal voltage to the liquid crystal cell, and a switching element for writing or reading a signal voltage to or from the capacitor. In the active matrix type liquid crystal display device consisting of, as the addresses of the pixels arranged in a matrix,
A row to which the pixel belongs can be designated as a row address, and a read row address and a write row address can be independently designated, and a row address designating means corresponding to each row belonging to the designated row address. The read / write means for reading or writing the signal voltage in the storage capacitor, and the storage means sufficient to store the signal voltage read from the pixels for one row, and the row addressing means, The read start row address is set and the clock signal supplied from the clock generation source is counted to increase or decrease the set read start row address, and the required read operation is performed depending on the number of the supplied clock signals. A read row addressing means (26) for specifying the number of rows and a write start row By counting the clock signals whose addresses have been set and which are supplied from the clock generation source, the set write start row address is increased or decreased, and the required number of write rows is determined by the number of the supplied clock signals. Write line addressing means to be specified (27)
The read / write means reads out the signal voltages of all the pixels belonging to the read row address set by the read row address designating means, and temporarily stores them in the storage means,
Writing to a pixel belonging to the write row address set by the write row address designating means, then, similar read and temporary storage are performed for the read row address increased or decreased by the clock signal, and increased or decreased by the clock signal. An active-matrix liquid crystal display device characterized in that scroll display is realized by performing similar writing for the written row address. 2. The active matrix type liquid crystal display device according to claim 1, wherein the storage means shifts the stored signal voltage from the pixels for one row to the right in the row direction prior to reading the signal voltage. Alternatively, an active matrix type liquid crystal display device characterized by comprising storage means that can be shifted to the left, thereby realizing horizontal or diagonal scroll display.