JPH0712046B2 - Method for manufacturing field effect transistor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a low noise field effect transistor that can be used in a high frequency band.

2. Description of the Related Art A field effect transistor is considered to be advantageous in a high frequency band because a carrier is an element in which carriers travel due to a drift due to an electric field, and has been actively developed in recent years. A field effect transistor usually has a channel layer formed by using a vapor phase epitaxial substrate or an ion implantation method.
The ion implantation method has advantages such as good in-plane distribution, steep profile, and low cost, and there are already many practical examples.

Hereinafter, a conventional method for manufacturing the above-described field effect transistor will be described with reference to the drawings.

FIG. 2 shows an outline of a conventional method for manufacturing a field effect transistor.

In FIG. 2, 8 is a semi-insulating substrate, 9 is a resist, 10 is a region where impurities are ion-implanted at a low concentration, 11 is a region where impurities are ion-implanted at a high concentration, and 12 is a source electrode.
Reference numeral 13 is a drain electrode, and 14 is a gate electrode. In a high-frequency field effect transistor, the source and drain resistances need to be lowered, and a sufficient gate breakdown voltage is required. Therefore, normally, the element isolation region on the semi-insulating substrate 8 is first protected by a resist 9 and selectively ion-implanted. A low-concentration ion implantation region 10 to be an active layer is formed (Fig. 2a). Next, in order to reduce the source / drain resistance, high concentration ion implantation is performed only in the source / drain formation region, and the high concentration ion implantation region is formed.
11 is formed (Fig. 2b). Source electrode after annealing
12 and the drain electrode 13 are attached (Fig. 2c). Next, so-called recess etching is performed in the gate formation portion to form a recess by etching, and the gate electrode 14 is attached to complete the field effect transistor (FIG. 2d).

Problems to be Solved by the Invention However, in the above-described configuration, the source resistance and the drain resistance are high because the impurities are not in a high concentration near the gate. In addition, when the ion implantation amount is increased to reduce the source resistance and drain resistance, the steepness of the impurity profile cannot be obtained, the gm (voltage amplification factor) decreases near the pinch-off voltage, and the gate breakdown voltage also decreases. Was.

In view of the above-mentioned drawbacks, the present invention provides a method for manufacturing a field effect transistor capable of reducing the source resistance and the drain resistance while maintaining the steepness of the profile of the channel portion and obtaining a sufficient gate breakdown voltage.

Means for Solving the Problems In order to solve the above problems, in the method for manufacturing a field effect transistor of the present invention, first, a low resistance layer having a steep impurity profile is selectively implanted by first ion implantation with a high impurity concentration. And the surface thereof is etched to form a channel layer penetrating the low resistance layer by a second ion implantation with a low impurity concentration.
Performing a third implantation of a high impurity concentration through the channel layer, partially removing the resistance layer between the source and drain electrodes, and exposing the channel layer,
And a step of forming a gate electrode on the exposed channel layer.

Action With this configuration, since the low resistance layer exists in the immediate vicinity of the gate of the field effect transistor, the source and drain resistances are reduced, and low noise can be realized in the high frequency band.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an outline of the manufacturing process of the field effect transistor in the first embodiment of the present invention.

In FIG. 1, 1 is a semi-insulating substrate, 2 is a resist, 3,
31 is a region where impurities are ion-implanted at a high concentration, and 4 is a region where impurities are ion-implanted at a low concentration (however, as a result of double-implantation of high concentration and low concentration, Since it has a high concentration, it is shown as a high concentration region. 5 is a source electrode, 6 is a drain electrode, and 7 is a gate electrode. It is advantageous for the high frequency field effect transistor to reduce the surface resistance while keeping the impurity profile steep. In order to achieve this, the present invention protects the element isolation region with a resist 2, minimizes the acceleration voltage, and performs a first ion implantation with a high impurity concentration to form a shallow low resistance layer on the surface (FIG. 1a). ). Next, the same resist 2 is used to etch the surface to further reduce the depth of the low resistance layer, and the second ion implantation with a low impurity concentration is also performed at the same minimum acceleration voltage. Only the channel layer can be formed (Fig. 1b). A third resist 21 is used as a mask to perform third ion implantation with a high impurity concentration on the source and drain formation portions to reduce the resistance thereof (FIG. 1c). After annealing, the source electrode 5 and the drain electrode 6 are attached, the low resistance layer between the source electrode 5 and the drain electrode 6 is removed, and recess etching is performed to expose the channel layer, and then the gate electrode is formed on the exposed channel layer. This field effect transistor is completed by attaching 7. The field effect transistor manufactured in this manner has a good impurity profile because the active layer is formed at a low acceleration voltage. Since the low resistance layer exists in the immediate vicinity of the gate electrode, the source / drain resistance is low. Since the gate electrode is not in contact with the low resistance layer, it has a high gate breakdown voltage.
The noise figure at GHz was less than 1.7 dB.

EFFECTS OF THE INVENTION As described above, the present invention can realize a field effect transistor capable of low noise operation by providing the steps of high-concentration ion implantation, surface etching, and low-concentration ion implantation. There is a great one.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method for manufacturing a field effect transistor in an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional method for manufacturing a field effect transistor. 1 ... semi-insulating substrate, 2,21 ... resist, 3,31 ... high-concentration ion implantation region, 4 ... low-concentration ion implantation region.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masahiro Hagio, 1006 Kadoma, Kadoma, Osaka Prefecture Matsuda Denshi Kogyo Co., Ltd.

Claims (1)

[Claims] 1. A step of performing first ion implantation with a high impurity concentration on a part of a substrate and etching the surface of the implanted first ion implantation layer, and penetrating the first ion implantation layer. As described above, the second ion implantation with a low impurity concentration is performed to form the second ion implantation layer, and the first and second ion implantation layers are further formed on the source and drain electrode formation portions.
Of the high impurity concentration so as to penetrate the ion implantation layer of
Of the first ion-implanted layer between the source and drain electrodes to expose the second ion-implanted layer, and the exposed second ion-implanted layer.
And a step of forming a gate electrode on the ion-implanted layer, the method for manufacturing a field-effect transistor.