JPH07120635B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device with an improved impurity diffusion layer forming step.

(Prior Art) Conventionally, in the method of introducing impurities in the manufacture of semiconductor devices,
Known techniques include an ion implantation method and a solid phase diffusion method utilizing diffusion from a substance containing impurities. The former is a method of directly implanting ions into the surface of a silicon substrate and then diffusing the ions by heat treatment, and has an advantage that the amount of impurities to be introduced can be electrically controlled accurately. The latter is a method in which an impurity-containing glass film is deposited on a silicon substrate and then the impurities in the glass film are diffused into the silicon substrate by heat treatment, which has the advantage that a relatively shallow diffusion layer can be formed. However, it is not as popular as the ion implantation method industrially.

By the way, it is necessary to form a shallow junction (diffusion layer) in the manufacturing process of a MOS transistor.
AM is made with a junction depth of about 0.25 μm. Furthermore, in the 4Mbit DRAM class, which is expected to be put to practical use in the future, 0.1 μm
It is necessary to have the following junction depth. With the progress of miniaturization of devices as described above and the need to make the diffusion layer in the silicon substrate shallower, the ion implantation method and the solid phase diffusion method have the following problems.

In the ion implantation method, the impurity atoms are physically buried in the silicon substrate, so the distribution of the implanted impurity atoms largely depends on the acceleration energy at the time of ion implantation. In order to make a shallow junction, it is necessary to make a shallow ion implantation distribution, and for that purpose it is important to perform ion implantation with low acceleration energy. However, when implanting ions with low acceleration energy, it is difficult to control the ion flow, and it is difficult to achieve a junction depth of 0.1 μm or less. Further, the ion-implanted impurities need to be activated by a thermal process, and due to the impurity diffusion phenomenon in this thermal process, the diffusion layer becomes wider than immediately after the ion implantation. Furthermore, it is difficult to form a uniform diffusion layer on the inclined surface by the ion implantation method.
Recently, in order to solve the decrease in capacitance due to the miniaturization of elements in MOS capacitors, a technique has been proposed in which a trench is formed in a silicon substrate and a sidewall is used to form a capacitor. It is extremely difficult to uniformly introduce impurities into the side walls of the groove.

On the other hand, in the case of the solid phase diffusion method using the impurity glass as the diffusion source,
There are the following problems. That is, in both cases of boron and arsenic which are generally used as impurities, the diffusion coefficient in the glass is smaller than the diffusion coefficient in the silicon substrate by two digits or more, so that the impurity diffusion in the glass is rate-determining in the solid phase diffusion. Therefore, in order to sufficiently increase the amount of impurities introduced into the silicon substrate, diffusion must be performed at a high temperature.
In this case, as a result, the diffusion layer in silicon expands, making it difficult to form a shallow junction.

(Problems to be Solved by the Invention) As described above, according to the conventional method, the impurity layer having a sufficiently high surface concentration and a sufficiently shallow junction depth can be controlled with good controllability in both the ion implantation method and the solid phase diffusion layer. It was difficult to form.

The present invention has been made in consideration of the above circumstances, and an object thereof is to be able to form an impurity diffusion layer having a sufficiently high surface concentration and a sufficiently shallow junction depth with good controllability,
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can contribute to higher density and higher integration of elements.

[Configuration of Invention] (Means for Solving Problems) The essence of the present invention is basically a solid phase diffusion method, and is formed by a chemical vapor deposition method (CVD method) as a diffusion source of solid phase diffusion. This is to use a thin film of arsenic (As), arsenic (B), phosphorus (P) or the like.

That is, the present invention is a method for manufacturing a semiconductor device including a step of forming an impurity diffusion layer on the surface of a semiconductor substrate, after forming a diffusion mask on the surface of the semiconductor substrate except the region where a diffusion layer is to be formed, A, B or P halide is used as a source gas to selectively form a thin film of As, B or P on the exposed portion of the substrate by a chemical vapor deposition method, and then a heat treatment is performed on the semiconductor substrate from the thin film of As, B or P. Alternatively, it is a method of diffusing P.

(Function) Although the depth of the impurity diffusion layer is limited in the ion implantation method,
In solid phase diffusion, there is no limit to the diffusion layer formed in principle. Further, unlike the case where the impurity-containing glass is used as the diffusion source, the impurities are directly diffused from the thin film made of the impurities to be diffused, so that a sufficient impurity introduction amount can be diffused at a low temperature. Therefore, it is possible to form a very shallow diffusion layer with a sufficient impurity introduction amount by utilizing solid phase diffusion from a thin film of As, B, P or the like. Further, since the solid phase diffusion is used, it is possible to uniformly introduce the impurities into the inclined surface.

(Examples) The details of the present invention will be described below with reference to illustrated examples.

FIG. 1 is a schematic configuration diagram showing a CVD apparatus used in an embodiment method of the present invention. Reference numeral 11 in the figure denotes a vacuum container, and the substrate to be processed supported by the substrate holder 12 is provided in the container 11.
13 are housed. Inside the substrate holder 12, a heater 14 for heating the substrate 13 to be processed is provided. container
A predetermined gas is introduced into the inside of the container 11 through the gas introduction port 15, and the gas inside the container 11 is exhausted through the gas exhaust port 16.

On the other hand, a flash lamp 17 is provided above the container 11. The flash lamp 17 includes a plurality of flash tubes each having an output of 1 kw. Then, the light from the flash lamp 17 is introduced into the container 11 through the light introduction window 18 provided on the upper surface of the container 11, and is irradiated onto the surface of the substrate 13 to be processed.

Next, regarding the formation process of the As diffusion layer using the above apparatus,
This will be described with reference to FIG.

First, as shown in FIG. 2A, a SiO ₂ film (diffusion mask) for device isolation is formed on the surface of a silicon substrate (semiconductor substrate) 21.
A substrate 13 to be processed having 22 formed thereon is prepared and placed on the substrate holder 12 of the CVD apparatus shown in FIG. In this state, Ar or N ₂ was introduced into the container 11 to increase the substrate temperature to 200
Set to ~ 800 ° C.

Then, H ₂ gas was flowed in the container 11 at 10 to 1000 cc / min, and when the substrate temperature was stabilized at the above temperature, AsF ₃ gas was added at 0.1 to 10 cc / mi.
Flow at a flow rate of n for 1 to 3 minutes. AsF ₃ was reduced by underlying Si atoms or hydrogen in the next reaction, and as a result, a thin film 23 of As was formed only on the silicon surface as shown in FIG. 2 (b).

At this time, the As film thickness could be controlled within the range of several Å to about 1000 Å. The substrate on which the As thin film 23 is formed on the silicon surface in this manner is, for example, 600 to 1 by flash annealing in an N ₂ atmosphere.
By heat treatment at a temperature of 400 ° C. for 1 to 60 minutes, the As diffusion layer 24 having a junction depth of 0.1 μm or less could be formed as shown in FIG. 2 (c). More specifically, the As thin film 23 is
With 0 Å formed, heat treatment at 900 ℃ gives a junction depth of 0.1
It is possible to form the diffusion layer 24 having a thickness of μm, and by making the As thin film 23 thinner or lowering the heat treatment temperature,
The diffusion layer 24 having a thickness of 1 μm or less could be formed.

Thus, according to the method of this example, AsF ₃ was used as the source gas.
A thin film 23 of As can be formed on the silicon substrate 21 by the CVD method, and by subsequent flash annealing,
A shallow As diffusion layer (n-type layer) can be formed on the surface of the silicon substrate 21. In this case, the amount of As introduced is sufficiently high and uniform, and an extremely shallow junction depth of 0.1 μm or less can be realized. Further, the introduced amount of As can be set with good controllability by the thickness of the thin film 23, the temperature of flash annealing, and the like. Therefore, MOS
When applied to the manufacture of transistors, it becomes possible to form source / drain regions with a shallow junction depth, which is extremely effective in the manufacture of high-density / high-integrated circuits.

When applied to the manufacture of a MOS transistor, an oxide film for element isolation is formed on a silicon substrate 31 as shown in FIG. 3 (a).
After forming 32, forming the gate electrode 34 through the gate oxide film 33, and further forming the side wall oxide film 35, the As thin film is formed by the CVD method and flash annealing is performed in the same manner as above. As a result, as shown in FIG. 3B, shallow As diffusion layers (n ⁺ layers) 36 and 37 to be the source / drain regions can be formed.

FIG. 4 is a sectional view for explaining a method of another embodiment of the present invention. The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The difference of this embodiment from the above-described embodiments is that the As thin film is formed not only on the silicon surface but on the entire surface of the substrate. That is, in the CVD process shown in FIG. 2B, the AsF ₃ flow rate is 1 to 100 [cc / min],
The As thin film 23 was formed at a H ₂ flow rate of 100 to 10,000 cc / min, a substrate temperature of 150 to 800 ° C., and a deposition pressure of 0.01 torr or more. In this case, as shown in FIG.
An As thin film is also deposited on the O ₂ film 22, and the As thin film is deposited on the entire surface of the substrate.
23 could be formed. Even if this substrate was heat-treated under the same conditions as above, a shallow diffusion layer of about 0.1 μm could be formed.

The present invention is not limited to the method of each of the embodiments described above. For example, the source gas for the CVD is not limited to AsF ₃ , but also AsBr ₃ , AsCl ₃ or AsI ₃ can be used as A gas.
s Thin films can be deposited. Further, it is not limited to the halide of As, but it is also possible to form a thin film of B or P by using a halide of B or P. That is, the present invention is not limited to the diffusion of As, but can be applied to the diffusion of B and P.

Further, after forming the As thin film and before performing the flash annealing, by forming a thin SiO ₂ film or the like on the thin film, it is possible to reduce vapor phase diffusion from the thin film. As a result, As can be more efficiently diffused into silicon. In addition, As as a raw material gas for CVD,
When mixing additive gas with B or P halide,
As the additive gas, at least one kind of Ar, N ₂ , H ₂ or the like may be selected. Further, the diffusion mask is not limited to the silicon oxide film, but other insulating films such as a silicon nitride film can be used. In addition, various modifications can be made without departing from the scope of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, impurities are directly solid-phase diffused from a thin film of As, B or P formed by a CVD method to a semiconductor substrate such as silicon. The impurity diffusion layer having a high surface concentration and a shallow junction depth can be formed with good controllability. Therefore, it is effective for high density and high integration of semiconductor elements.

[Brief description of drawings]

FIG. 1 is a schematic view showing a CVD apparatus used in an embodiment method of the present invention, FIG. 2 is a sectional view showing an impurity diffusion process according to the embodiment method of the present invention, and FIG. MO
Sectional view showing an example applied to manufacture of an S transistor, 4th
The figure is a cross-sectional view for explaining a method of another embodiment of the present invention. 11 ... Vacuum container, 12 ... Substrate holder, 13 ... Substrate, 14 ... Heater, 15 ... Gas inlet, 16 ... Gas outlet, 17 ... Flash lamp, 18 ... Light inlet window ,twenty one……
Silicon substrate (semiconductor substrate), 22 ... Element isolation oxide film (diffusion mask), 23 ... As thin film, 24 ... As diffusion layer.

Claims (7)

[Claims] 1. A step of forming a diffusion mask on a surface of a semiconductor substrate except a region where a diffusion layer is to be formed, and then arsenic,
A step of selectively forming a thin film of arsenic, boron or phosphorus on the exposed portion of the surface of the substrate by chemical vapor deposition using a boron or phosphorus halide as a source gas, and then performing a heat treatment on the substrate from the thin film to arsenic, And a step of diffusing boron or phosphorus. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate, and the diffusion mask is a silicon oxide film. 3. The semiconductor device according to claim 2, wherein the thin film of arsenic, boron or phosphorus is formed only on the surface of single crystal or polycrystalline silicon exposed on the surface of the substrate. Production method. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is heated when the thin film of arsenic, boron or phosphorus is formed. 5. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of argon, nitrogen and hydrogen is mixed as an additive gas with the source gas. 6. A semiconductor device according to claim 1, wherein after the thin film of arsenic, boron or phosphorus is formed, a silicon oxide film is formed on the surface of the substrate before the heat treatment. Production method. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the step of diffusing by the heat treatment includes irradiating the surface of the substrate with light.