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JPH07120652B2 - Semiconductor device - Google Patents
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JPH07120652B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07120652B2
JPH07120652B2 JP25610287A JP25610287A JPH07120652B2 JP H07120652 B2 JPH07120652 B2 JP H07120652B2 JP 25610287 A JP25610287 A JP 25610287A JP 25610287 A JP25610287 A JP 25610287A JP H07120652 B2 JPH07120652 B2 JP H07120652B2
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
silicon nitride
nitride film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP25610287A
Other languages
Japanese (ja)
Other versions
JPH0198231A (en
Inventor
和重 野邉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP25610287A priority Critical patent/JPH07120652B2/en
Publication of JPH0198231A publication Critical patent/JPH0198231A/en
Publication of JPH07120652B2 publication Critical patent/JPH07120652B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Weting (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体チップ表面を保護するためのパッシベー
ションについて改良した半導体装置に関する。
The present invention relates to a semiconductor device having improved passivation for protecting the surface of a semiconductor chip.

〔従来の技術〕[Conventional technology]

従来、半導体装置のチップは最外面保護のために例えば
プラズマ窒化シリコンによるパッシベーション膜が施さ
れている。
Conventionally, a chip of a semiconductor device is provided with a passivation film of, for example, plasma silicon nitride for protecting the outermost surface.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

ところが、従来のプラズマ窒化シリコン膜は、モールド
樹脂との密着性が良く、また、樹脂に発生する応力をチ
ップに伝達し易い硬度を有しているため、チップがモー
ルド樹脂を会して外乱の影響を受け易く、その特性が変
動したり劣化する等の虞れがあった。また、その膜は硬
度的に弱く、樹脂モールドアセンブリ後にクラック等が
発生し易かった。さらに、膜に含有されている多量の水
素がチップに対しその界面において種々作用してチップ
の特性を変動させる問題もあった。よって、従来のプラ
ズマ窒化シリコン膜では充分にチップを保護することが
困難であった。
However, the conventional plasma silicon nitride film has good adhesiveness with the mold resin and has a hardness that easily transmits the stress generated in the resin to the chip, so that the chip meets the mold resin to prevent disturbance. They are easily affected, and there is a risk that their characteristics may fluctuate or deteriorate. Further, the film was weak in hardness, and cracks and the like were likely to occur after the resin mold assembly. Further, there is a problem that a large amount of hydrogen contained in the film acts on the chip in various ways at its interface to change the characteristics of the chip. Therefore, it is difficult to sufficiently protect the chip with the conventional plasma silicon nitride film.

本発明はこのような事情に鑑みてなされたもので、上記
の問題を解消したプラズマ窒化シリコン膜でチップを保
護した半導体装置を提供することである。
The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device in which a chip is protected by a plasma silicon nitride film which solves the above-mentioned problems.

〔問題点を解決するための手段〕[Means for solving problems]

このために本発明は、プラズマ気相成長法により半導体
チップにパッシベーション膜としての窒化シリコン膜を
施して成る半導体装置において、 上記窒化シリコン膜を、屈折率が2.05以上で、且つ1.45
wt%のフッ化アンモニウム水溶液と39.2wt%のフッ化水
素酸を35対1の割合で混合した液による27℃でのエッチ
ングレートが30Å/min以下の条件を満足する材質とし
た。
Therefore, the present invention provides a semiconductor device in which a semiconductor chip is provided with a silicon nitride film as a passivation film by plasma vapor deposition, wherein the silicon nitride film has a refractive index of 2.05 or more and 1.45.
A material that satisfies an etching rate of 30 Å / min or less at 27 ° C. with a solution in which a wt% ammonium fluoride aqueous solution and a 39.2 wt% hydrofluoric acid are mixed at a ratio of 35: 1.

〔実施例〕〔Example〕

以下、本発明の実施例の半導体装置について説明する。
本実施例では、プラズマ気相成長法によりチップに窒化
シリコン膜を成長させる際、原料ガスであるモノシラン
(SiH4)とアンモニア(NH3)の流量比を選択して、形
成された窒化シリコン膜の性質が次の(a)(b)
(c)を満たすようにする。
Hereinafter, a semiconductor device according to an embodiment of the present invention will be described.
In this embodiment, when a silicon nitride film is grown on a chip by the plasma vapor deposition method, the flow rate ratio of monosilane (SiH 4 ) and ammonia (NH 3 ) which are raw material gases is selected to form the formed silicon nitride film. Has the following properties (a) and (b)
Make sure that (c) is satisfied.

(a).シリコンを多量に含むこと。つまり、SixNy
x,yがx/y≧3/4であること。なお、通常の窒化シリコン
はSi3N4で表される。
(A). Contain a large amount of silicon. That is, Si x N y
x and y must be x / y ≧ 3/4. Note that ordinary silicon nitride is represented by Si 3 N 4 .

(b).屈折率が2.05以上(通常は2.0〜2.05)である
こと。
(B). Refractive index of 2.05 or more (usually 2.0 to 2.05).

(c).1.45wt%のフッ化アンモニウム水溶液と39.2のw
t%のフッ化水素酸を35対1の割合で混合した液の27℃
でのエッチングレートが30Å/min以下(通常は100Å/mi
n)であること。
(C) 1.45 wt% ammonium fluoride aqueous solution and 39.2 w
27 ℃ of the liquid which mixed t% hydrofluoric acid in the ratio of 35: 1
Etching rate at 30 Å / min or less (usually 100 Å / mi
n).

このような条件を満足する窒化シリコンのパッシベーシ
ョン膜が施された半導体チップを樹脂モールドしてなる
半導体装置では、膜とモールド樹脂との密着性が低下
し、モールド樹脂に発生する応力のチップへの伝達がほ
とんどなくなる。また、この窒化シリコン膜は硬度的に
強固となり樹脂モールド後においてもクラックが発生す
ることがほとんどない。さらに、膜中の水素含有量が少
ないためチップ界面での水素による特性変動がない。以
上は実験的に実証されている。
In a semiconductor device in which a semiconductor chip having a silicon nitride passivation film satisfying such conditions is resin-molded, the adhesion between the film and the molding resin is reduced, and the stress generated in the molding resin on the chip is reduced. Almost no communication. In addition, this silicon nitride film becomes hard in hardness, and cracks hardly occur even after resin molding. Further, since the hydrogen content in the film is small, there is no change in characteristics due to hydrogen at the chip interface. The above has been experimentally verified.

〔発明の効果〕〔The invention's effect〕

以上から本発明によれば、モールド樹脂の応力のチップ
への伝達性を遮断するようにしたので、外乱要素がモー
ルド樹脂を介してチップへ影響することがなく、チップ
の特性の変動・劣化が防止される。また、パッシベーシ
ョン膜におけるクラックの発生の低減化及びチップ界面
での水素による特性変動の解消等も可能となり、これら
と前記の効果とが奏合され半導体装置の性能が向上す
る。
As described above, according to the present invention, the transmission of the stress of the mold resin to the chip is blocked, so that the disturbance element does not affect the chip through the mold resin, and the fluctuation / deterioration of the characteristics of the chip is prevented. To be prevented. Further, it becomes possible to reduce the occurrence of cracks in the passivation film and to eliminate the characteristic variation due to hydrogen at the chip interface. These effects are combined with the above effects to improve the performance of the semiconductor device.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】プラズマ気相成長法により半導体チップに
パッシベーション膜としての窒化シリコン膜を施して成
る半導体装置において、 上記窒化シリコン膜を、屈折率が2.05以上で、且つ1.45
wt%のフッ化アンモニウム水溶液と39.2wt%のフッ化水
素酸を35対1の割合で混合した液による27℃でのエッチ
ングレートが30Å/min以下の条件を満足する材質とした
ことを特徴とする半導体装置。
1. A semiconductor device in which a semiconductor chip is provided with a silicon nitride film as a passivation film by plasma vapor deposition, the silicon nitride film having a refractive index of 2.05 or more and 1.45.
A material that satisfies the condition that the etching rate at 27 ° C is 30 Å / min or less with a solution in which a wt% ammonium fluoride aqueous solution and a 39.2 wt% hydrofluoric acid are mixed at a ratio of 35: 1. Semiconductor device.
JP25610287A 1987-10-09 1987-10-09 Semiconductor device Expired - Lifetime JPH07120652B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25610287A JPH07120652B2 (en) 1987-10-09 1987-10-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25610287A JPH07120652B2 (en) 1987-10-09 1987-10-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0198231A JPH0198231A (en) 1989-04-17
JPH07120652B2 true JPH07120652B2 (en) 1995-12-20

Family

ID=17287917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25610287A Expired - Lifetime JPH07120652B2 (en) 1987-10-09 1987-10-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07120652B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05196559A (en) * 1992-01-21 1993-08-06 Tadahiro Omi Producing method for standard sample for calibrating measured displacement, standard sample and measuring device and calibrating method
JP4485303B2 (en) * 2004-09-17 2010-06-23 株式会社半導体エネルギー研究所 Method for manufacturing transmissive display device
JP4485302B2 (en) * 2004-09-17 2010-06-23 株式会社半導体エネルギー研究所 Method for manufacturing transmissive display device

Also Published As

Publication number Publication date
JPH0198231A (en) 1989-04-17

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