JPH07120695B2 - Semiconductor integrated circuit inspection device and inspection method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection apparatus and an inspection method for inspecting a plurality of chips simultaneously in parallel at the wafer stage of a semiconductor integrated circuit.

2. Description of the Related Art The degree of integration of semiconductor integrated circuits is increasing year by year, and it takes a long time for this functional test. In addition, the function becomes complicated, and the inspection machine for performing the function inspection is becoming expensive. Therefore, the cost required for functional inspection of semiconductor integrated circuits is increasing year by year. As a method of reducing the inspection cost, there is a simultaneous parallel inspection technique in which a plurality of devices are regarded as one device and various inspection conditions generated by an inspection machine are simultaneously applied to the plurality of devices for inspection.

FIG. 2 shows an inspection method using such a conventional inspection machine. In FIG. 2, a probe is erected simultaneously on the electrodes of the semiconductor integrated circuit chip 1 and the chip 2 on the wafer 8, and the probe erected on the electrode of the chip 1 is connected to the voltage source 3 of the inspection machine. The probe set up on the electrode of is connected to the power source 4 of the inspection machine,
The good ground electrode of is connected to the ground point 5 of the inspection machine. Voltages can be simultaneously applied to the chips 1 and 2 from the voltage source 3 and the voltage source 4 of the inspection machine, and the currents of the two chips can be simultaneously measured.

However, not all chips to be measured at the same time are non-defective chips, and there may be defective chips.
Further, in order to improve the electric characteristics, the substrate potential of the semiconductor integrated circuit is set to be more negative than the ground level.
Are incorporated in the semiconductor integrated circuit chips 1 and 2. The output terminals of the substrate potential generation circuits 6 and 7 are in direct contact with the impurity diffusion layer on the substrate and apply a potential to the substrate. However, if one of the substrate potential generation circuits 6 and 7 of the chip to be measured at the same time is defective and the output part of the substrate potential generation circuit leaks or shorts to the ground point of the chip,
There is a problem in that it is difficult to maintain the substrate potential at a normal potential because a substrate is connected to a chip in which the substrate potential generation circuit operates normally, and a correct function test cannot be performed.

Means for Solving the Problems In order to solve the problems as described above, the present invention provides a method in which a probe is set on a plurality of chips at the same time in a semiconductor integrated circuit wafer stage inspection, and the probe is set on a ground terminal of the plurality of chips. In addition, simultaneous parallel inspection is performed using an inspection machine in which a switch such as a relay capable of disconnecting electrical connection between the probe and the grounding point of the inspection machine is turned on.

Operation With the above configuration, even if a defective chip in which the output part of the substrate potential generation circuit and the ground point are short-circuited within the chip is included in the simultaneous parallel inspection, the ground point of the defective chip is cut from the ground point of the inspection machine. By releasing, the substrate potential can be normally applied to the substrate.

Embodiment An embodiment of the present invention will be described with reference to FIG. In FIG. 1, a probe is simultaneously set up on the electrodes of the semiconductor integrated circuit chip 11 and the chip 12 on the wafer 10. The probe set up on the electrode of the chip 11 is connected to the voltage source 13 of the inspection machine, and the probe set up on the electrode of the chip 12 is connected to the voltage source 14 of the inspection machine. A relay between the probe set up on the ground electrode of the chip 11 and the grounding point 15 of the inspection machine.
18 is connected, and a relay 19 is connected between the probe set up on the ground electrode of the chip 12 and the grounding point 15 of the inspection machine. During the simultaneous parallel inspection of the chip 11 and the chip 12, the relays 18 and 19 are closed. Chip 1
Substrate potential generation circuits 16 and 17 are provided in 1 and the chip 12, respectively, and the substrate potential generation circuits of the chips are inspected before the simultaneous parallel inspection. That is, the relay 19 is opened to inspect the substrate potential generation circuit 16 of the chip 11, then the relay 18 is opened, the relay 19 is closed, and the substrate potential generation circuit of the chip 12 is closed.
Inspect 17 When the substrate potential generating circuits 16 and 17 of both the chip 11 and the chip 12 are good, thereafter, the relays 18 and 19 are closed and various characteristic tests of the chip 11 and the chip 12 can be performed simultaneously in parallel. If the substrate potential generation circuit 17 of the chip 12 is defective, the relay 19 may be opened and the ground electrode of the chip 12 may be disconnected from the inspection machine so as not to adversely affect the substrate potential of the chip 11. Yes, chip 11
Can accurately perform various characteristic tests.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to perform accurate simultaneous parallel inspection of a plurality of chips even if the adjacent chips on the wafer are defective.

[Brief description of drawings]

FIG. 1 is a schematic diagram for explaining an embodiment of the present invention, and FIG. 2 is a schematic diagram for explaining a conventional example. 1,2,11,12 …… Semiconductor integrated circuit chip, 8,10 …… Wafer, 3,4,13,14 …… Inspector voltage source, 5,15 …… Inspector ground point, 6,7 , 16,17 …… Substrate potential generation circuit, 18,19 …… Relay.

Claims (2)

[Claims] 1. A voltage source of an inspection machine is respectively connected to a plurality of probes simultaneously set up on respective electrodes to be inspected of a plurality of chips formed on a wafer, and a plurality of sets are formed on respective ground electrodes of said plurality of chips. 2. A semiconductor integrated circuit inspection device, wherein a plurality of switches capable of disconnecting electrical connection are respectively inserted between the probe and the ground point of the inspection machine. 2. A voltage source of an inspection machine is connected to a plurality of probes simultaneously set up on respective electrodes to be inspected of a plurality of chips formed on a wafer, and a plurality of grounding electrodes are set up on respective ground electrodes of said plurality of chips. Using an inspection machine in which a plurality of switches capable of disconnecting electrical connection are inserted between the probe and the grounding point of the inspection machine, first, the plurality of switches are sequentially closed one by one, and each chip alone Inspecting the substrate potential generation circuit incorporated on the chip for good or bad, and if all the substrate potential generation circuits of the plurality of chips are good products, then close all of the plurality of switches and inspect each of the plurality of chips. Simultaneous parallel testing of multiple chips by applying voltage from the voltage source to the electrodes at the same time, and if the substrate potential generation circuit of any of the chips is defective, respond to the defective chip Said switch opening only, method of inspecting a semiconductor integrated circuit, characterized in that close to the other switches are concurrently examined only good chips that.