JPH0712085B2 - Method for manufacturing insulated gate field effect semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to an insulating gate type electric field effect.
Source region and drain of semiconductor device (called IGFET)
And a method of forming a region.

[0002]

2. Description of the Related Art Conventionally, an insulating gate type field effect semiconductor
As a method of forming the source region and the drain region, thermal expansion is performed.
The powder method or the ion implantation method was known. But heat diffusion
With regard to the method, the depth of the junction was increased by 0.5 to 3 μm.
Increase in parasitic capacitance at the gate, that is, high frequency characteristics
Had the drawback of not being sufficient.

On the other hand, an ion implantation method is known. this is
Precision for fresh halt control of IGFET
Controllable and low temperature makes it highly preferred
It was good. But configure the source and drain
Has a high impurity concentration for forming a shallow junction
It takes 2 to 4 hours per batch,
It was another step towards practical application. Especially at high temperatures
Ion implantation furnaces are expensive, at 500 to 700 million yen.
Method and device that can perform high impurity concentration implantation at one price
Was required.

[0004]

[Problems to be Solved by the Invention]

The present invention relates to an insulating gate type field effect semiconductor device.
As a means for forming a source region and a drain region
Low cost, that is, high productivity, and high impurity concentration.
Doping capable of forming shallow regions
The purpose is to provide a method.

[0006]

SUMMARY OF THE INVENTION The present invention is an insulated gate type device.
A manufacturing method of a field effect semiconductor device, opens on a semiconductor
Forming a film having holes, and plating the semiconductor
To a reactive gas containing a trivalent or pentavalent element
Exposed to 200Å on the surface of the semiconductor in the opening.
Source region and drain region having a depth of ˜0.3 μm
And having a step of forming an insulating Gay
Method for manufacturing a toroidal semiconductor device. Is the summary.

As described above, the present invention is not successful in the conventional method.
The shallow junction that did not happen was turned into plasma by high impurity implantation.
In a reactive gas atmosphere containing impurities to be injected.
Plasma ion implantation (PII or
Plasma ion implantation)
And

The present invention constitutes a source and a drain
Impurity region with junction depth of 200Å-0.3μm, preferred
It is formed at a depth of 800 Å ~ 0.2 μm and its impurities
The concentration is 10 ¹⁹ cm ⁻³ or more, preferably 5 × 10 ¹⁹ to
A shallow junction having 1 × 10 ²¹ cm ⁻³ and high
Characterized by forming an impurity region of pure substance concentration
It

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An insulating gate using the present invention will be described below with reference to the drawings.
An example of manufacturing an itite type field effect semiconductor device will be described. Fig. 1
Shows a manufacturing process of the IGFET used in the present invention. Figure
In terms of surface, first of all, selective oxidation technology for semiconductor substrate
And field insulator (2) 0.5 to 2μ
It was formed to a thickness of m. Further, as shown in FIG. 1 (B).
The gate insulator (4) to a thickness of 100-500Å
Formed of silicon oxide, silicon nitride or a multilayer film of these,
Further, the contact hole (5) is formed by photoetching.
I made it. Furthermore, by the plasma CVD method, semiconductors or
Or a conductor (6) was formed. Form semiconductor as (6)
In that case, the plasma CVD method was used. That is, 100
% Silane is introduced into the reaction furnace at a temperature of 200 to 300 ° C.
And the pressure is 0.05 to 0.2 torr, for example, 0.
1 torr and a high frequency of 13.56 MHz for 5 to 10
In addition to W, the film formation rate should be 1 to 10Å / sec.
Thereby forming a semiconductor film (6) of silicon.

Further, a method of forming this silicon semiconductor film (6)
As the method, the following methods can be adopted.
It That is, if the substrate is a P-type semiconductor, phosphorus or arsenic
₃ or AsH ₃ (PH ₃ or AsH ₃ ) / Si
H ₄ mixed with 0.5 to 2% and introduced, trivalent or pentavalent
The impurity-added semiconductor film has a thickness of 0.2 to 1 μm.
It is a method of forming. In addition, the above PCVD method is the present invention.
Patent application to be filed by a person (Plasma gas phase reactor S5
7.9.25 application According to Japanese Patent Application No. 57-167280)
It was

In addition, instead of this semiconductor (6), a conductor W
Formed by introducing F ₆ or MoCl ₃ as a reactive gas
May be. Further, by mixing these with a silicide gas, Six
Wy or SiXMoy is formed, and phosphorus is contained in this.
It is effective to add the to increase its electrical conductivity.
It was

Next, the source region (10) and the drain
A film having an opening for forming the region (9)
It was formed as follows. That is, the photo etching method
A lead (11) and a gate (7) were formed from the above. After this
The aforementioned PCVD apparatus, PH ₃ or the 0.5% to 2%
Or AsH ₃ diluted with hydrogen or He
Introducing a reactive gas, typically 0.05 to 2 torr
Electricity at 0.1 torr and substrate temperature of 200-600 ° C
Supplying energy to turn the reactive gas into plasma
did. Such plasmatized phosphorus or arsenic is
In the semiconductor (1) because it has been converted to kinetic energy
As impurities forming the source (10) and the drain (9)
So called plasma ion implantation (PII)
Done.

This plasma ion implantation should be performed at a low temperature.
Ukoto can, moreover 1 × ^{10 19} ~ to have you in the shallow area
Impurities can be implanted at a high concentration of 10 ²¹ cm ^−3.
And can be performed on a large area at the same time. High to add
It is economical because the frequency energy is 10 W to 1 kW.
It Moreover, using the method shown below,
The plates can be processed simultaneously. For example,
In a reaction space with a height of 20 cm, a width of 60 cm, and a depth of 60 cm
Place 70 5-inch wafers on the supporter.
A pair of electrodes placed above and below the forest
And discharge impurities from the plasma of the present invention.
70 sheets by putting in, / large amount of production in 0.5 hours
It is possible to produce. The doping at this time is 1
× 10 ¹⁹ to 10 ²¹ cm ^−3, typically 2 × 10 ²⁰
cm ⁻³ impurity region to a depth of 100 Å ~ 0.3 μm
It can be done in advance.

After the plasma ion implantation, 30 again.
No need for plasma treatment with hydrogen only at 0-500 ℃
Removes adhered impurities and pours hydrogen ions into the semiconductor.
In order to neutralize lattice defects and damage,
It is effective when it has an H bond.

After that, these semiconductor substrates are taken out from the device.
Then, an interlayer insulator (12) was formed. Further holes (14)
A second layer wiring (13) was formed. This second layer arrangement
Line (13) also further aluminum as Al _{(CH 2) 3}
It was formed by adding 1-5% of SiH ₄ . Addition
By adding 0.1% to 1% of PH ₃ , contact spa
Forming an aluminum film that does not occur by PCVD method
did.

At this time, before forming this (13), this hole
However, impurities of the same conductivity type are
May be injected to promote ohmic contact.

In the above, the source region and the drain region
On the other hand, impurities were implanted by high-purity shallow injection. Also between layers
Before forming the insulator, in a hydrogen atmosphere at 400 to 800 ° C
To remove the damage caused by plasma method at temperature,
It is effective to perform thermal annealing. At such low temperatures
Neil is effective for making shallow implants. The processing
Since the processing temperature is less than 800 ℃,
No re-diffusion and excellent in energy saving
Is.

When the present invention is applied, on a silicon substrate
It is common to make N-type source and drain regions in
Is. In addition, the channel formation region is an enhancement type,
Even if it is a depletion type,
Even if the method uses a few carriers,
May be used. P on the reverse N-type substrate
A method of implanting boron of the mold may be used. Also the substrate
As for, instead of silicon, GaAs, GaAlA
It is also effective to use compounds such as s and InP.

The present invention is not limited to one IGFET
Uses 1Tr / cell memory and floating gate
Source drain of IC or VLSI such as EPROM
It is also effective for the production of microcomputers
It is also effective for the manufacturing process of.

[0020]

EFFECT OF THE INVENTION In exposing a semiconductor to the plasma of the present invention
Therefore, by implanting impurities from the plasma, the source region,
The drain region could be formed with a shallow depth and a high concentration.
In addition, the feature that productivity can be increased can be obtained.
It was

[Brief description of drawings]

FIG. 1 shows a manufacturing process of an insulating gate type field effect semiconductor device.

Claims (2)

[Claims] 1. Fabrication of an insulating gate type field effect semiconductor device.
A method for forming a film having holes on a semiconductor
Process and trivalent or pentavalent plasma of the semiconductor
Exposed to a reactive gas containing the element of
Has a depth of 200Å-0.3μm on the semiconductor surface
Yusuke that the source region, and forming a drain region, the
Of an insulating gate type field effect semiconductor device characterized by
Manufacturing method. 2. A source region and a drain according to claim 1.
Thermal anneal at a temperature of 400-800 degrees after forming
Insulated gate type field effect semiconductor characterized by performing
Method for manufacturing device.