JPH07120925B2 - Switched capacitor circuit and switched capacitor filter circuit - Google Patents

Description

The present invention relates to a switched capacitor circuit (hereinafter, referred to as SC circuit) and a switched capacitor filter circuit (hereinafter, referred to as SC circuit).
SCF circuit), and particularly to a means for initializing the capacitance of the capacitive element.

[Prior Art] Conventionally, SC circuits have been used for filters, sample-hold circuits, etc. in the fields of audio, communication, servo, etc. Among SC circuits, those configured as filters are called SCF circuits. There is.

FIG. 6 shows a configuration example of a conventional SC circuit.

In this figure, for example, analog switches 10, 12, 14, 16 composed of MOS transistors and a capacitive element 18
It is shown.

Among these elements, analog switches 12 and 14
Is grounded at one end, and the capacitive element 18 is connected between the other ends. One ends of the analog switches 10 and 16 are connected to both ends of the capacitive element 18, and the other ends of the analog switches 10 and 16 are connected to the input / output ends of the SC circuit, respectively.

In this SC circuit, analog switches 12 and 16 are clock φ ₁ , analog switches 10 and 14 are clock φ ₂ ,
Each shall be opened and closed. Further, it is assumed that the clocks φ ₁ and φ ₂ occur at different timings.

Analog switches 12 and 16 are closed by the clock phi _1, when the analog switches 10 and 14 is opened by the clock phi _2, one end of the analog switch 12 of the capacitor 18
Via the analog switch 16 and the other end is connected to the output end. At this time, the electric charge stored in the capacitive element 18 is discharged through the analog switch 16.

Conversely, the analog switches 12, 16 is opened by the clock phi _1, if the clock phi ₂ the analog switches 10 and 14 are closed, one end of the capacitor 18 is grounded through an analog switch 14, the other end It is connected to the input terminal via the analog switch 10. At this time, electric charges are stored in the capacitance element 18 from the outside via the analog switch 10.

Further, FIG. 7 shows an example of the configuration relating to the LPF of the conventional SCF circuit.

In this figure, an operational amplifier 20 including a MOS transistor and having a non-inverting input terminal grounded, and an operational amplifier 20.
A capacitance element 22 and an analog switch 23 that connect the inverting input terminal of 20 and the input end of the SCF circuit, and an analog switch 24 that grounds the input end of the SCF circuit through the analog switch 23.
And the analog switch 26 and the capacitance element 28, the analog switch 30, the analog switch 32 and the capacitance element 34, which short-circuit the inverting input terminal and the output terminal of the operational amplifier 20, respectively, and the connection portion between the analog switch 32 and the capacitance element 34 is grounded. Analog switch 36 is shown.

Of the analog switches shown in this figure, 23,2
It is assumed that 6,32 are opened and closed at different timings by the clock φ ₁ and 24, 30, 36 by the clock φ ₂ .

In this case, the analog switch 23 and 26 by the clock φ _1,
32 is closed, the analog switch 2 by the clock phi ₂
At the timing when 4, 30, 36 are opened, the input is input from the input end to the operational amplifier 20 through the capacitive element 22, and the capacitive elements 28, 30 store charges and are integrated.

Conversely, the clock φ ₁ opens the analog switches 23, 26, 32, and the clock φ ₂ opens the analog switches 24, 30, 36.
Is closed, capacitive element 34 is an analog switch.
The capacitor 36 is grounded, and the capacitive element 22 is grounded by the analog switch 22.

[Problems to be Solved by the Invention] In the SC circuit and the SCF circuit having the above-described configuration, there is a problem that it is difficult to initially set the charge of the capacitive element.

For example, in the SC circuit of FIG. 6, it is impossible to fix the potentials at both ends of the capacitive element 18 at the same time. As a result,
The electric charge accumulated in the capacitive element 18 causes a potential difference across the capacitive element 18. This potential difference causes a defect such as a decrease in dynamic range and occurrence of offset in a circuit including the SC circuit.

Also in the SCF circuit of FIG. 7, for example, a potential difference is generated across the capacitive element 28 for the same reason. During the period when the potential difference is generated, that is, the period when the electric charge of the capacitive element 28 is not zero, it is not possible to realize desired characteristics generally designed on the assumption that the initial electric charge of the capacitive element 28 is zero.
That is, the number of clocks determined by factors such as the gain is required to make the charge of the capacitive element 28 zero, and the characteristic of the period required for this clock is not the desired characteristic.

In addition, when designing SC circuits and SCF circuits, circuit characteristics are generally simulated by a circuit simulator, but at this time, the unspecified initial charge leads to the need for "idle feed" in the simulation. Will take longer.

The present invention has been made to solve the above problems, and it is possible to set the initial charge of the capacitive element and set the initial operation characteristics to desired characteristics.
Another object is to provide an SC circuit and an SCF circuit that can be designed in a shorter time by simulation.

[Means for Solving the Problems] In order to achieve such an object, the SC circuit of the present invention is
The SCF circuit of the present invention is characterized by including an initialization analog switch that short-circuits both ends of the capacitive element in response to an initialization clock generated prior to any clock. Also includes an initialization analog switch that short-circuits both ends of the capacitive element related to the feedback of the operational amplifier in accordance with the initialization clock generated in advance.

[Operation] In the SC circuit of the present invention, the initialization analog switch is opened and closed according to the initialization clock. When both ends of the capacitance element are short-circuited by the initialization analog switch, the electric charge accumulated in the capacitance element is discharged by the initialization analog switch. Therefore, the charge of the capacitive element is initialized at a desired timing by the initialization clock generated prior to any clock.

Further, also in the SCF circuit of the present invention, the initialization analog switch is opened / closed according to the initialization clock. When both ends of the capacitance element related to the feedback of the operational amplifier are short-circuited by the initialization analog switch, the charge accumulated in the capacitance element is discharged by the initialization analog switch.
Therefore, the charge of the capacitive element is initialized at a desired timing by the initialization clock generated prior to any clock.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the drawings. The same components as those of the conventional example shown in FIGS. 6 to 7 are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 shows the configuration of the SC circuit according to the first embodiment of the present invention.

In this figure, an analog switch 38 is connected in parallel with the capacitive element 18.

The operation of this embodiment is shown in FIG. 2, in which the clock φ ₁ for opening / closing the analog switches 12, 16 and the clock φ ₂ for opening / closing the analog switches 10, 14 and the analog Clock φ for opening and closing switch 38
_{and α} are shown as a timing chart.

In this figure, when the clock φ _α falls at time t ₁ , the analog switch 38 is opened accordingly. That is, before this time t ₁ , the analog switch 38 is in the closed state. For example, connect a capacitor and a resistor connected in series in parallel with the power supply, and change the charging voltage of the capacitor to NO.
When it is taken out via T, the output of this NOT becomes H for the time determined by the charging time constant of the capacitor, and then L
Becomes Therefore, by detecting the power-on can generate a clock phi _alpha, this clock phi _alpha can be opened and closed analogue switch 38 as described above.

When the analog switch 38 is closed,
Both ends of the capacitive element 18 are short-circuited. Thus, for example, when the clock phi _alpha is H by power-on, charge stored in the capacitor 18 is discharged via the analog switch 38, the load of the capacitor 18 is to be initialized to zero.

After this, at the predetermined timings t ₂ , t _3, etc., the clocks φ ₁ , φ
₂ rises to H.

At this time, since the analog switch 38 is opened, the operation is the same as that in the stable state of the conventional example shown in FIG. That is, the analog switch 38 is once closed and the capacitive element
Since the normal operation is shifted to after the 18 is discharged, the operation in which the initial charge of the capacitive element 18 is zero from the beginning of the shift to the normal operation, that is, the operation corresponding to the stable time of the conventional example.

Therefore, in this embodiment, it is possible to set the initial charge of the capacitive element 18 to obtain desired characteristics from the beginning of the operation. As a result, it is possible to secure the dynamic range and reduce the offset.

Further, even when designing by simulation, it is not necessary to feed the circuit simulator in an idle manner, so that the simulation can be performed in a shorter time and the verifiability is improved.

FIG. 3 shows the configuration of an SC circuit according to another embodiment of the present invention.

In this figure, the capacitive element 18 and the analog switch 16 are connected in series, and the capacitive element 18 and the analog switch 38 are connected.
Are connected in parallel.

Assuming that the analog switch 16 shown in this figure is opened / closed by the clock φ ₁ and the analog switch 38 is opened / closed by the clock φ _α generated by power-on or the like.
It is possible to set the initial charge of the capacitive element 18 to zero as in the illustrated embodiment. Therefore, also in this embodiment, the same effect as that of the embodiment of FIG. 1 can be obtained.

FIG. 4 shows the configuration of the SC circuit according to the third embodiment of the present invention. In this figure, the analog switch 1
0, the capacitor 18, and the analog switch 16 are sequentially connected in series. Further, an analog switch 38 is connected in parallel with the capacitive element 18.

In this embodiment, the analog switch 10 is opened / closed by a clock φ ₁ , the analog switch 16 is opened / closed by a clock φ ₂ , and the analog switch 38 is opened / closed by a clock φ _α generated by power-on or the like. Therefore, also in this embodiment, the electric charge of the capacitance element 18 is set according to the clock φ _α , and the same effect as that of the embodiment of FIG. 1 can be obtained.

FIG. 5 shows the configuration of the SCF circuit according to the fourth embodiment of the present invention.

In this figure, in addition to the conventional circuit of FIG.
A circuit with an analog switch 40 in parallel with 28 is shown.

Further, the analog switch 40 is opened / closed by a clock φ _α generated by turning on the power supply or the like.

Also in this embodiment, the charge of the capacitive element 28 can be initialized to zero, and desired characteristics designed on the assumption that the initial charge of the capacitive element 28 is zero can be realized immediately after the start of operation. Further, the circuit simulator does not need to be fed in a short time, the simulation time is shortened, and the circuit has improved verifiability.

Although the clock φ _α is generated by turning on the power, it may be generated by other means.

Further, although the LPF is exemplified as the SCF circuit, it goes without saying that another type of filter may be used.

[Effects of the Invention] As described above, according to the present invention, the initial charge of the capacitive element is set to zero, so that the characteristic can be set to a desired characteristic immediately after the start of the operation, and further the design by the simulation can be performed. Can be shortened further.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a switched capacitor circuit according to a first embodiment of the present invention, FIG. 2 is a timing chart diagram showing a clock according to the operation of this embodiment, and FIG. FIG. 4 is a circuit diagram showing a configuration of a switched capacitor circuit according to a second embodiment of the invention, FIG. 4 is a circuit diagram showing a configuration of a switched capacitor circuit according to a third embodiment of the present invention, and FIG. FIG. 6 is a circuit diagram showing a configuration of a switched capacitor filter circuit according to a fourth embodiment of the invention, FIG. 6 is a circuit diagram showing a configuration example of a conventional switched capacitor circuit, and FIG. 7 is a conventional switched capacitor. It is a circuit diagram which shows one structural example of a filter circuit. 18,28 …… Capacitance element 38,40 …… Analog switch for initialization φ ₁ , φ ₂ …… Clock φ _α …… Clock for initialization

Claims (2)

[Claims] 1. A switched capacitor circuit including a predetermined number of analog switches each of which is opened and closed according to a clock, and a capacitive element having at least one end connected to the analog switch, which is generated prior to any of the clocks. A switched capacitor circuit including an initialization analog switch that short-circuits both ends of the capacitive element according to the initialization clock. 2. An operational amplifier, a predetermined number of analog switches each of which opens and closes according to a clock, one end is connected to the output end of the operational amplifier via the analog switch, and the other end is connected to the input end of the operational amplifier. The capacitive element,
A switched capacitor filter circuit including: a switched capacitor including an initialization analog switch that short-circuits both ends of the capacitive element according to an initialization clock generated prior to any of the clocks. Filter circuit.