JPH07120931B2 - Phase synchronization circuit - Google Patents

Description

The present invention relates to a phase locked loop circuit for synchronizing a plurality of frequency dividers with each other.

[Prior Art] In digital signal processing, a system clock with phase synchronization is used.

FIG. 7 is a block diagram of a circuit for dividing the reference clock into two systems of 1 / n and 1 / m.

In the digital signal processing circuit, since it is necessary to perform phase-synchronized data calculation for each clock, a clock that is n, 1 / n (n; integer) times the reference clock is required.

Here, when n and m are mutually prime relative to the reference clock as in the above circuit, it is difficult to create a 1 / n to 1 / m system. Create separately.

[Problems to be Solved by the Invention] At this time, both counters are reset by a reset signal or a load signal S in order to synchronize the phases of the n and m series, but the reset (load) signal is synchronized with the clock signal. There are different types such as a type that does and a type that does not, and the timing to give is often complicated, and in general, the operation time to enable reset is longer than the operation time of the internal F / F. This has the drawback of limiting the operating speed of the counter,
This problem became more serious as the frequency became higher.

The present invention has been made to solve the above problems, and in particular, a phase synchronization circuit that can be phase-synchronized with each other even for frequency dividers used in high-speed digital circuits and having different frequency division ratios. Is intended to provide.

[Means for Solving the Problems] In order to achieve the above object, a phase locked loop circuit of the present invention includes a shift register having a plurality of output terminals and selecting the output terminals according to a frequency division ratio. When the output states of the selected output terminals are all aligned, a condition determining circuit that inverts this and feeds it back to the input terminals of the shift register, and a plurality of frequency dividers each having a different frequency division ratio, An OR circuit that is provided in front of the input terminals of each shift register that constitutes the frequency divider and that outputs the logical sum of the output of the condition determination circuit and the forced synchronization signal, and the phase synchronization of each frequency divider is provided. In the phase synchronization circuit, the phase synchronization circuit according to claim 1 is provided with a divider that outputs the forced synchronization signal having a frequency division ratio corresponding to the least common multiple of the frequency division ratios of the frequency dividers.

Further, according to claim 2, when the frequency division ratio corresponding to the least common multiple of the frequency division ratios of the respective frequency dividers is equal to the frequency division ratio of one of the frequency dividers, the one frequency divider is forced to operate. It is characterized by outputting a synchronizing signal.

First, a frequency divider using a shift register used in the present invention will be described. FIG. 4 (a) shows a shift register and
Comprised of NAND circuit, shift register outputs Q ₁ , Q ₂ , ..., Q
It is a circuit in which the divided signal f becomes 0 when _n is all 1.
Further, FIG. 4 (b) is a circuit which is composed of a shift register and a NOR circuit, and the divided signal f becomes 1 when the outputs Q ₁ , Q ₂ , ..., Q _{n of} the shift register are all 0. . The proof that the above configuration is a frequency divider can be done by logical algebra using a truth table,
The output can be taken from the output of the shift register.

Specifically, the 1/2 divider has the configuration shown in Fig. 5 (a),
The truth table is the first vote (a). Looking at Q ₁ and f, it changes in the same pattern once every two times.

The 1/3 frequency divider has the configuration shown in FIG. 5 (b), and the truth table is shown in Table 1 (b). If you look at Q ₁ , Q ₂ , f, it ’s always 3
It changes in the same pattern once per time. The output can be extracted from various directions in this way.

In general, the 1 / n frequency divider has the configuration shown in FIG. 5 (e) and is composed of shift registers of Q _{1 to} Q _n-1 stages.

The same applies to the configuration of the NOR circuit.

The circuit configuration for forcibly phase-locking the frequency divider of FIG. 5 (e) is shown in FIG. 4 (a) or FIG. 4 (b). In this case as well, the configuration is based on the NAND circuit and the NOR circuit,
The input of the forced phase synchronization signal becomes 0 or 1. FIG. 4 (a) will be described with reference to the truth table of Table 2 (a). When the outputs of the shift register are Q ₁ , Q ₂ , and Q _n-1 and the forced phase synchronization signal 0 is input to Q ₁ , the truth table shows 01… 1, 01… 1.
It turns out that it becomes a 1 / n frequency divider and the first 0 is output n times from the input. FIG. 4 (b) will be described with reference to the truth table of Table 2 (b). The output of the shift register is Q ₁ , Q ₂ ,…, Q
_{When n-1} and the forced phase synchronization signal 1 is input to Q ₁ , 10
0, 10 ... 0 and 1 / n frequency divider, and it can be seen that the first 1 is output n times from the time of input.

As described above, 0 or 1 with 1 clock width is externally applied.
Since the input operation is performed via the OR circuit, the start of the frequency divider can be controlled from the outside. The frequency divider is determined by how many bits the output stage of the shift register has. The external forced phase synchronization signal is an integral multiple of the frequency division ratio of the frequency divider.

Next, mutual phase synchronization for synchronizing the frequency dividers will be described. FIG. 1 shows a mutual phase synchronizing circuit of a frequency divider using a shift register. Also, the output of the 1 / n frequency divider is
Shown in the figure. The 1 / m frequency divider has a period longer than 1 / n and is divided by an integer. When the 1 / n frequency division signal, which is a forced phase synchronization signal, is input to the 1 / m frequency divider, the 1 / m frequency division signal is controlled by the 1 / n frequency division signal and the 1 / m frequency divider starts to synchronize. This will be described using the truth table in Table 3.

The first divided output is output at the m-th bit after 0 is input to Q ₁ . After that, for every mth bit, (a), (b),
(C) and the 1 / m frequency divider operate and repeat 1 / m frequency division. Therefore, the output of the same phase as the 1 / n frequency divider can be taken out from the In terminal of the 1 / m frequency divider, and the 1 / n frequency divider outputs from the terminals of Q ₁ , Q ₂ , ..., Q _m-1 . Outputs shifted by 1 bit, 2 bits, ..., M-1 bits from the output can be taken out.

The above is the outline of the mutual phase synchronization circuit. If n <m
In the case of, it is configured using a divider of n × n ₀ , and 1 / (n ×
A signal of n ₀ ) (n × n ₀ > m: n ₀ is an integer) is used as a forced phase synchronization signal.

[Operation] According to the above configuration, the divider generates the compulsory synchronization signal of the least common multiple of the division ratio of each of the plurality of frequency dividers provided. They can always operate in synchronization with each other.

[First Embodiment] FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit according to the present invention.

The first embodiment is an embodiment for claims 1 and 2. That is, when the switch circuit 17 is in the ON state, the embodiment of claim 1 is provided, and the forced synchronization signal output by the divider according to claim 1 is output from the configuration of the 1 / n frequency divider 1 and the divider 5. .

That is, the divider 5 inputs the output of the 1 / n frequency divider 1 and
A forced synchronization signal having a frequency division ratio corresponding to the least common multiple of the frequency division ratios of the / n frequency divider 1 and the 1 / m frequency divider 3 is output. In the embodiment, the divider 5 has the same 1 / m frequency division ratio as that of the 1 / m frequency divider 3.
The frequency division ratio was used.

Further, when the switch circuit 17 is in the OFF state, the embodiment of claim 2 is adopted, in which the 1 / n frequency divider 1 has a frequency division ratio of 1 / n frequency divider 1 and 1 / m.
It outputs a forced synchronization signal having a frequency division ratio corresponding to the least common multiple of the frequency division ratio of the frequency divider 3.

As shown in the figure, the phase locked loop circuit is roughly divided into a 1 / n frequency divider 1, a 1 / m frequency divider 3, and a divider 5. Here, each of the frequency division outputs output from the 1 / n frequency divider 1 and the 1 / m frequency divider 3 is a positive logic in which the bit is in the "1" state and the system is in the "ON" state.

The 1 / n frequency divider 1 is connected to the shift register 7 and the bit output terminals 7a to 7w (w; the number of bit output terminals connected corresponding to the division ratio n) of the shift register 7 It is composed of a NAND circuit 9 as a discrimination circuit. The clock CLK is input to the clock terminal CK of the shift register 7, and the clock is divided by 1 / n and output from the output terminal 7z. If the frequency division ratio n is 2 and the output of the 1 / n frequency divider 1 is 1/2 frequency division output of the reference clock, only the bit output terminal 7a is used. The output of the NAND circuit 9 is connected to the input terminal In of the shift register 7.

The 1 / m frequency divider 3 has a frequency division ratio that is substantially the same as that of the 1 / n frequency divider 1. NA connected to the shift register 11 and the bit output terminals 11a to 11w (w; the number of bit output terminals connected in correspondence with the division ratio m) of the shift register 11
It is composed of an ND circuit 13. This shift register 11
The clock CLK is input to the clock terminal CK, and this clock is divided by 1 / m and output from the output terminal 11z. Here, the division ratio m is 3, and the output of the 1 / m divider 3 is 1/3 of the reference clock.
Assuming frequency division output, 11a and 11b are used as the bit output terminals.

In addition, in the 1 / m frequency divider 3, the output of the NAND circuit 13 is O
It is connected to one input terminal of the R circuit 15, and the output terminal of the OR circuit 15 is connected to the input terminal 1n of the shift register 11.

Next, the divider 5 outputs the least common multiple of the frequency division ratio n of the 1 / n frequency divider 1 and the frequency division ratio m of the 1 / m frequency divider 3.
Here, since n = 2 and m = 3, the output of the divider 5 is C
1/2 × 1/3 = 1/6 frequency division output for LK. Therefore, the divider 5 has almost the same configuration as the 1 / m frequency divider 3,
Moreover, the output of the NAND circuit is directly connected to the input terminal IN of the shift register as compared with the 1 / m frequency divider 3, and the output 7z of the 1 / n frequency divider 1 is connected to the clock terminal CK of the shift register. Only the points that are different are acceptable.

The output of the divider 5 is passed through the switch circuit 17 used as a forced synchronization signal to the OR by the forced synchronization line 16.
It is connected to the other input terminal of the circuit 15.

The switch circuit 17 is normally connected to the output of the divider 5 as shown.
The connection between the input terminal of the OR circuit 15 and the input terminal is maintained and the configuration of claim 1 is obtained. The 1 / m frequency divider 3 delays the compulsory synchronization signal by the delay time of the elements forming the divider 5 as compared with the 1 / n frequency divider 1. Input it to the input terminal IN of the 1 / m divider 3 and
Shift with the same CLK as frequency divider 1. Therefore, the final output of the 1 / m frequency divider 3 may be delayed by 1 CLK from the final output of the 1 / n frequency divider 1. In this case, in the actual circuit, the final output of the 1 / m frequency divider 3 is taken out from the output terminal immediately before the final output. Thereby, the 1 / n frequency divider 1 and the 1 / m frequency divider 3 can be phase-locked. However, when the element forming the divider 5 is ideal and there is no delay time, this is not necessary. There is also a means for delaying the CLK input to the 1 / m frequency divider 3 within the allowable range. However, a frequency division ratio input that is an integral multiple of the forced synchronization signal input to the 1 / m frequency divider 3 via the OR circuit 15 (for example, the frequency division ratio m of the 1 / m frequency divider 3 in the embodiment is When a forcible synchronization signal with a frequency division ratio of 6 times that of 3, that is, a 1/6 frequency division input) is generated by the 1 / n frequency divider 1, the switch circuit 17 is switched and the connection line 19 is changed.
It is connected to the input of the 1 / m frequency divider 3 and has the structure of claim 2.
Of course, in this case, the 1 / n frequency divider 1 has a frequency division ratio n = 6.

Next, the operation of the above configuration will be described.

As shown in the timing chart of FIG. 2, clock CLK
Based on the above, the 1 / n frequency divider 1 outputs 1/2 frequency division when n = 2. The 1 / m frequency divider 3 outputs 1/3 frequency division when m = 3. These are initially in synchronization with each other at time t1, but are not in phase synchronization with each other because they operate individually.

However, the divided waveforms of 1 / n and 1 / m again rise at almost the same timing at time t2.

Since the divider 5 performs the least common multiple of the 1 / n frequency divider 1 and the 1 / m frequency divider 3, that is, 1/6 frequency division,
The rising edge of the compulsory synchronization signal waveform generated at time t2 is compulsorily input to the input terminal In of the 1 / m frequency divider 3 via the OR circuit 15, whereby the frequency division output of the 1 / m frequency divider 3 is output. Will be forcibly synchronized with the 1 / n frequency divider 1 at time t2, and the output will rise again at the same timing.

As described above, the 1 / m frequency divider 3 forcibly outputs the frequency-divided output of the 1 / n frequency divider 1 at a predetermined timing (after outputting the number of waveforms corresponding to the least common multiple of the frequency division ratio). Since they are synchronized, the 1 / n frequency divider 1 and the 1 / m frequency divider 3 can always be synchronized with each other.

[Second Embodiment] Next, FIG. 3 shows the second embodiment, and is a block diagram showing the configuration thereof in the case where the forced synchronization signal output by the divider 5 is supplied from the outside. Is.

The second embodiment is an embodiment corresponding to claim 1. That is, the forced synchronization signal output from the divider according to the first aspect is output from the external divider 5 (not shown). In other words, the divider 5 corresponds to the least common multiple of the division ratios of the 1 / na divider 30a, the 1 / nb divider 30b, and the 1 / nk divider 30k. It is configured to output a forced synchronization signal with a frequency ratio.

As shown in the figure, when each of the plurality of frequency dividers 30a, 30b, ..., 30k has an arbitrary frequency division ratio n _a , n _b , ..., n _k , all of these frequency dividers 30, 31, 32 the mutually synchronized to a respective shift register 31a, 31b, ..., 31 _k input terminal in the preceding stage OR circuit
15 is provided, and a forced synchronization line 16 from the outside is input to this OR circuit 15. Then, at each predetermined timing, that is, when a forced synchronization signal having the least common multiple of the frequency division ratios n _a , n _b , ..., N _k of each frequency divider is input to the forced synchronization line 16, each frequency division is performed. vessel
30a, 30b, ..., it is possible to synchronize the 30 _k each other.

[Third Embodiment] FIG. 6 is a block diagram showing a third embodiment of the phase locked loop circuit according to the present invention. The third embodiment is an embodiment corresponding to claim 1. That is, the forced synchronization signal output by the divider according to claim 1 is the external divider 5 configured by a counter and a ROM. Although only one 1 / n frequency divider is described, as in the other embodiments, the external divider 5 includes a frequency division ratio of the 1 / n frequency divider 1 and a 1 / m frequency divider 3. The forcible synchronization signal of the frequency division ratio corresponding to the least common multiple of the frequency division ratio is output.
The data for each address is written in advance in a predetermined cycle, the clock is input, the counter is advanced, and the address of the ROM connected to it is sequentially updated to output the signal of the predetermined cycle. Is. With the above configuration, the same operational effect as that of the first embodiment can be obtained.

In each of the above embodiments, the frequency division ratio n =
A few items have been explained, but more specifically, the division ratio n
= 2, as shown in FIG. 5 (a), it can be configured by only feeding back the inverted output of only the output terminal Q ₁ of the shift register 7 to the input terminal In, and when the frequency division ratio n = 3. As shown in FIG. 5 (b), the output terminals Q ₁ and Q _{2 of the} shift register 11 are
It can be configured by feedback of the inverted signal of the NAND output of.

5 (c) and 5 (d) show the configurations of the 1/4 frequency divider and the 1/5 frequency divider, respectively. Thus, in general, a 1 / n frequency divider can be created by using the output terminals Q _{1 to} Q _n-1 when using a shift register, and using this frequency divider It can be configured to synchronize.

The procedure for obtaining the forced synchronization in each of the above embodiments is shown below as a procedure.

1) The smallest integers of n series and m series that are disjoint
Find n ₀ and m ₀ .

2) Construct a shift register having a division ratio of n ₀ and m ₀ .

3) Create a signal with a division ratio of the least common multiple (LCM) of n ₀ and m ₀ . This means creating a forced sync signal by a divider or an external signal.

4) A forced sync line is connected to the input of the OR circuit of the frequency divider composed of one shift register to input the forced sync signal.

In the first and second embodiments, the frequency divider used in the positive logic system has been described. However, in the case of a non-logical system, the NAND circuit forming the condition determining circuit is used instead.
It may be configured with a NOR circuit.

According to the present invention, since a plurality of frequency dividers having different frequency division ratios can be synchronized without using a reset signal, it is possible to operate by following a clock up to the operating frequency of the shift register. The frequency dividing frequency can be applied to the high frequency band, and the frequency dividers can be easily synchronized with each other.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a phase locked loop circuit of the present invention, FIG. 2 is a timing chart of the circuit,
FIG. 3 is a block diagram showing a second embodiment of the present invention, FIGS. 4 (a) and 4 (b) are circuit diagrams showing the configuration of a frequency divider using a shift register, and FIG. 5 (a). ), (B), (c),
(D) and (e) are diagrams showing frequency dividers having other frequency division ratios,
FIG. 6 is a block diagram showing a third embodiment of the present invention, and FIG. 7 is a diagram showing a conventional frequency dividing circuit. 1 …… 1 / n divider, 3 …… 1 / m divider, 5 …… divider,
7, 11 ... Shift register, 9,13 ... Condition determination circuit (NAND circuit), 15 ... OR circuit, 16 ... Forced synchronization line.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03K 21/38 23/54 Z H03L 7/00 B

Claims (2)

[Claims] 1. A shift register having a plurality of output terminals for selecting the output terminal according to a frequency division ratio, and inverting this when all output states of the output terminals selected by the shift register are complete. A plurality of frequency dividers having different frequency division ratios, each of which is configured to feed back to the input terminal of the shift register, and provided in the preceding stage of the input terminal of each shift register constituting the frequency divider. And a OR circuit for outputting the logical sum of the output of the condition determination circuit and the forced synchronization signal, and in a phase synchronization circuit for phase-locking each frequency divider, the least common multiple of the frequency division ratios of each frequency divider. A phase synchronization circuit comprising a divider for outputting the forced synchronization signal having a frequency division ratio corresponding to. 2. A shift register having a plurality of output terminals and selecting the output terminal according to a frequency division ratio, and inverting this when all output states of the output terminals selected by the shift register are complete. A plurality of frequency dividers having different frequency division ratios, each of which is configured to feed back to the input terminal of the shift register, and provided in the preceding stage of the input terminal of each shift register constituting the frequency divider. And a OR circuit for outputting the logical sum of the output of the condition determination circuit and the forced synchronization signal, and in a phase synchronization circuit for phase-locking each frequency divider, the least common multiple of the frequency division ratios of each frequency divider. The phase-locked loop circuit is characterized in that when the frequency division ratio corresponding to is equal to the frequency division ratio of the one frequency divider, the one frequency divider outputs the forced synchronization signal.