JPH07120934B2 - Bidirectional switch - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bidirectional switch used in a subscriber circuit device or the like of a time division switch.

(Prior Art) Conventionally, as a technology in such a field, there is a bidirectional switch including a PNPN switch (thyristor) used in a subscriber circuit device. The configuration will be described below with reference to the drawings.

FIG. 2 is a diagram showing a configuration example of a subscriber circuit device including a conventional bidirectional switch.

In FIG. 2, reference numeral 1 denotes a subscriber's telephone, which is the telephone 1
Is connected to a power supply circuit 5 via transmission lines 2 and 3 and a bidirectional switch (also referred to as a separation switch) 4. The bidirectional switch 4 turns on / off between the transmission lines 2 and 3 and the feeding circuit 5, and is a terminal connected to the feeding circuit 5 side of the terminals 11 and 12 connected to the transmission lines 2 and 3 side. It has 13,14 and. A pair of PNPN switches 15 and 16 are connected in anti-parallel between terminals 11 and 13, and a pair of PNP switches is also connected between terminals 12 and 14.
N switches 17 and 18 are connected in antiparallel.

The power supply circuit 5 supplies power for communication to the closed circuit shown in FIG. In the bidirectional switch 4, normally, the PNPN switch
15,18 is turned on, and a call is made from the telephone 1 to another telephone (not shown) via the power feeding circuit 5,
When a failure occurs in the transmission lines 2 and 3, etc., the PNPN switches 15 to 18 are turned off, the telephone 1 and the power feeding circuit 5 are disconnected, the failure location is investigated, and repair is performed.

In such a subscriber circuit device, during a normal call, a call is made to the direction indicated by A in the figure, that is, to the power feeding circuit 5, the PNPN switch 15, the transmission line 2, the telephone 1, the transmission line 3, the PNPN switch 18, and the power feeding circuit 5. A loop current consisting of power for use and audio signals flows.

By the way, the transmission lines 2 and 3 are often installed in a common groove such as a manhole, and in this case, they may be subjected to AC induction due to the influence of the power lines or the like laid adjacent to each other. The transmission line
When this AC induced current is superposed on 2, 3 more than the loop current described above, the call current is reversed and the PNPN switch 15, 1
8 cut off, but at the same time PNPN switch 16,17
Is conducted, a current flows in the direction B in FIG. 2 and the call is held.

(Problems to be Solved by the Invention) However, in the bidirectional switch 4 having the above-described configuration, the current / voltage characteristic curve is the curve A1 as shown in FIG. 3, and therefore the PNPN switches 15 and 18 to the PNPN switch 16 are used. When the operation shifts to 17, the AC induction input signal B1 is distorted and becomes the output signal C1. Therefore, when a voice signal is superimposed on the output signal C1, signal distortion occurs and the S / N ratio (signal to cross ratio) is significantly deteriorated, which causes a problem that the call quality is significantly deteriorated.

The present invention has a problem that the above-mentioned conventional technique has a problem that nonlinear distortion occurs when a large-amplitude AC induction current exceeding the power supply current to the subscriber's telephone is superimposed, and the S / N characteristic deteriorates. This is to provide a bidirectional switch that solves the above problem.

(Means for Solving the Problems) In order to solve the above problems, the present invention is a bidirectional switch that conducts between a first terminal and a second terminal, which is connected to a force current source. A first node, a second node connected to the sink current source, a source connected to the first series connection point, a drain connected to the first terminal, and a drain connected to the first node A first N-channel MOS transistor (hereinafter referred to as NMOS) having a gate and a back gate connected to the first series connection point, a source connected to the first series connection point, and the second A second NMOS having a drain connected to the terminal, a gate connected to the first node, and a back gate connected to the first series connection point, and a second series connection point Source, the first terminal Connected drains, the second node connected to a gate,
And a first P-channel MOS transistor (hereinafter referred to as PMO) having a back gate connected to the second series connection point.
S), a source connected to the second series connection point, a drain connected to the second terminal, a gate connected to the second node, and a second series connection point. A second PMOS having a back gate formed by:
I have it.

Further, a predetermined voltage is connected between the gate and the drain of the first NMOS based on the current flowing from the force current source to the first terminal, which is connected between the first node and the first terminal. A first bias circuit that generates a bias voltage, and the second NMOS connected to the first node and the second terminal based on a current flowing from the force current source to the second terminal. A second bias circuit for generating a predetermined bias voltage between a gate and a drain of the first bias circuit, and a second bias circuit connected between the first terminal and the second node, and the sink current source is connected from the first terminal. A third bias circuit for generating a predetermined bias voltage between the drain and the gate of the first PMOS based on a current flowing to
Connected between the second terminal and the second node,
A fourth bias circuit for generating a predetermined bias voltage between the drain and the gate of the second PMOS based on the current flowing from the second terminal to the sink current source is provided.

For example, each of the first and second bias circuits is
A series circuit of a diode resistance in the forward direction with respect to the force current source, and the third and fourth circuits.
Each of the bias circuits is composed of a series circuit of a diode and a resistor in the forward direction with respect to the sink current source.

(Operation) In the present invention, since the bidirectional switch is configured as described above, the first, second, third and fourth bias circuits are independent of the magnitudes of the potentials of the first and second terminals. First and second NMOS
A bias voltage is applied to either of the first and second PMOSs or both of them to turn them on so that the first and second terminals are turned on. These first and second
Since the current and voltage characteristics of the NMOS and the first and second PMOSs are linear, the signal input to the first or second terminal is not distorted and the second or first terminal is not affected. Is output from. Therefore, the above problems can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a bidirectional switch showing an embodiment of the present invention.

This bidirectional switch comprises a first terminal 21 connected to the transmission line 2 or 3 of FIG. 2 and a second terminal 22 connected to the feeding circuit 5 of FIG.

Between the first and second terminals 21 and 22, the first and second NMOSs 23 and 24 connected in series and the first and second PMOSs 25 and 26 connected in series are connected in parallel. There is. Each MOS23〜
First, second, third, and fourth bias circuits 27, 28, 29, and 30 are connected between the gate and drain of 26, respectively. Further, the first and second bias circuits 27 and 28 are provided with a force current source 31 which supplies a constant current thereto, and the third and fourth bias circuits 29 and 30 are provided with a constant current from the bias circuits 29 and 30. A sink current source 32 that draws in each is connected. The connection state will be further described below.

The NMOSs 23 and 24 and the PMOSs 25 and 26 are transistors having a linear current-voltage characteristic, and their breakdown voltages between the drain and the source and between the drain and the gate are, for example, about 500 to 600V.

The first NMOS 23 has its drain connected to the first terminal 21, its source connected to its own back gate and a first series connection point, and its gate connected to the force current source 31 via the first node. ing. The second NMOS 24 has its source connected to the first back gate and its first series connection point via the first series connection point.
The source of the NMOS23, its drain to the second terminal 22,
The gates thereof are respectively connected to the force current source 31 via the first node. The first PMOS 25 has its drain connected to the first terminal 21, its source connected to the second series connection point of its own back gate, and its gate connected to the sink current source 32 via the second node. ing. Second
The PMOS 26 has its source connected to the back gate of itself and the source of the first PMOS 25 via the second series connection point, its drain to the second terminal, and its gate to the sink via the second node. Each is connected to a current source 32.

The first and second bias circuits 27 and 28 include a force current source 31
It is a circuit that converts a constant current supplied from
For example, it is composed of a series circuit of a diode and a resistance of about 5 to 10 KΩ.

That is, the first bias circuit 27 includes the diode D1 connected in the forward direction to the gate of the first NMOS 23 and the diode D1
And a resistor R1 connected to the drain of the first NMOS 23, and applies a bias voltage between the gate and drain of the first NMOS 23. This bias voltage is
It is the gate-source bias of NMOS24. The second bias circuit 28 includes a forward diode D2 connected to the gate of the second NMOS 24 and a resistor R2 connected between the diode D2 and the drain of the second NMOS 24. A bias voltage is applied between the gate and drain of. This bias voltage becomes a gate-source bias of the first NMOS 23 during operation.

The third and fourth bias circuits 29 and 30 are circuits that convert a constant current drawn into the force current source 32 into a voltage, and are composed of a series circuit of a resistor of about 5 to 10 KΩ and a diode, for example. Has been done.

That is, the third bias circuit 29 is composed of a resistor R3 connected to the drain of the first PMOS 25 and a diode D3 connected in the forward direction between the resistor R3 and the gate of the first PMOS 25. A bias voltage is applied between the drain and gate of PMOS 25 of. This bias voltage is
It serves as the gate-source bias of the PMOS 26. The fourth bias circuit 30 includes a resistor R4 connected to the drain of the second PMOS 28 and a diode D4 connected between the resistor R4 and the gate of the second PMOS 28. A bias voltage is applied between the gates. This bias voltage serves as a gate-source bias of the first PMOS 25 during operation.

The diodes D1 to D4 are connected between the first and second terminals 21 and 22, and between the terminals 21 and 22 and the upstream sources 31 and 32 when the NMOSs 23 and 24 and the PMOSs 25 and 26 are not driven. This is for ensuring the breakdown voltage between them.

Next, the operation of this embodiment will be described.

Assuming that the potential of the first terminal 21 is V1 and the potential of the second terminal 22 is
V2, drive current of force current source 31 is VN, sink current source 32
The drive potential of is VP. Normally, VN is about + 5V, VP
Is set to about −5 V, VN> VP, and the force current source 31 and the sink current source 32 are driven simultaneously. Therefore, the magnitude relation of each potential is divided as follows.

(I) VN> VP ≧ V1, V2 (ii) V1, V2 ≧ VN> VP (iii) VN> V1, V2> VP The operation will be described for these three cases.

In the case of condition (i) When V1> V2, a current flows from the force current source 31 toward the second terminal 22, and the voltage generated in the resistor R2 is the second NMOS 24.
The bias voltage between the gate and source of the
It becomes the bias voltage between the gate and drain of NMOS23.
Therefore, the first and second NOMS 23, 24 are conducted.

At this time, the potential VP of the sink current source 32 is higher than the first and second terminal potentials V1 and V2, but since the diodes D3 and D4 are in the opposite directions, the current flows through the resistors R3 and R4. Not flowing. Therefore, the bias voltage is not applied to the first and second PMOSs 25 and 26, and the first and second PMOSs 25 and 26 become non-conductive.

Also, if V2> V1, then from the force current source 31 to the first terminal
A current flows toward 21 and the voltage generated in the resistor R1 is the first
It serves as a bias voltage between the gate and drain of the NMOS 23 and a bias voltage between the gate and source of the second NMOS 24. Therefore, the first and second NMOSs 23 and 24 are conductive. At that time, the first and second PMOSs 25 and 26 become non-conductive for the same reason as above.

Therefore, under the condition (i), the first and second terminals 21 and 21 are connected via the first and second NMOSs 23 and 24 regardless of the magnitudes of the first and second terminal potentials V1 and V2. Between 22 is turned on.

In the case of condition (ii) If V1> V2, the first terminal potential V1 is the sink current source 32.
Since the potential is higher than the potential VP of the first terminal 21, current flows from the first terminal 21 to the sink current source 32 via the resistor R3 and the diode D3.
Therefore, a voltage is generated across the resistor R3, which is the first
It becomes a bias voltage between the drain and gate of the PMOS 25 and a bias voltage between the source and gate of the second PMOS 26, and the first and second PMOSs 25 and 26 become conductive.

At that time, the potential VN of the force current source 31 is lower than the first and second terminal potentials V1 and V2, and the diode D1 and D2 are in opposite directions, so that no current flows through the resistors R1 and R2. Since the bias voltage associated with is not generated, the first and second NMOS23,2
4 is non-conductive.

If V2> V1, the second terminal potential V2 is the sink current source 32.
Since it becomes higher than the potential VP of the resistor R4,
A current flows to the sink current source 32 via the diode D4. Therefore, a voltage is generated across the resistor R4, which serves as a bias voltage between the drain and gate of the second PMOS 26 and a bias voltage between the source and gate of the first PMOS 25, and the first and second PMOS 25 , 26 conduct. At this time, the potential of the force current source 31 is the first and second terminal potentials V
It is lower than 1, V2, so for the same reason as above,
The second NMOSs 23 and 24 are non-conductive.

Therefore, in the case of the condition (ii), the first and second PMOSs 25 and 26 are used to connect the first and second PMOSs 25 and 26 regardless of the potentials V1 and V2.
The terminals 21 and 22 of are turned on.

In the case of the condition (iii), if V1> V2, a current flows from the force current source 31 toward the second terminal 22 and a current flows from the first terminal 21 toward the sink current source 32. Therefore, due to the bias voltage generated across the resistor R2, the first and second NMOSs 23, 24
Is conducted, and the first and second PMOSs 25 and 26 are conducted by the bias voltage generated across the resistor R3.

If V2> V1, from the force current source 31 to the first terminal 21,
Currents respectively flow from the second terminal 22 to the sink current source 32, and the bias voltage generated by the resistor R1 causes the first and second currents to flow.
The NMOSs 23 and 24 are rendered conductive, and the first and second POMS 25 and 26 are rendered conductive by the bias voltage generated by the resistor R4.

Therefore, under the condition (iii), the NMOSs 23 and 24 and the PMOSs 25 and 2 are irrespective of the magnitudes of the first and second terminal potentials V1 and V2.
6 turns on between the first and second terminals 21 and 22.

It should be noted that the drive of the force current source 31 and the sink current source 32 may be stopped to turn off the first and second terminals 21 and 22.

FIG. 4 shows the current-voltage characteristics of the NMOSs 23 and 24 and the PMOSs 25 and 26 shown in FIG. 1. As shown in FIG.
The voltage characteristic curve A2 becomes a straight line. Therefore, AC induced current
B2 is output as the output current C2 without being distorted.

Thus, this embodiment has the following advantages.

By making a complementary connection between the NMOSs 23 and 24 and the PMOSs 25 and 26, the switch operation can be performed without being affected by the potentials V1 and V2 of the first and second terminals 21 and 22. The current-voltage characteristics of this switch are linear, and the first NMOS
23 and the second NMOS 24 and PMOS 26 of the PMOS 25 are connected in cascade to increase the bidirectional withstand voltage, so that even if a large amplitude AC induction current is input, it can be output without distortion. Therefore, if this bidirectional switch is used as a separation switch of a subscriber circuit unit in a time-division switch, it is possible to eliminate S / N characteristic deterioration, and thus, an all solid-state subscriber having a large amplitude AC induction withstand capability. It becomes possible to realize a circuit device.

It should be noted that the bidirectional switch according to the present embodiment is not limited to being used as the separation switch of the subscriber circuit device, but can be used in other applications. Also, the bias circuits 27-30
Can be composed of circuits other than the resistors R1 to R4 and the diodes D1 to D4.

(Effect of the Invention) As described in detail above, according to the present invention, the first and second NMOSs are connected in series, and the first and second NMOSs are connected.
PMOSs are connected in series, these circuits are connected in parallel between the first and second terminals, and the first, second, third and fourth bias circuits turn on and off the respective NMOSs and PMOSs. Therefore, it is possible to perform a switch operation having a linear current-voltage characteristic without being affected by the potentials of the first and second terminals, thereby eliminating the distortion of the output signal with respect to the input signal. It is possible to avoid deterioration of S / N characteristics.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a bidirectional switch showing an embodiment of the present invention, FIG. 2 is a circuit diagram for explaining a conventional bidirectional switch, and FIG. 3 is a current / voltage of the circuit of FIG. A characteristic diagram, FIG. 4 is a current / voltage characteristic diagram of the circuit of FIG. 21,22 …… First and second terminals, 23,24 …… First and second NM
OS, 25,26 …… First and second PMOS, 27,28,29,30 …… First,
2nd, 3rd, 4th bias circuit, 31 ... Force current source,
32 …… Sink current source, D1 to D4 …… Diodes, R1 to R4…
…resistance.

Claims (2)

[Claims] 1. A bidirectional switch for electrically connecting a first terminal and a second terminal, wherein a first node connected to a force current source and a second node connected to a sink current source. A source connected to the first series connection point, a drain connected to the first terminal, a gate connected to the first node, and a back gate connected to the first series connection point A first N-channel MOS transistor having a source connected to the first series connection point, a drain connected to the second terminal, a gate connected to the first node, and the first A second N-channel MOS transistor having a back gate connected to the serial connection point of the source, a source connected to the second series connection point, a train connected to the first terminal, and a second node Connected A first P-channel MOS transistor having a gate and a back gate connected to the second series connection point, a source connected to the second series connection point, and a second terminal A second P-channel MOS transistor having a train, a gate connected to the second node, and a back gate connected to the second series connection point; the first node and the first terminal; Connected between
A first bias circuit for generating a predetermined bias voltage between a gate and a drain of the first N-channel MOS transistor based on a current flowing from the force current source to the first terminal; and the first node. And the second terminal,
A second bias circuit for generating a predetermined bias voltage between a gate and a drain of the second N-channel MOS transistor based on a current flowing from the force current source to the second terminal; and the first terminal. Is connected between the first node and the first node,
A third bias circuit for generating a predetermined bias voltage between the drain and the gate of the first P-channel MOS transistor based on the current flowing from the first terminal to the sink current source; and the second terminal. Connected to the second node,
A fourth bias circuit for generating a predetermined bias voltage between the drain and the gate of the second P-channel MOS transistor based on the current flowing from the second terminal to the sink current source. The featured bidirectional switch. 2. Each of the first and second bias circuits comprises a series circuit of a diode and a resistor in a forward direction with respect to the force current source, and each of the third and fourth bias circuits. The bidirectional switch according to claim 1, wherein the bidirectional switch is configured by a series circuit with a diode resistance in a forward direction with respect to the sink current source.