JPH07120943B2 - Digital phase synchronization circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a synchronization establishment circuit in a digital phase synchronization circuit.

(Prior Art) FIG. 2 is a conventional synchronization establishment circuit diagram, in which the phase comparison circuit 1
Here, the phases of the input signal A to be subjected to the synchronization control and the output signal B subjected to the synchronization control from the counter 3 which will be described later are compared, and the signal B leads the signal A as shown in FIG. If so, a pulse of the comparison output C shown in "state 2" is generated at the rising edge of the signal A, and if delayed, similarly, a pulse of the comparison output D shown in "state 3" is generated at the rising edge of the signal A. , "Status 1" if synchronized
As shown in, the comparison outputs C and D do not generate pulses. The control circuit 2 uses the comparison outputs C and D,
When the signals A and B are synchronized with each other in response to the clock CLK shown in FIG. 3 (the cycle is 1/4 times the signal A for convenience of explanation), the state is shown as "state 1". As described above, the signal E is output in synchronization with the signal A and has a period 1/2 times that of the signal A. When the output C has a pulse, as shown in "state 2", the signal E subsequent to the pulse is output in a phase delayed by one cycle of the clock CLK, and the output D has a pulse. At this time, as shown in "state 3", similarly, the subsequent signal E following the pulse is
It is designed to be output in a phase advanced by one cycle of the clock CLK.

The counter circuit 3 is shown in FIG. 4 and FIG. 5 by adding a dash to each of the input / output signals E, F, G, B and showing the configuration and operation thereof. In the figure, a start timing signal G'is received in response to a count start value input F ', and an output signal B'which is obtained by dividing the clock input E'in half is obtained. At the time of generation of the start timing signal G ', if the count start value F'is at L level as in LD1 in FIG. 4, the output signal B'starts to be output from L level, and similarly as in LD2, F'. Is at the H level, the output signal B'starts output from the H level. In FIG. 2, the signals F and G are commonly at the H level, and in this case, the output B divides the frequency of the clock E regardless of the count start value F.

For example, when the signal B is ahead of the signal A in the initial state as in “state 2” of FIG. 3, the period of the subsequent signal E becomes longer by one period of the clock CLK, so that the signal B is It acts to delay. This operation is repeated for each cycle of the signal A until synchronization is achieved, as in "state 1". Therefore, the phase difference between the signals A and B is t _AB , the clock CL
Assuming that one cycle of K is t _CLK and one cycle of the signal A is t _A , the time T until the synchronization is established is T = t _A xt _AB / t _CLK .

(Problems to be Solved by the Invention) However, in the circuit having the above configuration, the clock
Since there is one cycle of CLK, there is a problem that if the frequency of the clock CLK is increased to reduce the jitter width, it takes a long time to establish synchronization.

(Means for Solving Problems) The present invention relates to a synchronization signal output circuit that outputs a signal for synchronizing with an input signal, and the synchronization signal output circuit for each predetermined clock that subdivides the cycle of the input signal. A phase comparison circuit for comparing the output signal and the input signal to determine the phase delay or advance and outputting the signal in synchronization with the input signal; A phase control circuit for providing a phase correction signal, detecting the H level of the input signal and detecting the H level if the phase correction signal is valid for the synchronization signal output circuit. And a detection circuit for tightening the input signal, and when the input signal is at the L level for a predetermined period of time exceeding a predetermined period of the input signal, the output signal of the synchronization signal output circuit is set to the H level, and then the A timer for holding the output state of the synchronizing signal output circuit until the input signal becomes H level is provided.

(Operation) When the input signal is at the L level for a predetermined period of time exceeding the predetermined period, the output signal of the synchronization signal output circuit is set to the H level, and then the output state of the synchronization signal output circuit is set until the input signal becomes the H level. That is, in order to keep the H level, the operation can be started from the time when the H level of the subsequent input signal is detected, and the output signal can be synchronized with the input signal.

(Embodiment) FIG. 1 shows a synchronization establishment circuit showing an embodiment of the present invention.
The phase comparison circuit 4, the control circuit 5, and the counter circuit 6 are equivalent to those having the same names in FIG.

The counter circuit 6 receives the H level signal as the count start value T and the output Q of the flip-flop (FF) 7 as the start timing signal U. The flip-flop 7 receives the inverted signal V of the input signal J via the inverter 8 at its setting terminal S, and
Becomes H level, the signal U is thereafter set to H level and the same control as in FIG. 2 is performed.

The timer circuit 9 receives the signal V at its reset terminal R, and the input signal J has a predetermined time as shown in FIG.
When it goes to L level over T _G , its output signal W goes to L level, at which time the flip-flop 7 is reset and the start timing signal U of the counter circuit 6 goes to L level.
To level. The time T _G is set to be slightly longer than the cycle of the input signal J.

FIG. 6 shows each timing of the circuit of FIG. 1, and at time t ₁ , the input signal J becomes L level,
If this is achieved at time T _G but there is no input signal J,
The output W of the timer 9 becomes L level, the flip-flop 7 is reset, and the start timing signal U becomes L level. Therefore, the output K of the counter circuit 6 becomes H level at the rising time LD3 of the signal P, and this is held for the time when the input signal J is L level. At time t ₂ , when the input signal J becomes H level,
The flip-flop 7 is set and the counter circuit 6 starts. Therefore, the signal K at this start point
Is synchronized with the input signal J.

(Effects of the Invention) As described above, according to the present invention, the synchronizing signal output circuit loaded to the H level by the input signal being at the L level for a predetermined time exceeding the predetermined cycle is input. The output signal and the input signal can be synchronized by immediately starting from the time when the H level of the signal is detected, which is particularly effective for a system that requires high-speed synchronization processing.

[Brief description of drawings]

1 is a synchronization establishment circuit showing an embodiment of the present invention, FIG. 2 is a synchronization establishment circuit showing a conventional example, FIG. 3 is an operation timing chart of the circuit of FIG. 2, and FIG. 4 is an explanatory diagram of a counter circuit. , FIG. 5 is an operation timing chart of the circuit of FIG.
FIG. 6 is an operation timing chart of the circuit of FIG. 7 ... Flip-flop (detection circuit), 9 ... Timer circuit.

Claims (1)

[Claims] 1. A synchronization signal output circuit for outputting a signal for synchronizing with an input signal, and an output signal of the synchronization signal output circuit and the input signal for each predetermined clock obtained by subdividing a cycle of the input signal. A phase comparison circuit that outputs a signal in which the phase delay or advance is compared and is output in synchronization with the input signal; and a control circuit that gives a phase correction signal corresponding to the determined signal to the synchronization signal output circuit. A phase control circuit including: a detection circuit that detects the H level of the input signal and, if there is the H level, validates the phase correction signal with respect to the synchronization signal output circuit; When the input signal is at the L level for a predetermined time period exceeding the predetermined period, the output signal of the synchronizing signal output circuit is set to the H level, and then the input signal is set to the H level.
A digital phase synchronizing circuit comprising: a timer for holding the output state of the synchronizing signal output circuit until the level is reached.