JPH07120951B2 - CMI code transmission system - Google Patents
CMI code transmission systemInfo
- Publication number
- JPH07120951B2 JPH07120951B2 JP4372988A JP4372988A JPH07120951B2 JP H07120951 B2 JPH07120951 B2 JP H07120951B2 JP 4372988 A JP4372988 A JP 4372988A JP 4372988 A JP4372988 A JP 4372988A JP H07120951 B2 JPH07120951 B2 JP H07120951B2
- Authority
- JP
- Japan
- Prior art keywords
- cmi
- nrz
- signal
- circuit
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 title claims description 23
- 238000006243 chemical reaction Methods 0.000 claims description 30
- 238000003780 insertion Methods 0.000 claims description 7
- 230000037431 insertion Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は送信情報をCMI符号に変換して伝送する方式に
関する。The present invention relates to a method for converting transmission information into CMI code and transmitting it.
（従来の技術） 従来のCMI符号伝送方式にはCRVがかけられるビツトの割
合が少ないことを利用してブロツク同期をとるものがあ
る。これはCMI符号の0.1パターンでブロツク同期をと
り、CMI符号からNRZ符号に変換し、その後にフレームパ
ターンを検出してフレーム同期をとるものである。(Prior Art) Some conventional CMI code transmission systems use block synchronization by utilizing the fact that the ratio of bits to which CRV is applied is small. This is to synchronize the block with 0.1 pattern of the CMI code, convert the CMI code to the NRZ code, and then detect the frame pattern to establish the frame synchronization.
（発明が解決しようとする課題） しかしながら、上記CMI符号伝送方式ではCRVをかける割
合が高くなつた場合にはブロツク同期がとれなくなると
いう欠点があつた。(Problems to be Solved by the Invention) However, the above CMI code transmission system has a drawback that block synchronization cannot be achieved when the rate of CRV application increases.
本発明の目的は、上記欠点を解決するもので、ブロツク
同期をとらないでフレームビツトを検出することにより
フレームビツト以外自由にCRVをかけることができるよ
うにしたCMI符号伝送方式を提供することにある。An object of the present invention is to solve the above-mentioned drawbacks, and to provide a CMI code transmission system capable of freely applying CRV other than the frame bit by detecting the frame bit without block synchronization. is there.
（課題を解決するための手段） 前記目的を達成するために本発明によるCMI符号伝送方
式は送信主信号にフレームビツトを挿入するフレーム挿
入回路と、前記フレーム挿入回路のNRZ符号出力信号と
送信クロツク信号を入力し、前記NRZ符号出力信号をCMI
符号に変換するとともにフレームビツト部分以外のビツ
ト部に送信副信号にしたがつてCRVを挿入するNRZ/CMI変
換回路と、前記NRZ/CMI変換回路の出力信号を入力と
し、ブロツク同期をとらずに２ビツトの組合せを変え
て、それぞれCMI/NRZ変換およびCRV検出を行なう第１お
よび第２のCMI/NRZ変換回路と、前記第２のCMI/NRZ変換
回路の出力信号を半クロツク遅延させるフリツプフロツ
プ回路と、前記第１のCMI/NRZ変換回路の出力信号と前
記フリツプフロツプ回路の出力信号を入力とし、CRVの
かかつている位置のデータ信号をインヒビツトし、CRV
のかかつていないデータからフレーム信号を検出して同
期をとり、前記第１のCMI/NRZ変換回路出力信号とフリ
ツプフロツプ回路出力信号のいずれの信号と同期したか
という信号を送出するフレーム同期回路と、前記フレー
ム同期回路の出力信号によつて前記CMI/NRZ変換回路出
力信号とフリツプフロツプ回路出力信号のいずれかを選
択する選択回路から構成されている。(Means for Solving the Problems) In order to achieve the above-mentioned object, a CMI code transmission system according to the present invention uses a frame insertion circuit for inserting a frame bit in a transmission main signal, an NRZ code output signal of the frame insertion circuit, and a transmission clock. Signal and input the NRZ code output signal to CMI
An NRZ / CMI conversion circuit that converts into a code and inserts a CRV according to the transmission sub-signal in bit parts other than the frame bit part, and the output signal of the NRZ / CMI conversion circuit as an input, without block synchronization. First and second CMI / NRZ conversion circuits that perform CMI / NRZ conversion and CRV detection by changing the combination of two bits, and a flip-flop circuit that delays the output signal of the second CMI / NRZ conversion circuit by half a clock. And the output signal of the first CMI / NRZ conversion circuit and the output signal of the flip-flop circuit are input, and the data signal at the position where CRV is present is inhibited and CRV
A frame synchronization circuit that detects a frame signal from unprecedented data and synchronizes with the first CMI / NRZ conversion circuit output signal and a flip-flop circuit output signal, and outputs the signal. It comprises a selection circuit for selecting one of the CMI / NRZ conversion circuit output signal and the flip-flop circuit output signal according to the output signal of the frame synchronization circuit.
（実 施 例） 以下、図面を参照して本発明をさらに詳しく説明する。(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings.
第１図は本発明方式にしたがって構成された送信側、受
信側の回路構成図である。FIG. 1 is a circuit configuration diagram of a transmitting side and a receiving side configured according to the method of the present invention.
第２図は第１図の回路の動作を説明するための図であ
る。FIG. 2 is a diagram for explaining the operation of the circuit of FIG.
送信主信号151がフレーム挿入回路101に入力され、送信
クロツクにしたがつてフレームパターン1010が挿入さ
れ、送信主信号154が出力される。NRZ/CMI変換回路102
は送信副信号153に従がい、送信主信号154にCRVをか
け、NRZ→CMI符号変換を行ない、伝送路にCMI信号155を
出力する。The transmission main signal 151 is input to the frame insertion circuit 101, the frame pattern 1010 is inserted according to the transmission clock, and the transmission main signal 154 is output. NRZ / CMI conversion circuit 102
According to the transmission sub-signal 153, the transmission main signal 154 is subjected to CRV, NRZ → CMI code conversion is performed, and the CMI signal 155 is output to the transmission path.
受信側では伝送路からのCMI符号155はCMI/NRZ変換回路1
03と104で受信される。CMI/NRZ変換回路１ 103とCMI/N
RZ変換回路２ 104は前後２ビツトの組合せを変えてCMI
→NRZ変換し、それぞれの出力からは第２図に示す156,1
57および158,159の波形が得られる。CMI/NRZ変換回路10
3,104は下記の変換則に従い、CRVを検出したとき、“1"
を出力し、それぞれ受信副信号159,157を得ることがで
きる。On the receiving side, the CMI code 155 from the transmission line is the CMI / NRZ conversion circuit 1
Received at 03 and 104. CMI / NRZ conversion circuit 1 103 and CMI / N
The RZ conversion circuit 2 104 changes the combination of front and rear 2 bits to CMI.
→ NRZ-converted and output 156,1 shown in Fig. 2 from each output.
Waveforms of 57 and 158,159 are obtained. CMI / NRZ conversion circuit 10
3,104 is “1” when CRV is detected according to the following conversion rules
Can be output to obtain reception sub-signals 159 and 157, respectively.
そしてCMI/NRZ変換回路104の出力156と157はフリツプフ
ロツプ回路105で半クロツク遅延させられ、信号160,161
が出力される。 The outputs 156 and 157 of the CMI / NRZ conversion circuit 104 are delayed by a half clock in the flip-flop circuit 105, and signals 160, 161 are output.
Is output.
フレーム同期回路108は上記CMI/NRZ交換回路103の出力1
58,159、フリツプフロツプ回路105の出力160,161および
受信クロツクを受け、CRVがかかつていない1010信号、
すなわちフレームビツトを検出することによりCMI/NRZ
変換回路103の出力158,159とフリツプフロツプ回路1055
の出力160,161のいずれかが求める信号であるかを判定
できる。この例ではCMI/NRZ変換回路１ 103の出力であ
る158,159が求める信号であると判定でき、選択回路109
は上記158,159を選択し、受信主信号163と受信副信号16
4を出力する。The frame synchronization circuit 108 outputs 1 of the CMI / NRZ exchange circuit 103.
58,159, the output of 160,161 of the flip-flop circuit 105 and the reception clock, and the 1010 signal whose CRV is not before,
That is, by detecting the frame bit, CMI / NRZ
Outputs 158 and 159 of conversion circuit 103 and flip-flop circuit 1055
It is possible to determine which of the outputs 160 and 161 of 1 is the desired signal. In this example, it can be determined that the signals 158 and 159 which are the outputs of the CMI / NRZ conversion circuit 1103 are the desired signals, and the selection circuit 109
Selects 158, 159 above, and receives main signal 163 and sub-signal 16
Outputs 4.
（発明の効果） 以上、説明したように、本発明によるCMI符号伝送方式
はCMI→NRZ変換において、ブロツク同期をとらないでフ
レームビツトを検出するように構成してあるのでCRVの
挿入の割合に制限があるという従来のCMI符号伝送方式
の欠点を解決でき、フレームビツト以外は自由にCRVを
かけることができるという効果がある。(Effect of the Invention) As described above, the CMI code transmission method according to the present invention is configured to detect a frame bit without block synchronization in the CMI → NRZ conversion, so that the CRV insertion rate can be reduced. This has the effect of solving the drawbacks of the conventional CMI code transmission method that has limitations and allowing CRV to be applied freely except for frame bits.
第１図は本発明によるCMI符号伝送方式の実施例を示す
ブロツク図である。 第２図は第１図の動作を説明するためのタイミングチヤ
ートである。 101……フレーム挿入回路 102……NRZ/CMI変換回路 103……CMI/NRZ変換回路１ 104……CMI/NRZ変換回路２ 105……フリツプフロツプ回路 108……フレーム同期回路 109……選択回路 151,154……送信主信号 152……送信クロツク 153……送信副信号、155……CMI信号 156……NRZ信号、157……CRV信号 158……NRZ信号、159……CRV信号 160……NRZ信号、161……CRV信号 163……受信主信号、164……受信副信号FIG. 1 is a block diagram showing an embodiment of a CMI code transmission system according to the present invention. FIG. 2 is a timing chart for explaining the operation of FIG. 101 …… Frame insertion circuit 102 …… NRZ / CMI conversion circuit 103 …… CMI / NRZ conversion circuit 1 104 …… CMI / NRZ conversion circuit 2 105 …… Flip-flop circuit 108 …… Frame synchronization circuit 109 …… Selection circuit 151,154… … Sending main signal 152 …… Sending clock 153 …… Sending sub signal, 155 …… CMI signal 156 …… NRZ signal, 157 …… CRV signal 158 …… NRZ signal, 159 …… CRV signal 160 …… NRZ signal, 161 …… CRV signal 163 …… Received main signal, 164 …… Received sub signal
Claims (1)
レーム挿入回路と、前記フレーム挿入回路のNRZ符号出
力信号と送信クロツク信号を入力し、前記NRZ符号出力
信号をCMI符号に変換するとともにフレームビツト部分
以外のビツト部に送信副信号にしたがつてCRVを挿入す
るNRZ/CMI変換回路と、前記NRZ/CMI変換回路の出力信号
を入力とし、ブロツク同期をとらずに２ビツトの組合せ
を変えて、それぞれCMI/NRZ変換およびCRV検出を行なう
第１および第２のCMI/NRZ変換回路と、前記第２のCMI/N
RZ変換回路の出力信号を半クロツク遅延させるフリツプ
フロツプ回路と、前記第１のCMI/NRZ変換回路の出力信
号と前記フリツプフロツプ回路の出力信号を入力とし、
CRVのかかつている位置のデータ信号をインヒビツト
し、CRVのかかつていないデータからフレーム信号を検
出して同期をとり、前記第１のCMI/NRZ変換回路出力信
号とフリツプフロツプ回路出力信号のいずれの信号と同
期したかという信号を送出するフレーム同期回路と、前
記フレーム同期回路の出力信号によつて前記CMI/NRZ変
換回路出力信号とフリツプフロツプ回路出力信号のいず
れかを選択する選択回路から構成されたことを特徴とす
るCMI符号伝送方式。1. A frame insertion circuit for inserting a frame bit into a transmission main signal, and an NRZ code output signal and a transmission clock signal of the frame insertion circuit are input to convert the NRZ code output signal into a CMI code and a frame bit. NRZ / CMI conversion circuit that inserts CRV according to the transmission sub-signal in bits other than the part and the output signal of the NRZ / CMI conversion circuit as input, and change the combination of 2 bits without block synchronization. , First and second CMI / NRZ conversion circuits for respectively performing CMI / NRZ conversion and CRV detection, and said second CMI / N
A flip-flop circuit for delaying the output signal of the RZ conversion circuit by half a clock, an output signal of the first CMI / NRZ conversion circuit and an output signal of the flip-flop circuit are input.
Inhibit the data signal in the position where CRV is present, detect the frame signal from the data that is not present in CRV and establish synchronization, and synchronize with either of the signals of the first CMI / NRZ conversion circuit output signal and flip-flop circuit output signal. A frame synchronization circuit for transmitting a signal indicating whether the CMI / NRZ conversion circuit output signal or the flip-flop circuit output signal is selected according to the output signal of the frame synchronization circuit. And CMI code transmission method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4372988A JPH07120951B2 (en) | 1988-02-26 | 1988-02-26 | CMI code transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4372988A JPH07120951B2 (en) | 1988-02-26 | 1988-02-26 | CMI code transmission system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01218217A JPH01218217A (en) | 1989-08-31 |
| JPH07120951B2 true JPH07120951B2 (en) | 1995-12-20 |
Family
ID=12671875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4372988A Expired - Lifetime JPH07120951B2 (en) | 1988-02-26 | 1988-02-26 | CMI code transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120951B2 (en) |
-
1988
- 1988-02-26 JP JP4372988A patent/JPH07120951B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01218217A (en) | 1989-08-31 |
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