JPH07120964B2 - Extension circuit - Google Patents

Description

The present invention relates to a decompression circuit for decompressing an 8-bit μ255 law PCM code into a linear code.

[Conventional technology]

FIG. 4 shows, for example, H. Kaneko, “A Unified
Formulation of Segment Companding Laws and Synthesis of Causes
And Digital Companders “BST J., 1555 pages, September 1970 (H.KANEKO,“ A
Unified Formulation of Segment Companding Laws and
Synthesis of Codes and Digital Compandors "BST
J., P1555, SEPT.'70), which is a conventional decompression circuit, in which 1 is a code in which the polarity of the PCM code is inverted, and 2 is an inverter for inverting the input of this code 1,
Reference numeral 3 is a shift register for performing parallel output using the output of the inverter 2 as serial input, and 4 is a clock for inputting to the terminal T ₀ of the shift register 3 and sequentially fetching data from the serial signal input terminal S _IN and shifting. ,Ten
Reference numerals 0, 101, 102, 103, 104, 105 and 106 respectively indicate the signals Q ₀₀ , Q ₀₁ , Q ₀₂ , Q ₀₃ , Q ₀₄ , Q ₀₅ and Q ₀₆ output from the shift register 3, and reference numerals 5 and 6 denote a shift register and a down counter, respectively. Parallel data input is D ₂₀ ,, D ₂₁ ,, D ₂₂ ,, D ₂₃ , D
₂₄ and D ₂₅ , the parallel data input D ₂₅ and the serial signal input terminal S _IN are grounded, and the parallel data input D ₂₀
Is "1".

In addition, the parallel data inputs D ₁₀ , D ₁₁ ,
The parallel output 104 from the shift register 3 is output to D _12.
106 is entered.

Reference numeral 7 is a mode signal for setting a serial input mode or a mode for loading (D) data in parallel. In the serial input mode, clock inputs T ₂ and T ₁
The data is shifted one by one, and the down counter 6 counts down.

Reference numeral 8 is an OR circuit which receives the data outputs Q ₁₀ , Q ₁₁ and Q ₁₂ of the down counter 6, and 9 is an OR circuit which receives the output of the OR circuit 8 and the output Q ₂₅ of the shift register 5.

Reference numeral 10 is a clock (T ₃ ) for shifting or counting down the shift register 5 and down counter 6, and 11 is the clock input T ₁ of the down counter 6 or the clock input of the shift register 5 by the output of the OR circuit 8.
It is a switching device that switches to T ₂ and supplies.

Reference numeral 12 is deviation data by a serial signal, 13 is a D-flip-flop (hereinafter, referred to as DF / F) for outputting the deviation data 12 at a timing with a clock 10, and ₄₀ thereof is output data. .

Reference numeral 14 is a full adder that sequentially adds the output ₄₀ and the output of the OR circuit 9 at the timing of the clock 10, and 15 is the output of the full adder 14.

Next, the operation will be described. First, the 8-bit inverted code 1 is further inverted by the inverter 2 to become a PCM code of the correct polarity, which is input from the serial data input terminal S _IN0 of the shift register 3 at the falling _{edge of} the clock 4 and sequentially shifted. , Data output Q ₀₀ 100, Q ₀₁ 101, Q ₀₂ 102, Q
_The output is shifted in the order of ₀₃ 103, Q ₀₄ 104, Q ₀₅ 105, Q ₀₆ 106,
It is output.

The bit structure of the 8-bit PCM code is composed of a code bit P, a segment S, and a quantization step number Q as shown in FIG. 5, and the code bit P is input to the shift register 3 first.

Further, W, X, Y, Z represent the components of the number of quantization steps Q and have a value of 0 or 1, and e ₀ , e ₁ , e ₂ represent the components of the segment S, which are also 0 or 1. Is a binary number.

After these are input to the shift register 3, the correspondence between the data output of the shift register 3 and the sign is the data output (Q
₀₇ , Q ₀₆ , Q ₀₅ , Q ₀₄ , Q ₀₃ , Q ₀₂ , Q ₀₁ , Q ₀₀ ) ＝ (P, e ₂ , e ₁ , e ₀ , W,
X, Y, Z).

Next, the mode signal 7 becomes the load D (= 0), and the shift register 5 and the down counter 6 receive the data input (D ₁₂ ,
D ₁₁ ,, D ₁₀ ,, D ₂₀ ,, D ₂₁ ,, D ₂₂ ,, D ₂₃ , D ₂₄ , D ₂₅ ) ＝ (e ₂ , e ₁ , e ₀ , 1, W,
X, Y, Z, 0) is input.

The data outputs D ₁₂ , D ₁₁ , D ₁₀ of the down counter 6 are input to the OR circuit 8 as (Q ₁₂ , Q ₁₁ , Q ₁₀ ) = (e ₂ , e ₁ , e ₀ ), and (e ₂ , e ₁ , e ₀ ) ≠ (0,0,0), this OR circuit 8
Becomes 1 and the clock 10 is first switched by the switch 11 to be input to the clock input T ₁ of the down counter 6 and counts down until the output of the OR circuit 8 becomes 0, during which the OR circuit The output of 9 is 1 which is the output of the OR circuit 8 itself, and the count continues.

Next, the data output of the down counter 6 (Q ₁₂ , Q ₁₁ , Q ₁₀ )
When = (0,0,0), the output of the OR circuit 8 becomes 0, the switch 10 switches the clock 10 to the shift register 5, and the clock 10 is input to the clock input T ₂ of the shift register 5.

At this time, the output of the down counter 6 is (0,0,0), and OR
The output of the circuit 8 also remains 0. Therefore, the clock
Data output of shift register 5 at rising edge of 10
Data input D of the shift register 5 data input (D ₂₀ , D ₂₁ , D ₂₂ , D ₂₃ , D ₂₄ , D ₂₅ ) to the input of the OR circuit 9 from Q _25
The signals are output in order from ₂₅ , and then serial signal input terminals
Since S _IN = 0, 0 is continuously input.

Therefore, the OR circuit 9 outputs the signals according to the input signals. The signal train at this time forms 13 binary numbers. This is shown in Table 1 below.

In Table 1, the serial output from the OR circuit 9 is LS
It is output from the B side, and 1 on the right side of (... Z, 0) continues for the number of binary numbers of (e ₂ , e ₁ , e ₀ ).

The values in Table 1 above are called deviation linear codes, and the output from which deviations have been removed is a linear code. In order to remove this deviation, 33 in decimal (0 0000 0010 0001 in binary) should be subtracted.

Therefore, the deviation data 12 is stored in some memory (not shown).
When it is taken out from the memory, converted into the form of 2's complement through the DF / F 13 at the timing of the clock 10 and inputted to the full adder 14, the same result as the subtraction is obtained. In order to make this deviation data 12 into two's complement, it is shown in FIG.
It is recommended to input 00 0010 0000 (LSB) from LSB.

[Problems to be Solved by the Invention]

Since the conventional decompression circuit is configured as described above, it is effective only when the sign bit P is positive, and there is a problem that correct conversion cannot be performed when the sign bit P is negative.

The present invention has been made in order to solve the above problems, and the target can be expanded even when the sign bit P is a negative number (P = 1), and "+0" ... 0000 0000) and ( The purpose of the present invention is to obtain a decompression circuit in which two different PCM codes (“−0” ... 1000 0000) are both converted to “0” when converted into linear codes.

[Means for Solving the Problems]

A decompression circuit according to the present invention outputs a two's complement of a linear code and converts a linear code of an 8-bit PCM code indicating ± 0 into all 0s, and switches the output of this conversion circuit and the linear code. And a switching device for outputting the output.

[Work]

The conversion circuit according to the present invention sequentially adds the 1's complement whose linear code is an inverted signal and the 13-bit addend in the full adder to output the 2's complement of the linear code, and when the 13th digit is added. Obtain the polarity signal of the linear code by taking the logical product of the inverted signal obtained by inverting the carry signal and the sign bit, or
When all 7 bits other than the sign bit of the 8-bit PCM code are 0, they are logically combined with the sign bit to obtain the polarity signal of the linear code, and it also works effectively for the negative 8-bit PCM code. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, 201 is an addend (0 0000) for obtaining a two's complement.
0000 0001), which is input to the full adder 202 from “1” first.

This full adder 202 uses the input of addend 201 and the input 15 (same as full adder output 15 of FIG. 4) as 1's complement through inverter 15a to output 1's complement data 203 to clock 10 (clock of FIG. 4). (Same as 10), and the full adder output 204 is output.

Reference numeral 205 denotes a switch for switching the output 204 of the full adder or the input 15 and when the sign bit Q ₀₇ (data output Q ₀₇ of the shift register 3 in FIG. 4) is positive (sign bit Q ₀₇ =
0) Input 15 is output.

When the sign bit Q ₀₇ is negative, Q ₀₇ = 1 and full adder 20
The second output, that is, the full adder output 204 is output as the switch output 206. 206 is an output of the switch 205, that is, a switch output, and 207 is a shift register that sequentially shifts the switch output 206.

Data output of this shift register 207 Q ₁₂ is LSB, Q ₀ is MSB
Represents Reference numeral 208 is a full adder carry signal.

Therefore, if clock 10 is input for 13 clocks,
All conversion is completed, and at this time, the full adder carry signal 20
If 8 is 1, it indicates carry.

Reference numeral 209 is an inverted signal of the full adder carry signal 208. 209a denotes an AND circuit for taking a logical product of the inverted signal 209 and the sign bit Q _07, by the AND circuit 209a and the full adder 202, the 8-bit PCM code "+0", "- 0" of the linear code A conversion circuit for converting all 0s is configured.

210 is the output of this AND circuit 209a, that is, the output of the AND of the inverted signal 209 and the sign bit Q ₀₇ ,
A polarity signal of a linear code indicating a negative polarity if 1 and a positive polarity if 0.

Next, the operation will be described. Now, when a negative number is output from the full adder 14 of FIG. 4 and is input as the input 15 to the inverter 15a, it is inverted by this inverter 15a and the 1's complement data 203 is input to the serial full adder 202. It
This is called the one's complement, and this and (0 0000 0000
0001) addend 201 is input to full adder 202
It is fully added based on 10.

As a result, the full adder output 2 output from the full adder 202
04 is a two's complement. Switcher 20
5 outputs the full adder output 204 as the switch output 206 and sequentially inputs it to the shift register 207. When the last 13th digit is over and the result is input to the shift register 207,
The polarity at that time is output as a polarity signal 210 having a linear code. It is 0 if positive and 1 if negative.

This will be shown using an actual example. In the 8-bit PCM code, the following two codes correspond to 0 of the linear code. That is, "+0" ... 0000 0000 = 00H "-0" ... 1000 0000 = 80H When this is converted into a linear code, the former is "+0" ... 0 (polarity) 0000 0000 0000 0 The latter is "-1" ... 1 ( (Polarity) 0000 0000 0000 0, a negative sign remains in “−0”, and it becomes a negative full scale in the two's complement form, and does not become 0 of a linear code.

Therefore, looking at the carry signal 208 of the full adder 202 and the signal of the sign bit Q ₀₇ in FIG. 1, the truth table in FIG. 2 can be satisfied, and the straight line coding can be correctly performed, and “+0” and “−0” can be obtained. The result that both are all 0 is obtained. The polar code polarity signal 210 is the output of a circuit constructed based on the truth table of FIG.

Although the polarity signal 210 of the linear code is output based on the carry signal 208 of the serial full adder 202, another embodiment of the present invention will be described with reference to FIG. In FIG. 3, the parts indicated by 1,2,3,100 to 106 are the same as those in FIG. 4, and the outputs 100 to 106 of the shift register 3 are output in parallel in FIG. Is the first processing system
Same as the figure, but AND which inputs the inverted signal 209 and the sign bit Q ₀₇ to obtain the polarity signal 210 of the linear signal of FIG.
The circuit is omitted.

Also, 400 indicates the value of the code S, Q (segment S, quantization step Q) excluding the code bit Q ₀₇ of the 8-bit PCM code N
It is the output of the OR circuit 400a, the output 400 is 1 when all of its inputs are 0, and the output 401 of the NAND circuit 400b is the sign bit Q ₀₇ = 1 only when the output is "-0", so that "-0" is output. At this time, the value becomes 0, and the output of the AND circuit 400c becomes 0. Therefore, a code (polarity signal 210 of the linear signal) that satisfies the truth table of FIG. 2 can be output.

Thus, a conversion circuit equivalent to the conversion circuit for converting the two types of 0 of the 8-bit PCM code into the all 0s of the linear code by the full adder 202 and the AND circuit 209a in FIG. 1 is provided as the output of the shift register 3 and the NOR circuit 400a. AND circuit 400b AND circuit 400c
It consists of and.

Further, the same result can be obtained by performing the same thing in software without performing these in hardware.

〔The invention's effect〕

As described above, according to the present invention, the two's complement of the linear code is output, and the carry signal and the 8-bit carry signal obtained by adding the one's complement by the inversion signal of the linear code and the 13-bit addend are added.
Logical AND with the sign bit of PCM code, or 7 bits of 8-bit PCM code excluding sign bit are all 0
Is detected and combined with the sign bit, the straight line code of the 8-bit PCM code indicating ± 0 is all 0
Since the linear code and the two's complement of the linear code are switched and output, the correct conversion can be performed without significantly increasing the circuit scale and the processing target is expanded even when the code bit P is negative. If the PCM code indicating 0 which is possible and different type is converted into the linear code, there is an effect that it becomes "0" based on "+0" and "-0".

[Brief description of drawings]

FIG. 1 is a circuit diagram of a decompression circuit according to an embodiment of the present invention,
FIG. 2 is a truth table showing the relationship between the carry signal of the full adder circuit and the code bit Q _{07 in} the above embodiment, and FIG. 3 is a circuit for obtaining the polarity signal of the linear code in the expansion circuit according to another embodiment of the present invention. Fig. 4 is a circuit diagram of a conventional decompression circuit, and Fig. 5 is an 8-bit PCM applied to the decompression circuit of Fig. 4.
It is explanatory drawing which shows the bit structure of a code | symbol. 3, 207 is a shift register, 202 is a full adder, 205 is a switch, 209a is an AND circuit, 400a is a NOR circuit, 400b is a NAND circuit,
400c is an AND circuit, and 202,209a, 3,400a, 400b, 400c are conversion circuits. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A full adder for sequentially adding a 8-bit μ255 law PCM code and a 2's complement of 13-bit deviation data to obtain a linear code, and the 8-bit μ255 law PCM code is −0. In the case where it is shown, a conversion circuit for converting the above linear code so that all the bits are 0 in the complement format, and when the 8-bit μ255 law PCM code shows +0, it is output from the full adder. A decompression circuit having a switch for selecting a linear code and for selecting the linear code output from the conversion circuit when the 8-bit μ255 law PCM code indicates -0.