JPH07120972B2 - Eco-Cancer device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an echo canceller device for suppressing howling caused by acoustic coupling between a microphone and a speaker in an electronic conference system or the like.

(Prior Art) FIG. 4 shows a configuration of an echo canceller device used in an electronic conference system. In FIG. 4, reference numeral 1 denotes a reception input digital signal input terminal, which is connected to the D / A converter 2 and the echo canceller 7. The D / A converter 2 is a speaker 3
It is connected to the. A microphone 4 is connected to the A / D converter 5. The echo canceller 7 is connected to the input terminal 1, the output terminal 6, the D / A converter 2 and the A / D converter 5. In the figure, (1) is a signal called a reception input digital signal or a far end input digital signal, and (2) is its D / A conversion output. These are x _j ,
It is represented as x _(t) . Also, (3) is an echo signal of x _(t) , (4) is a near-end input signal composed of a transmission sound and a room sound, and (5) is a transmission input signal obtained by the sum of (3) and (4). Yes, they are represented as z _(t) , n _(t) , and s _(t) , respectively. (6)
Is the A / D conversion output of s _(t) , and (7) is the residual echo, which are also expressed as s _j and e _j , respectively.

Next, the above operation will be described. Far-end input x _j is D /
A-converted to x _(t) , but due to acoustic coupling between the microphone and speaker, part of it leaks to the transmitting side as echo z _(t) . On the other hand, since the near-end input n _(t) is also superimposed on the transmitting side,
After all, s _j obtained by A / D converting s _(t) = z _(t) + n _(t) is obtained. On the other hand, the echo canceller sequentially estimates the impulse response of the echo path by the learning identification method as shown in the following equations (1) and (2), and on the other hand, cancels the echo component using the estimated impulse response.

e _j = s _j −X _j ^T H _j (1) Where H _j = (h ₀ ^j h ₁ ^j … h _N-1 ^j ) ^T is the estimated impulse at time j X _j = (x _j x _j … x _jN-1 ) ^T is the received input sequence at time j Yes, N is the number of samplings corresponding to the impulse response length of the echo path.

That is, the conventional echo canceller device is
Pseudo echo is calculated by estimating the transfer function from n _(t) and the echo train z _(t) and performing a convolution operation of the estimated transfer function with the reception input train and the echo train,
A pseudo echo was subtracted from the echo to obtain a residual echo.

(Problems to be Solved by the Invention) However, in the above-described conventional echo canceller device, when the impulse response length of the echo path becomes longer, the convergence time required for canceling the echo also becomes longer, so that the characteristics change at the time of starting and the echo path. Sometimes there was a problem that the echo could not be canceled sufficiently.

The present invention solves such a conventional problem, and when the impulse response is estimated only by the first echo canceller, the convergence speed becomes large, and an estimation error and an approximation error occur. The present invention provides an excellent echo canceller device that is corrected by the second echo canceller.

Further, the present invention combines two echo cancellers having different characteristics, so that even if the impulse response length is long and the characteristic changes frequently, it is an excellent echo that follows the echo path at high speed and cancels the echo. It is an object to provide a canceller device.

(Means for Solving the Problems) In order to achieve the above object, the present invention approximates an impulse response of an echo path with a transfer function of a discrete system having poles, and calculates its coefficient from a reception input sequence and an echo sequence. A first means for estimating, a pseudo echo is calculated by a convolution operation of the transfer function estimated by the first means, the reception input sequence and the echo sequence, and a second residual echo is generated by subtracting the pseudo echo from the echo. And a third means for estimating an impulse response of an echo path including the first echo canceller from the received input sequence and the first residual echo, and an estimation estimated by the third means. A fourth echo for generating a second residual echo by calculating a pseudo echo by a convolution operation of the impulse response and the received input sequence and subtracting the pseudo echo from the first residual echo Means for connecting the first echo canceller and the second echo canceller in cascade connection, and the first echo canceller having a large convergence speed at the time of start-up and when the characteristics of the echo path change. Also approximates and estimates the transfer function of the echo path, and further the second echo canceller corrects the approximation and estimation error of the first echo canceller, and even for a system in which the echo delay is large and the echo path changes frequently. It is characterized in that the echo can be erased by following it.

(Operation) The present invention having the above-mentioned configuration has the following operations. That is, at start-up and when the echo path characteristics change,
Since the first echo canceller approximates and estimates the impulse response of the echo path in the form of a transfer function with poles,
It has the effect that the echo can be canceled several times faster than the echo canceller that estimates the normal impulse response.

Further, according to the present invention, the second echo canceller corrects the approximation and estimation errors of the first echo canceller and cancels the echo. Therefore, there is an effect that the echo can be erased by following the echo path at high speed even if the echo path has a long reverberation time and the characteristic changes frequently.

(Embodiment) FIG. 1 shows the configuration of an embodiment of the present invention.
In FIG. 1, reference numeral 1 denotes an input end of a received input digital signal, which is connected to the D / A converter 2 and the echo cancellers 7 and 8. Reference numeral 3 is a speaker, which is connected to the D / A converter 2. The first echo canceller 7 is connected to the D / A converter 2, the A / D converter 5 and the second echo canceller 8. The second echo canceller 8 is connected to the input terminal 1, the output terminal 6 and the first echo canceller 7. The first and second echo cancellers will be referred to as EC1 and EC2, respectively.

In the figure, (1) is the received input digital signal
x _j , and (2) is the D / A conversion output x _(t) .
(3) is the echo z _(t) due to the D / A conversion output x _(t) ,
(4) is the near-end input n _(t) , and (5) is the transmission input s _(t) which is the sum of the echo z _(t) (3) and the near-end input n _(t) (4).
(6) is the A / D conversion output s _j of the transmission output s _(t) . or,
(7) is the residual echo obtained by removing the echo from the A / D conversion output s _j by EC1, and is expressed as e _j ¹ . EC8 is (8)
It is a residual echo obtained by removing an echo component having a larger delay than e _j ¹ , and this will be referred to as e _j ² . (9)
Is a signal indicating that EC2 has detected a near-end input, and will be expressed as t _j .

FIG. 2 shows the configuration of EC1. In FIG. 2, reference numeral 11 denotes an input end of x _j , which is connected to the reception output end 12, the reception input shift register 13, the transmission / reception input squared norm calculator 19, the power calculator 34, and the control circuit 37. 12 is an output terminal of x _j , and is a reception input terminal 11, a reception input shift register 1
3, connected to the transmission / reception input square norm calculator 19, the power calculator 34, and the control circuit 37. Reference numeral 13 is a word shift register for storing the received input sequence, which is connected to the product-sum calculator 14 and the estimated transfer function numerator coefficient correction register 18.
The shift register 13 is represented by X _{j −M} ² .
14 is a sum-of-products calculator, which is a shift register for receiving inputs 13,
It is connected to the estimated transfer function numerator coefficient register 16 and the adders 17 and 28. Reference numeral 16 is a register for storing the estimated transfer function numerator coefficient B _j , which is connected to the product-sum calculator 14, the estimated transfer function numerator coefficient save register 15, and the adder 17. 15
Is a save register for B _j , and is connected to the estimated transfer function numerator coefficient register 16. An adder 17 is connected to the product-sum calculator 14, the estimated transfer function numerator coefficient register 16, and the estimated transfer function numerator coefficient correction register 18. 18 is
B _j correction register ΔB _j, which is connected to the reception input shift register 13, the adder 17, the transmission / reception input square norm calculator 19, and the transfer function denominator coefficient correction register 27. 20 is EC
It is an input terminal of the residual echo e _j ¹ of ¹ , and is connected to the transmission / reception input square norm calculator 19, 1-sample delay circuit 21, subtractor 29, power calculator 30, and control circuit 37. The one-sample delay circuit 21 is connected to the transmission input terminal 20, the transmission input shift register 22, the subtractor 29, the power calculator 30, and the control circuit 37.
The transmission input shift register 22 is a word register for storing the e _j ¹ input sequence, and the 1-sample delay circuit 21,
It is connected to the product-sum calculator 23 and the transfer function denominator coefficient correction register 27. The product-sum calculator 23 is connected to the transmission input shift register 22, the transfer function denominator coefficient register 25, and the adders 26 and 28. Reference numeral 24 is a save register, which is connected to the transfer function denominator coefficient register 25. The transfer function denominator coefficient register 25 is a register for storing the coefficient A _j of the denominator of the estimated transfer function, and is connected to the product-sum calculator 23 and the adder 26. The adder 26 includes a product-sum calculator 23, a transfer function denominator coefficient register 25, and a transfer function denominator coefficient correction register 2
Connected to 7. Transfer function denominator coefficient correction register 2
Reference numeral 7 denotes an A _j correction register ΔA _j, which is an estimated transfer function numerator coefficient correction register # 18, and a transmission / reception input square norm calculator 1
9, connected to the transmission input shift register 22 and the adder 26. The adder 28 is connected to the product-sum calculators 14, 23 and the IIR type echo canceller disable switch 36. The subtractor 29 includes a transmission input square norm calculator 19, a transmission input terminal 20,
1-sample delay circuit 21, power calculators 30, 33, transmission output terminal 3
5, connected to the IIR type echo canceller disable switch 36 and the control circuit 37. The power calculator 30 is a calculator that calculates the power E _Pj ¹ of e _j ¹ , and includes a transmission / reception input square norm calculator 19, a transmission input terminal 20, a 1-sample delay circuit 21, a subtractor 29, and a save register 31. It is also connected to the control circuit 37.
31 is a save register E _PM ¹ for E _Pj ¹ and is used by the power calculator 3
0, connected to control circuit 37. 33 is the residual echo of EC2 e
It is an arithmetic unit for calculating the power E _Pj ² of _j ² , and is connected to the subtracter 29, the save register 32, the transmission output terminal 35, and the control circuit 37. _{Reference numeral} 32 denotes a save register E _PM ² for E _Pj ² , which is connected to the power calculator 33 and the control circuit 37. 34 is an arithmetic unit for calculating the power X _{pj-M + 1} of x _{j-M + 1} , including a reception input end 11, a reception output end 12, a reception input shift register 13, and a transmission / reception input squared norm calculator 19, connected to control circuit 37. 35 is the output end of e _j ² , which is the subtractor 29 and the power calculator 3
3, connected to the control circuit 37. Reference numeral 36 is a switch for disabling EC1, which is connected to the adder 28 and the subtractor 29.

The control circuit 37 uses the correction register 1 for the estimated transfer function numerator coefficient.
8, transfer function denominator coefficient correction register 27 value set and estimated transfer function numerator coefficient save register 15-estimated transfer function numerator coefficient register 16 between, transfer function denominator coefficient save register 24-transfer function denominator coefficient register 25, between the power calculator 30 and the save register 31, and between the save register 32 and the power calculator 33, and is a circuit for controlling the switching of the switch of 36, the receiving input terminal 11, the receiving output. Terminal 12, reception input shift register 13, transmission / reception input squared norm calculator 19, transmission input terminal 20, 1-sample delay circuit 21, subtractor
29, power calculator 30, save registers 31, 32, power calculator
33, 34, a transmission output end 35, and a near end input detection signal input end 38 by a FIR type echo canceller. The near-end input detection signal input end 38 is an input end of t _j and is connected to the control circuit 37.

FIG. 3 shows the configuration of EC2. In FIG. 3, 41 is an input terminal of x _j , and is a shift register for reception input.
42, the reception input square norm calculator 50, the power calculator 45, and the control circuit 57. Reference numeral 42 is a word shift register for storing the received input sequence, which is connected to the product-sum calculator 43 and the estimated impulse correction register 49. In addition,
The reception input shift register 42 is represented as X _j ¹ . The product-sum calculator 43 is connected to the reception input shift register 42, the subtractor 45, the estimated impulse register 47, and the adder 48. 44 is an input terminal of s _j and is connected to the subtractor 45, the power calculator 51, and the control circuit 57. The subtractor 45 is
It is connected to the transmission input terminal 44, the power calculator 51, the power calculator 54, and the residual echo output terminal 56. 47 is a register for storing the estimated impulse response H _j ¹ , which is connected to the product-sum calculator 43, the estimated impulse save register 46, and the adder 48. Estimated impulse save register 46 is retracted register H _M ¹ of H _j ^1, is connected to the estimated impulse register 47. The adder 48 includes a product-sum calculator 43, an estimated impulse register 47, and an estimated impulse correction register 49.
It is connected to the. 49 is a register for H _j ¹ correction ΔH _j ^1, which is a shift register for reception input 42, an adder 48, a reception input 2
It is connected to the power norm calculator 50. The reception input square norm calculator 50 is a square norm calculator of X _j ¹ , and includes a reception input terminal 41, a reception input shift register 42, an estimated impulse correction register 49, a power calculator 55, and a control circuit 57. It is connected. _{Reference numeral} 51 is an arithmetic unit for calculating the power S _{Pj of} S _j , which is connected to the transmission input terminal 44, the subtractor 45, the save register 52, and the control circuit 57. 52 is a save register S _PM for S _Pj ,
It is connected to the power calculator 51 and the control circuit 57. 54 is EC1
_Is a computing unit for calculating the power E _Pj ¹ of the residual echo e _j ¹ by the subtractor 45, the save register 53, the residual echo output terminal 5
6, connected to the control circuit 57. 53 is a save register E _PM ¹ for E _Pj ¹ and is connected to the control circuit 57 and the power calculator 54. _{Reference numeral} 55 denotes an arithmetic unit for calculating the power X _Pj ¹ of X _j , which is connected to the reception input terminal 41, the reception input shift register 42, the reception input squared norm calculator 50, and the control circuit 57. Five
Reference _numeral 6 denotes an output terminal of e _j ¹ , which is connected to the subtractor 45, the power calculator 54, and the control circuit 57. 57 is a set of values of the estimated impulse correction register 49, and the estimated impulse save register 46-estimated impulse register 47, and a power calculator.
51-saving register 52, a circuit for performing control such as data transfer control between the saving register 53-power calculator 54,
Reception input terminal 41, reception input shift register 42, transmission input terminal
44, subtractor 45, reception input square norm calculator 50, power calculator 51, save registers 52, 53, power calculators 54, 55, near-end input detection signal output end 58. The near-end input detection signal output end 58 is an output end of the signal t _j indicating that the EC1 has detected the near-end input n _(t) , and is connected to the control circuit 57.

Next, the above operation example will be described. First of the above embodiment
In the figure, EC1 is the transfer function of the acoustic coupling between the microphone and the speaker. _{B (z) = b 0 +} b 1 Z -1 + ... + b N-1 Z -N + 1 A (z) = a 1 Z -1 + ... approximated by ^{_{+ a M-1 Z -M +}} 1 form. Here, since this transfer function has a pole, the convergence speed is higher when the coefficients of A (z) and B (z) are estimated than when the impulse response is estimated, and the impulse of the echo path is increased. Even if the response length is long, it is possible to realize an echo canceller capable of following the characteristic change at high speed. EC2 is for correcting the approximation error and the estimation error in EC1, and although the convergence speed is smaller than EC1, accurate estimation and echo cancellation are performed.

FIG. 2 of the above embodiment is a functional block diagram of EC1 in FIG. The calculation of EC1 that performs the above-described operation is as in equations (4), (5), and (6).

e _j = e _j ¹ −X _j ^2T B _j −E _j-1 ¹ A _j (4) here, ^{_{X jM 2 = (x j x}} j ...... x j) T E j - 1 1 = (e j-1 1 ...... e j 1) T Note that equation (4), the convergence of (5), (6) Sex and stability have already been proved and are publicly known. In FIG. 2, the product-sum calculators 14 and 23, the adder 28, and the subtracter 29 execute the above equation (4) and output the residual echo e _j to the output end 35.
The correction register 18 calculates the second term on the right side of the equation (5), and the adder 17 executes the equation (5). Further, the correction register 27 is the one that calculates the second term on the right side of the equation (6), and the equation (6) is executed by the adder 26. On the other hand, EC
The control circuit 57 of ² detects the near-end input by power comparison of the power calculator 51 of e _j ¹ , the save register 52 thereof, the power calculator 54 of e _j ² and the save register 53 thereof, as in EC1. . However, the operation of EC1 is disabled by the switch 36 when either EC1 or EC2 detects a near-end input.
Therefore, when the near-end input is detected, echo cancellation is not performed, but when there is no far-end input, no echo is originally generated, so there is no problem. Disabling of echo cancellation affects when both the far-end input and the near-end input are added and at the time of howling. Of these, the former case is infrequent and need not be considered. In the latter case, this device corresponds to a runaway, and another howling detector must be provided for resetting.

FIG. 3 of the above embodiment is a functional block diagram of the EC2 in FIG. The calculation of EC2 for performing the above operation is as shown in equations (7) and (8).

e _j ¹ = s _j −X _j ^1T・ H _1j (7) here, In FIG. 3, the product-sum calculator 43 and the subtractor 45 execute the above equation (7) and output the first residual echo e _j ¹ to the output end 56. Further, the correction register 49 is the one that calculates the second term on the right side of the equation (8), and the equation (8) is executed by the adder 48. On the other hand, the control circuit 57 uses the power _SPj calculator 51, its save register 52, and power E
_The near-end input is detected by comparing the powers of the _pj ¹ calculator 54 and its save register 53, and if detected, the estimation calculation shown in the above equation (8) is stopped and the detection flag t _j = 1 is output. It is output to 58 and input to the input terminal 38 of EC1.

As described above, according to the above-described embodiment, since the transfer function of the echo path is estimated in the form of the equation (3), it follows the echo path having a long impulse response length and frequent characteristic changes at high speed. You can erase the echo and go on.

Also, the echo canceller must be disabled during double talk, but it is considered that there is no problem with the ratio of time as described above.

The present invention can be configured by a relatively simple LSI by using the well-known digital filter technique, and is not limited to the configurations shown in FIGS. 2 and 3.

(Effects of the Invention) In the present invention, when estimating an impulse response, the first echo canceller having a high convergence speed, and the convergence speed being low,
By combining with a highly accurate second echo canceller, it is possible to follow the change in the characteristics of the echo path at high speed, and it is possible to cancel the echo.

The present invention can cancel the echo by correcting the estimation error and the approximation error by combining the two echo cancellers having different properties as described above.

[Brief description of drawings]

1 is a system block diagram in one embodiment of the present invention, FIG. 2 is a functional block diagram of the first echo canceller used in one embodiment of the present invention, and FIG. 3 is used in one embodiment of the present invention. FIG. 4 is a functional block diagram of the second echo canceller, and FIG. 4 is a schematic block diagram of a conventional example in the echo canceller device. In FIG. 1: 1 ... Receiving input end, 2 ... D / A converter, 3 ... Speaker, 4 ... Microphone, 5 ... A / D converter, 6 ... Transmission output end, 7 ... First echo canceller, 8 ... Second echo canceller. In Fig. 2: 11 ... Receive input end, 12 ... Receive output end, 13 ... Receive input shift register, 14 ... Multiply-accumulator, 15 ... Estimated transfer function numerator coefficient save register, 16 ... … Estimated transfer function numerator coefficient register, 17 …… Adder, 18 …… Estimated transfer function numerator coefficient correction register, 19 …… Sending / receiving input squared norm calculator, 20 …… Sending input end, 21 …… 1 sample Delay circuit,
22 …… Transmit input shift register, 23 …… Sum of product calculator,
24 …… Transfer function denominator coefficient save register, 25 …… Transfer function denominator coefficient register, 26 …… Adder, 27 …… Transfer function denominator coefficient correction register, 28 …… Adder, 29 …… Subtractor, 30 ... Power calculator, 31 ... Save register, 32 ...
… Saving register, 33 …… Power calculator, 34 …… Power calculator, 35 …… Transmission output terminal, 36 …… IIR type echo canceller disable switch, 37 …… Control circuit, 38 ……
Near end input detection signal input end by FIR type echo canceller. In Fig. 3: 41 ... reception input end, 42 ... reception input shift register,
43 …… Sum of products calculator, 44 …… Sending input terminal, 45 …… Subtractor,
46 …… Estimated impulse save register, 47 …… Estimated impulse register, 48 …… Adder, 49 …… Estimated impulse correction register, 50 …… Received input square norm calculator,
51 …… power calculator, 52 …… save register, 53 …… save register, 54 …… power calculator, 55 …… power calculator, 56 …… residual echo output terminal, 57 …… control circuit, 58 ......
Near end input detection signal output end.

Claims (1)

[Claims] 1. A first means for approximating an impulse response of an echo path by a discrete transfer function having poles and estimating its coefficient from a received input sequence and an echo sequence, and a transfer function estimated by the first means. A first echo canceller having a second means for generating a first residual echo by calculating a pseudo echo by a convolution operation with a received input sequence and an echo sequence and subtracting it from the echo, and the first echo A third means for estimating the impulse response of the echo path including the canceller from the received input sequence and the first residual echo;
The pseudo echo is calculated by the convolution operation of the estimated impulse response estimated by the third means and the received input sequence, and the first echo is calculated.
A second echo canceller having a fourth means for generating a second residual echo by subtracting the residual echo from the second echo canceller, the first echo canceller and the second echo canceller are connected in cascade, and at the time of start-up. When the characteristic of the echo path changes, the first echo canceller having a large convergence speed approximates and estimates the transfer function of the echo path, and the second echo canceller corrects the approximation and estimation error of the first echo canceller. An echo canceller device capable of canceling an echo by following a system having a large echo delay and a frequent echo path change.