JPH07121107B2 - High-definition television signal decoder circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a high-definition television system for demodulating a band-compressed high-definition television signal into a broadband high-definition television signal. The present invention relates to a television signal decoder circuit, and more particularly, to an improved means for obtaining a frozen image.

(Prior Art) As is well known, a wideband high-definition television signal is band-compressed to a practical level band for transmission, and is demodulated to a broadband original high-definition television signal on the receiving side. The high-definition television system, which has been adopted as described above, has been put into practical use. In this case, as a method for band-compressing a high-definition television signal, at present, a sub-sampling is performed on the high-definition television signal in a cycle of 4 fields.
The (Multiple Sub-Nyqist Sampling Encoding) system ("New transmission system for high-definition television-MUSE-", NHK Giken monthly report, Ninomiya, Vol. 27, No. 7, 1984) is generally used.

Here, FIG. 4 shows a conventional decoder circuit for demodulating a band-compressed high-definition television signal (hereinafter referred to as a MUSE signal) into an original broadband high-definition television signal. . That is, the MUSE signal supplied to the input terminal 11 is the A / D (analog / digital) conversion circuit 12
Is converted into digitized data having a data rate of 16 MHz (hereinafter referred to as MUSE data), and then supplied to the interframe interpolation circuit 13.

This interframe interpolating circuit 13 has a sub-sample switch 14 in which digitized data output from the A / D conversion circuit 12 is supplied to one fixed contact 14a, and a common contact 14c of the sub-sample switch 14 is input. A field memory 15 connected to an end and having a storage capacity capable of writing MUSE data for two fields, and a field memory 16 having a storage capacity capable of writing MUSE data for two fields read from the field memory 15 Composed,
The MUSE data read from the field memory 16 is supplied to the other fixed contact 14b of the sub sample switch 14.

The sub-sample switch 14 has an AND circuit 17
When the output of is at H level, it is switched to the fixed contact 14a side,
When the output of the AND circuit 17 is at L level, it is switched to the fixed contact 14b side. Here, the AND circuit 17 has one input terminal thereof connected to an input terminal 18 to which a sub-sampling information signal for sub-sampling phase control transmitted together with the MUSE signal is supplied, and the other input terminal thereof. , Is connected to the input terminal 19 to which a freeze signal is supplied which is H level in the normal image reproduction mode and which is L level in the mode in which the freeze image is requested.

Therefore, in the normal image reproduction mode, the sub-sampling switch 14 is controlled to be alternately switched based on the sub-sampling information signal, and the common contact 14c of the sub-sampling switch 14 controls the MUSE data whose data rate is increased to 32 MHz. Will be generated.

The output of the AND circuit 20 is supplied to the field memory 16. The AND circuit 20 has one input terminal connected to the input terminal 21 to which the motion vector signal transmitted together with the MUSE signal is supplied, and the other input terminal to which the freeze signal is supplied. Connected to 19.

Therefore, in the normal image reproduction mode, the field memory 16 operates so as to perform motion correction on the written MUSE data based on the motion vector signal supplied to the input terminal 21.

That is, the inter-frame interpolation circuit 13 uses the two field memories 15 and 16 to make a total of four fields of MUSE.
Data is sequentially interpolated, and the A / D conversion circuit 12
With respect to the MUSE data (current field signal) output from, the common contact 14c of the sub-sampling switch 14 provides a signal obtained by interpolating the current field signal and the signal two fields before the current frame, A signal obtained by interpolating a signal of one field before and a signal of three fields before is obtained from the memory 15, and a signal of two fields before and a signal of four fields before is interpolated from the field memory 16 between frames. Each signal is obtained.

Therefore, the sub-sample switch 14 is an AND circuit.
Output from field memory 16 by output of 17
This means that the operation is performed by exchanging the signal of four fields before the MUSE data and the signal of the current field.

Here, in the MUSE method, a fine image is reproduced by using all four fields of MUSE data in the still part of the image, while an image is reproduced by MUSE data of multiple fields in the moving part of the image. If this happens, multiple images will appear as if the images overlap, so in order to prevent this, the images are reproduced using only the MUSE data of the transmitted field, that is, the current field.

Then, it is the inter-field interpolation circuit 22 that reproduces the image corresponding to this stationary portion. The inter-field interpolating circuit 22 has a field memory inside, and the MUSE obtained from the common contact 14c of the sub-sample switch 14 is used.
A signal obtained by interpolating the signal of the current field and the signal two fields before that contained in the data is delayed by one field, and as a result, an inter-field interpolation signal corresponding to a still image is generated by MUSE data of four fields. Is generating.

On the other hand, it is the field interpolation circuit 23 that reproduces the image corresponding to the moving image portion. That is, the MUSE data obtained from the common contact 14c of the sub-sampling switch 14 is supplied to the sub-sampling circuit 24, and the signal component of the current field among the signal components of the current field and the signal component two fields before is supplied. Field interpolator after extracted
In-field interpolation processing is performed by 23, and an in-field interpolation signal corresponding to the moving image is generated.

Here, the MUSE data obtained from the common contact 14c of the sub-sample switch 14, the MUSE data read from the field memory 16, and the motion vector signal supplied to the input terminal 21 are supplied to the motion detection circuit 25. Has been done. In this case, generally, the motion detection is performed by taking the absolute value of the inter-frame difference signal on a pixel-by-pixel basis, but with the inter-frame offset sub-sampling structure like the MUSE signal, a simple one-frame difference can be obtained. Since it cannot be used, the difference between two frames having the same sub-sampling phase is used.

That is, the common contact 14c of the sub-sample switch 14
The MUSE data of the current field obtained from the above and the MUSE data of two fields before read from the field memory 16 are supplied to the subtraction circuit 26, and a difference signal between two frames which is a difference component thereof is calculated. Here, the current field MUSE obtained from the common contact 14c of the sub-sample switch 14
Both the data and the MUSE data two fields before read from the field memory 16 have a data rate of 32 MHz.
However, by taking the difference component in the subtraction circuit 26, the term one field before disappears and the data rate becomes 16 MHz.

The two-frame difference signal output from the subtraction circuit 26 is converted into an absolute value by the absolute value circuit 27, and the number of bits is reduced. After that, the absolute value circuit 27
Is directly supplied to one input end of the selection circuit 28, is delayed by one frame period by the frame memory 29, and is supplied to the other input end of the selection circuit 28. The data supplied to the frame memory 29 is motion-corrected based on the motion vector signal.

Here, the selection circuit 28 switches the output of the absolute value circuit 27 and the output of the frame memory alternately based on the sub-sample information signal supplied to the input terminal 30, and outputs the data rate. Generate a 32MHz signal.
After that, the data rate 32 output from the selection circuit 28
A signal of MHz is smoothed by a non-linear LPF (low pass filter) circuit 31, and a motion detection signal is generated here.

Then, the inter-field interpolation signal output from the inter-field interpolation circuit 22 and the intra-field interpolation signal output from the field interpolation circuit 23 are output from the motion detection circuit 25 by the mixing circuit 32. By mixing in a ratio based on the motion detection signal, a wideband high-definition television signal originally obtained at the output terminal 33 can be obtained.

By the way, in the case of obtaining a freeze image in the decoder circuit for a high-definition television signal having the above-mentioned configuration, the input terminal 19 is operated by the operation of requesting the freeze image.
The freeze signal supplied to is set to L level. Then,
First, since the output of the AND circuit 17 becomes L level, the sub sample switch 14 is set to the fixed contact 14b side.

Therefore, new MUSE data is not supplied to the interframe interpolation circuit 13, the MUSE data read from the field memory 16 is written to the field memory 15 via the sub-sampling switch 14, and the field memory 15 The cyclic operation of writing the MUSE data read from the field memory 16 in the field memory 16 is repeated for each field.

Further, since the output of the AND circuit 20 is also fixed to the L level, the motion vector signal is not supplied to the field memory 16, so that the motion correction process is stopped.

Then, in such a state, the inter-field interpolation circuit 22,
By operating the field interpolation circuit 23, the sub-sampling circuit, and the motion detection circuit 25 as described above, a high-definition television signal corresponding to a frozen image can be obtained from the mixing circuit 32. A means for obtaining such a freeze image is described in, for example, Japanese Utility Model Laid-Open No. 61-121083.

By the way, in the conventional means for obtaining a frozen image in the decoder circuit for a high-definition television signal as described above, all processed data is stored in the memory, and the frozen image is read by using the data read from the memory. Not obtained, the unprocessed MUSE data stored in the field memories 15 and 16 are subjected to still image processing and moving image processing by the inter-field interpolation circuit 22 and the field interpolation circuit 23, and a motion detection circuit. The freeze image is obtained only after performing a series of processes of performing the motion detection process by 25 and further mixing the still image component and the moving image component based on the motion detection signal.

Therefore, the inter-field interpolation circuit 22, the field interpolation circuit 23, the sub-sampling circuit 24, the motion detection circuit 25, etc. operate accurately not only during normal image reproduction but also in a state where a frozen image is requested. Is required.

However, the conventional motion detection circuit 25 reads new MUSE data output from the A / D conversion circuit 12 and the field memory 16 in the normal image reproduction mode.
By calculating the difference component from the MUSE data, the difference signal between the two frames is obtained to detect the motion.
A / D by sub sample switch 14 during image freeze
Since the supply of new MUSE data from the conversion circuit 12 is cut off, there arises a problem that a two-frame difference signal cannot be obtained and an accurate motion detection signal cannot be obtained.

For this reason, it becomes impossible to detect motion, and it becomes impossible to obtain a high-quality freeze image.

(Problems to be Solved by the Invention) As described above, in the conventional decoder circuit for a high-definition television signal, it is possible to obtain the difference signal between two frames from the motion detection circuit 25 in a state where a frozen image is requested. I can't
There is a problem that accurate motion detection becomes impossible and a high-quality freeze image cannot be obtained.

Therefore, the present invention has been made in consideration of the above circumstances, and generates an accurate motion detection signal in an image freeze state,
It is an object of the present invention to provide a very good high-definition television signal decoder circuit capable of improving the quality of a freeze image.

[Structure of the Invention] (Means for Solving the Problems) That is, the decoder circuit for a high-definition television signal according to the present invention has a new structure for the memory of the inter-frame interpolating circuit in a state where a frozen image is requested. Immediately before a freeze image is requested, the writing of a high-definition television signal is blocked, the motion compensation process is stopped, and the calculated difference signal between two frames is blocked from being written in the memory of the motion detection circuit. The motion detection signal is generated based on the contents stored in the memory.

(Operation) According to the above configuration, the motion detection signal is generated based on the contents stored in the memory of the motion detection circuit immediately before the freeze image is requested.
It is possible to generate an accurate motion detection signal in the image frozen state and improve the quality of the frozen image.

(Embodiment) Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, the same parts as those in FIG. 4 are shown with the same symbols and only different parts will be described here. That is, the freeze signal supplied to the input terminal 19 is delayed by one frame period by the delay circuit 34 and then supplied to one of the input terminals of the AND circuits 17 and 20, respectively. For this reason, a freeze image is requested, and the freeze signal is inverted from the H level to the L level, 1
After the frame period, the sub-sample switch 14 is fixed to the fixed contact 14b side, and the motion correction process by the field memory 16 is stopped.

The signal output from the absolute value circuit 27 of the motion detection circuit 25 is supplied to one input terminal of the selection circuit 35. The selection circuit 35 guides the output of the absolute value circuit 27 to the frame memory 29 when the freeze signal is at the H level, that is, in the normal image reproducing state, and the freeze signal is at the L level, that is, when the freeze image is requested. It operates to direct the output of circuit 36 to frame memory 29.

Further, the freeze signal and the motion vector signal respectively supplied to the input terminals 19 and 21 are ANDed in the AND circuit 37 and supplied to the frame memory 29. Therefore, the motion vector signal is supplied to the frame memory 29 only when the freeze signal is at the H level, and the freeze signal is at the H level.
The supply of the motion vector signal to the frame memory 29 is cut off at the level, that is, when the frozen image is reproduced.

Therefore, when the freeze image is requested and the freeze signal is inverted from the H level to the L level, the selection circuit 35 is immediately switched to select the output of the sub-sampling circuit 36 and the movement to the frame memory 29 is performed. The supply of the vector signal is cut off, and the freeze signal changes from H level to L level.
The timing is set so that the sub-sampling switch 14 is fixed to the fixed contact 14b side and the motion correction process by the field memory 16 is stopped with a delay of one frame period from the time when the level is inverted. .

The freeze signal supplied to the input terminal 19 is delayed by the delay circuit 38 for one frame period, and then the AND circuit 39
Is supplied to one of the input terminals. The other input terminal of the AND circuit 39 is connected to the input terminal 30 to which the sub-sample information signal is supplied, and the output terminal thereof is connected to the selection circuit 28.

Therefore, when the output of the delay circuit 38 is at the H level, the selection circuit 28 alternately selects the outputs of the absolute value circuit 27 and the frame memory 29 based on the sub-sampling information signal, as described above. When the output of the delay circuit 38 becomes L level, the selection circuit 28 selects only the output of the frame memory 29.

Then, the respective outputs of the selection circuit 28 and the nonlinear LPF circuit 31 are supplied to the selection circuit 40. This selection circuit 40 is
Nonlinear LPF circuit 3 when the output of the delay circuit 38 is at H level
The output of 1 is guided to the mixing circuit 32, and when the output of the delay circuit 38 is at the L level, the output of the selection circuit 28 is controlled to be guided to the mixing circuit 32.

The output of the non-linear LPF circuit 31 is supplied to the sub-sampling circuit 36. This subsample circuit 36
The data rate output from the nonlinear LPF circuit 31 is 32M.
By subsampling the Hz signal, it acts to convert to a 16MHz data rate.

According to the above-described configuration, first, in the normal image reproduction mode, since the freeze signal is at the H level, the subsample switch 14 is switched based on the subsample information signal, and the field memory 16 causes the motion vector to change. Motion correction processing is performed based on the signal, and stable interframe interpolation is performed.

Further, an accurate two-frame difference signal is obtained from the subtraction circuit 26, and the output of the absolute value circuit 27 is written in the frame memory 29 via the selection circuit 35. Then, the selection circuit 28 alternately selects and outputs each output of the absolute value circuit 27 and the frame memory 29 based on the sub-sample information signal, and outputs the nonlinear LPF.
The output of the circuit 31 is supplied to the mixing circuit 32 via the selection circuit 40.

Next, the operation when a freeze image is requested will be described. First, after the freeze signal is inverted to the L level by the operation of requesting the freeze image until one frame period elapses (immediately before the freeze), that is, the freeze signal is at the L level and the outputs of the delay circuits 34 and 38 are still at the L level. The operation during the level period will be described.

In this case, since the output of the delay circuit 34 is at the H level, the sub sample switch 14 is switching-controlled based on the sub sample information signal, and the field memory 16 stores the motion vector, as in the normal image reproduction mode. Motion correction processing is performed based on the signal. Further, since the output of the delay circuit 38 is also at the H level, the selection circuit 28, like the normal image reproduction mode, causes the selection circuit 28 to output the absolute value circuit 27 and the frame memory 29 based on the sub-sample information signal.
The output of the
The output of the LPF circuit 31 is selected.

On the other hand, the selection circuit 35 is controlled so as to supply the signal having a data rate of 16 MHz output from the sub-sampling circuit 36 to the frame memory 29. Also, the frame memory 29
, The supply of the motion vector signal is cut off, the stored data is read, and the output of the sub-sampling circuit 36 is written. As a result, the frame memory 29 stores the motion detection signal when the freeze image is requested, that is, immediately before the freeze image is obtained.

After the lapse of the period immediately before the freeze, the output of the delay circuit 34 becomes L level and the sub-sample switch 14 is fixed to the fixed contact 14b side and the motion correction process by the field memory 16 is performed in the next frame and thereafter. Is stopped and the MUSE data stored in the field memories 15 and 16 is circulated.

Also, the output of the delay circuit 38 becomes L level, and the selection circuit 28
Selects the motion detection signal written in the frame memory 29, and the selection circuit 40 is controlled so as to guide the output of the selection circuit 28 to the mixing circuit 32. Therefore, in the image freeze state, the motion detection circuit 25 outputs the motion detection signal generated at the required time point of the frozen image, that is, generated based on the accurate two-frame difference signal. Therefore, it becomes possible to obtain a high-quality freeze image.

Next, FIG. 2 shows another embodiment of the present invention. In FIG. 2, only the motion detection circuit is shown, and the MUSE data of the common contact 14c of the sub-sample switch 14 and the MUSE data read from the field memory 16 are supplied to the input terminals 41 and 42, respectively. . The output of the selection circuit 28 is supplied to one input end of the selection circuit 40, and the output of the nonlinear LPF circuit 31 is supplied to one input end of the selection circuit 40 via the output terminal 43.

Here, in the embodiment of FIG. 1, the output of the nonlinear LPF circuit 31 is supplied to the selection circuit 35 via the sub-sampling circuit 36, but in the embodiment of FIG. 2, the output of the absolute value circuit 27. And the output of the frame memory 29 are supplied to the maximum value circuit 44, and the larger one of the outputs is supplied to the selection circuit 35.

In this case, the operations in the normal image reproduction state and the frozen image reproduction state are the same as those shown in FIG.
The description thereof will be omitted, and the operation in the immediately preceding frame period from the inversion of the freeze signal to the L level by the operation of requesting the freeze image until the elapse of one frame period will be described.

That is, it is assumed that the motion of the image shown in FIGS. 3A to 3D has occurred over the four frames immediately before the freeze.
Then, the output signal of the absolute value circuit 27 and the signal read from the frame memory 29 immediately before freezing become as shown in FIGS. 3 (e) and (f), respectively, and the data rate of each signal is 16 MHz. There is.

The outputs of the absolute value circuit 27 and the frame memory 29 are alternately selected by the selection circuit 28 based on the sub-sampling information signal, so that the data rate as shown in FIG. 3 (g) is 32 MHz. Is converted to a signal. After that, the output signal of the selection circuit 28 is smoothed by the non-linear LPF circuit 31 as shown in FIG. 3 (h), and becomes a motion detection signal having a data rate of 32 MHz.

Here, in the embodiment shown in FIG. 1, the nonlinear LPF circuit 31
The signal shown in FIG. 3 (h) output by the sub-sampler 36 is supplied to the selection circuit 35 by the sub-sampling circuit 36 in the signal having the data rate of 16 MHz as shown in FIG. 3 (i).

By the way, the signals shown in FIG. 3 (i) supplied to the selection circuit 35 are, as is apparent from FIG. 3, (e) and (f).
It can be seen that it is substantially equal to the one in which the maximum value of the two signals shown in is selected. Therefore, in the embodiment shown in FIG. 2, the maximum value of each output of the absolute value circuit 27 and the frame memory 29 is taken and supplied to the selection circuit 35.
The same effect as that of the embodiment shown in the figure can be obtained.

The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[Effects of the Invention] Therefore, as described in detail above, according to the present invention, an extremely good high-definition television signal decoder capable of generating an accurate motion detection signal in an image frozen state and improving the quality of a frozen image can be achieved. A circuit can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a decoder circuit for high-definition television signals according to the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. Timing chart for explaining the operation of the embodiment, the fourth
FIG. 1 is a block diagram showing a conventional decoder circuit for high definition television signals. 11 ... input terminal, 12 ... A / D conversion circuit, 13 ... interframe interpolating circuit, 14 ... subsample switch, 15,16 ... field memory, 17 ... AND circuit, 18,19 ... input terminal, 20 ... AND circuit , 21… input terminal, 22… inter-field interpolation circuit,
23 ... Field interpolation circuit, 24 ... Sub-sample circuit, 25
… Motion detection circuit, 26… Subtraction circuit, 27… Absolute value circuit, 28…
Selection circuit, 29 ... Frame memory, 30 ... Input terminal, 31 ... Nonlinear LPF circuit, 32 ... Mixing circuit, 33 ... Output terminal, 34 ... Delay circuit, 35 ... Selection circuit, 36 ... Subsample circuit, 37 ... AND circuit, 38 ... Delay circuit, 39 ... AND circuit, 40 ... Selection circuit, 41, 42 ... Input terminal, 43 ... Output terminal, 44 ... Maximum value circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Izumi ▲ Yoshinori 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Broadcasting Technology Laboratory, Japan Broadcasting Corporation (72) Inventor Seiichi Koshi 1 Kinuta, Setagaya-ku, Tokyo Chome No. 10-11 Broadcasting Technology Institute, Japan Broadcasting Corporation (72) Inventor Takato Katagiri 8 Shinshinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa, Ltd. Home Appliances Research Laboratory, Toshiba Corporation Yokohama Works (72) Minor Fumio Minami Kanagawa 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Japan Stock company Toshiba Household Appliances Research Institute

Claims (1)

[Claims] 1. A high-definition television signal, which is band-compressed by one round of sub-sampling in a predetermined field and includes a motion vector signal for motion compensation and a sub-sample information signal for sub-sampling phase control, in the original wide band. A high-definition television signal is demodulated, and the band-compressed high-definition television signal for a predetermined field is stored and a first memory for performing motion correction based on the motion vector signal is provided for the predetermined field. Inter-frame interpolating means for inter-frame interpolating the high-definition television signal and the inter-field interpolating signal by performing field interpolating processing on the high-definition television signal output from this inter-frame interpolating means. The field interpolation means to be generated and the high-definition television output from the interframe interpolation means. Inter-field interpolation means for performing inter-field interpolation processing on the signal to generate inter-field interpolation signals, high-definition television signals written in the first memory of the inter-frame interpolation means, and the first memory Calculating means for calculating the difference component from the high-definition television signal read from the second memory and a second memory for writing the output of the calculating means and delaying the output for a predetermined period, and the output of the second memory and the calculating means. Motion detecting means for generating a motion detecting signal corresponding to a motion component of an image, comprising a selecting means for alternately selecting the output and the sub-sample information signal and a smoothing means for smoothing the output of the selecting means; A high-definition television signal provided with mixing means for mixing the intra-field interpolated signal and the inter-field interpolated signal at a ratio based on the output of the motion detecting means. In the decoder circuit, the first means for preventing the writing of a new high-definition television signal to the first memory in the state in which the freeze image is requested, and for stopping the motion correction, and the freeze image is requested. Second means for preventing writing of the output of the arithmetic means to the second memory in the state and generating the motion detection signal based on the contents stored in the second memory immediately before the request for a frozen image. A decoder circuit for a high-definition television signal, comprising: