JPH0712140B2 - Signal switching circuit - Google Patents

Description

The present invention relates to a signal switching circuit, and more particularly to a signal switching circuit that selectively extracts a timing signal from a system clock having a high frequency.

[Conventional technology]

A conventional signal switching circuit of this type is shown in FIG. The frequency divider circuit 9 divides the system clock CK to generate a timing decoder.
It has 10 inputs. The timing decoder 10 judges the output of the frequency dividing circuit 9 and outputs a switching request signal 101 and sets and stores the SR latch 11 at a predetermined switching timing. On the other hand, the selection circuit 13 using the AND-OR circuit outputs the system clock CK to the output OUT until the output 12 of the SR launch 11 becomes low level, but the SR latch 11 is set by the timing decoder 10 and its output is output. When 12 becomes low level, it is switched to the DC signal applied to the input terminal 14 (or the frequency dividing circuit 9 and the input terminal 14 may be connected so as to output a signal obtained by dividing the system clock), and the output OUT is output. To do.

RST is a reset terminal for inputting the reset signal of the circuit.

FIG. 4 is a timing chart showing the operation.
That is, when t ₁ is the switching timing in the figure, the switching request signal 101 is input by inputting the clock CK corresponding to the same timing.
Is generated, the SR latch 11 is set, and the signal from the output terminal OUT switches.

[Problems to be solved by the invention]

If there is no delay due to each element or wiring in principle, the signal switches at the switching timing t ₁ . However, such a delay is inevitable. That is,
As is well known to those skilled in the art, the frequency dividing circuit 9 is a cascade-connected N-stage flip-flop FF1 as shown in FIG.
~ FFN, and the timing decoder 10 detects the switching timing using a gate circuit (AND gate in the figure) that receives the outputs of the flip-flops FF1 to FFN in each stage. In the figure, the flip-flops FF1 to FFN are "1011 ...
The switch timing is t ₁ when it becomes 01 ". However, the output of each flip-flop FF changes after a change in the output of the preceding flip-flop, as shown in the timing chart of FIG. Therefore, as shown in the figure, the switching request signal 101 is generated with a delay.The output of the SR latch 11 is further delayed from the generation of the switching request signal 101. This delay is the system clock CK as shown in FIG. When the cycle is longer than half, an extra pulse is generated despite the switching timing, as indicated by 401. In addition, the duty ratio becomes bad.

Therefore, as shown in FIG. 5, it is conceivable to detect the timing t ₀ which is earlier than the switching timing t ₁ by one clock and to generate the switching request signal 101 at the same timing by incorporating the above delay. The structure of the timing decoder 10 for that purpose is as shown in FIG.
It suffices to detect that the output of 1 to FFN is "0011 ... 01". However, in this case, the switching request signal 101
With the occurrence of delayed and SR delay of change in the output of the latch 11, as shown in FIG. 5 as 402, the timing t ₀
The pulse from the output terminal OUT corresponding to is interrupted on the way. Therefore, the duty ratio of the pulse from the output terminal OUT changes, and the timing signal control also does not operate normally.

In order to prevent such extra pulses and interrupted pulses from occurring in the middle, the frequency of the clock CK must be lowered, and high-speed execution of signal processing is blocked accordingly. .

[Means for solving problems]

An object of the present invention is to provide a signal switching circuit that switches a clock signal and another signal at a predetermined timing without generating an extra pulse or a pulse with a changed duty ratio. A frequency divider circuit as an input, a timing decoder that determines a state one clock before the predetermined timing based on an output of the frequency divider circuit, and generates a switching request signal, one logic level of the clock signal, and the above A first SR latch set by a switching request signal, a second SR latch set by the other logic level of the clock signal and a set output of the first SR latch, and a second SR latch of the second SR latch. An output selection circuit for switching and outputting the clock signal and the other signal by set output is provided.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The configuration will be described with reference to the timing chart of FIG. Also in this embodiment, t ₁ is the switching timing.

Similar to the conventional example, the system clock CK is supplied to the frequency dividing circuit 1, and the timing decoder 2 monitors the timing based on the contents of the frequency dividing circuit 1. Then, the switching request signal 201 is output at the timing one clock before the timing t _{1 when} the switching is performed, that is, at the timing t ₀ .
The frequency dividing circuit 1 and the timing decoder 2 have the same configurations as those described with reference to FIGS. 6 to 8, and therefore their description will be omitted to avoid duplication.

The timing decoder 2 outputs the switching request signal 20 at the timing t _0.
Although 1 is generated, it occurs later as described above. This signal 201 is supplied to the AND gate 3 and at its output
SR latch 4 is set. In the present embodiment, as shown in FIG. 2, the signal 201 has a delay larger than the time corresponding to a half cycle of the system clock CK.
When 201 occurs, AND gate 3 has already received a high level clock at one of its inputs, and as a result, SR
The latch 4 is set in synchronization with the signal 201, and its output becomes low level.

On the other hand, when the signal 201 is generated with a delay smaller than the time corresponding to a half cycle of the clock CK, the high level of the signal 201 causes the AND gate 3 to open, and the clock CK
The SR latch 4 is set by the rising edge of the high level, and its output becomes the low level.

The gate 5 constitutes an OR gate because its output is low when its two inputs are low and its output is high when either of the two inputs is high. One input of such OR gate 5 is the second
As shown in the figure, since the low level output is received from the SR latch 4 within the period of timing t ₀ , the output becomes low level in synchronization with the falling of the clock CK to the low level, and the SR latch 6 is set. To do. That is, the SR latch 6 is timing
It is set in synchronism with the falling edge of the clock CK when shifting to t ₁ , and its Q output becomes high level.

The Q output of the SR latch 6 is input to the AND-OR circuit 7, and as a result, the output signal from the output terminal OUT is switched to the signal supplied to the input terminal 8 from the system clock CK at the timing t ₁ . No extra pulse or interrupted pulse is generated.

The signal at the input terminal 8 may be a signal obtained by dividing the system clock CK. Further, the reset signal RST resets the frequency dividing circuit 1 and the latches 4 and 6 before the signal selection operation.

〔The invention's effect〕

As described above, the frequency divider circuit, the timing decoder, and the first SR latch detect the timing one clock before the timing at which the signal should be switched, and store the state, and the stored contents and the transition to the timing to be switched. In response to, the second SR latch is set, and the set signal switches the clock signal to another signal. Therefore, signal switching is executed at a desired timing without generation of extra pulses or interrupted pulses, and the duty ratio of the output pulse does not deteriorate. Therefore, the frequency of the system clock can be increased, and high-speed signal processing can be executed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, FIG. 3 is a block diagram of a conventional example, and FIG. 4 shows the operation of FIG. 5 is a timing chart when the switching timing of FIG. 3 is changed, FIG. 6 is a block diagram showing the frequency dividing circuit and timing decoder of FIG. 3, and FIG.
6 is a timing chart of FIG. 6, and FIG. 8 is a circuit diagram showing another example of the timing decoder of FIG. 1 ... divider circuit, 2 ... timing decoder, 4,6 ... S
R latch, 3 …… AND gate, 5 …… OR gate, 7 …… AN
D-OR selection circuit, CK ... System clock, 8 ... Input terminal for other signals.

 ─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-50-29274 (JP, A) JP-A-51-44861 (JP, A) JP-A-58-80723 (JP, A) Actual development Sho-56- 167642 (JP, U)

Claims (1)

[Claims] 1. A signal switching circuit which receives a clock signal and another signal and switches between the clock signal and the other signal at a predetermined timing to output the same, and a frequency dividing circuit having the clock signal as an input and the frequency dividing circuit. It is set by a timing decoder that determines a state one clock before the predetermined timing based on the output of the circuit and generates a switching request signal, and one logic level of the clock signal and the switching request signal from the timing decoder. First
And a second SR latch set by the other logic level of the clock signal and the set output of the first SR latch, and the clock signal and the other by the set output of the second SR latch. And an output selection circuit for switching and outputting the signal.