JPH07122898B2 - Memory system - Google Patents

Description

The present invention relates to a method of constructing a memory system, and more particularly to a memory system suitable for writing data inside out when the memory system is used in a display device or the like. Concerning the construction method of.

[Conventional technology]

Conventionally, when writing a data pattern to a memory system, a method has been known in which the data pattern is written through a shifter 2 as shown in FIG. This is as described in JP-A-55-112644. According to this method, by setting the shift amount of the shifter 2 in the control unit 4 of FIG. 2 by a microprocessor or the like, data shifted by an arbitrary number of bits can be written in the memory at high speed. This is an effective method to reduce the load on the software such as the microprocessor that performs writing control and to shorten the processing time especially when writing characters and graphics to the memory system in the bitmap type display device. is there. However, in this method, no consideration was given to the writing of data patterns such as characters and figures with an image of inside out. For example, when such a memory system is applied to an image, character, or graphic display device, an image of inside out may be required to add an accent to the character or the like. In the conventional method, although the necessary portion of the image shifted by an arbitrary number of bits can be written in the memory 3 at high speed, when the above-mentioned inside-out pattern is required,
I had to rely on software processing.

[Problems to be solved by the invention]

Therefore, in the above-mentioned conventional technique, when writing the data pattern in which the bit position is turned over to the memory, the data pattern must be converted into the turned-over pattern by the microprocessor or the like, which increases the load of software and the like. However, there is a problem in that the processing time associated therewith also increases. It should be noted that, as described in Japanese Patent Laid-Open No. 61-9762, a technique for inverting data stored in a memory to obtain a mirror image, and Japanese Patent Laid-Open No. 59-174959 are described. As described above, it is possible to combine the technology of providing a circuit for inverting the array of data, but even if the conventional technology is simply combined, the graphic data is once stored in the memory and then the graphic data in the memory is inverted. The graphic data that has been subjected to these processes, such as shifting or shifting, can be divided into two and written into the memory in two steps, but graphic data for drawing an image including a reversed image and a non-reversed image. Cannot be written to memory at high speed.

An object of the present invention is to provide a memory system capable of writing data for drawing an image including a reversed image and a non-reversed image at an arbitrary bit position in a memory at high speed.

[Means for Solving the Problems]

To achieve the above object, the present invention transfers a memory connected to a microprocessor for processing data to store a plurality of bits of data and a plurality of bits of write data output from the microprocessor to the memory. In a memory system including a data bus, a bit position conversion unit that reverses a bit position of data transferred from the data bus to the memory, data converted by the bit position conversion unit, and converted by the bit position conversion unit First selection means for selecting any one of the previous data, shift means for shifting the data transferred from the data bus to the memory by an arbitrary number of bits, and the first selection means. Only the arbitrary bits of the data selected and shifted by the shift means are recorded. And a write control unit for permitting writing to the memory, wherein the bit position conversion unit, the first selection unit and the shift unit are connected in series with each other. .

[Action]

In FIG. 1, a data pattern to be written by inverting (mirror image) is applied to the bit position inverting circuit 1 through the data bus 100. Information indicating that the data pattern is to be turned over and written is previously set in the control unit 4 by a microprocessor or the like. As a result, the data pattern in which the bit position is reversed is output to the output bus 101 of the bit position reverse circuit 1 and applied to the shifter 2. By setting in advance a shift amount that specifies how many bits the data pattern to be written is written in the memory in the control unit 4 by a microprocessor or the like in advance, the output bus 102 of the shifter 2 can set the target bit position. The inverted data pattern shifted to is output, and this pattern is written in the memory 3.

When the data is not written inside out, information indicating that the data is not turned over is set in the control unit 4 by a microprocessor or the like, so that the data pattern applied by the data bus 100 is directly transmitted through the output bus 101 through the shifter 2.
Is shifted by and written in the memory 2.

In FIG. 3, the order of flipping the bit positions is shifter 2
Because it is after being shifted by
There is no essential difference. That is, the write data pattern applied from the data bus 100 is shifted by the shifter 2 by the shift amount set in the control unit 4, and applied to the bit position inverting circuit 1 via the output bus 105 of the shifter. If the pattern is to be flipped over and written, the pattern is flipped over by the bit position flipping circuit 1 according to the instruction of the control unit 4 and written into the memory 3 via the output bus 106. In the case of a pattern that does not need to be turned upside down, the data of the same pattern as the output bus 105 of the shifter 2 is output to the output bus 106 of the bit position flipping circuit 1 and written in the memory 3 according to the instruction of the control unit 4.

The write controller 5 is a part for writing only a necessary part of the data pattern given to the memory 3. That is, the output 107 from the write controller 5 is connected to the write control terminals of the memory element corresponding to each bit of one word (for example, one word of 8 bits or one word of 16 bits) forming the memory 3. .

〔Example〕

Hereinafter, a first embodiment of the present invention will be described with reference to FIG. 1 and FIGS. Here, the case where the data buses 100, 101 and 103 are 8 bits will be described as an example, but the data buses 100, 101
The bus width of 103 and 103 may be any number of bits as long as it is 2 bits or more. The bus widths of the data buses 100 and 101 input to and output from the bit position reverse circuit (bit position conversion means) 1 are the same, but the bus widths of the data buses 101 and 102 input to and output from the shifter (shift means) 2 are It does not necessarily have to have the same number of bits. (This means that the data buses 105 and 1 which are input to and output from the bit position inverting circuit 1 in FIG.
The same can be said for 06 and the data buses 100 and 105 which are input to and output from the shifter 2. ) FIG. 4 shows an example of a concrete means for realizing the bit position inverting circuit 1. In this example, since the data bus 100 has 8 bits, eight switch means (first selecting means) 10 to 17 are provided.
It is realized by. In the figure, the switch means 10 to 17 are switched to the a side as shown by the solid line, but this can be switched to the b side at the same time as the dotted line by the control line 103 from the control unit 4. In the figure, when the switch means 10 to 17 are switched to the side a, the data pattern is not turned over. Also, when the data pattern is switched to the b side, the data pattern is turned over.

FIG. 5 is turned over to the input data bit patterns b0 to b7 (patterns applied to the data bus 100; FIG. 7A) when the switching means 10 to 17 of FIG. 4 are switched to the b side. The data bit patterns b0 'to b7' (patterns output to the data bus 101; FIG. 7B) are shown. When the flipping is designated by the control line 103, the data pattern ~ shown in Fig. 5 (a) is changed to the data pattern '~' shown in Fig. 5 (b) by the bit position flipping circuit 1. To be converted. The converted data pattern is given to the shifter 2 as described above.

The shifter 2 can be constructed by various methods. For example, it can be realized by a combination of a shift register and switch means, but the realizing means is not particularly limited. However, here, as an example, a shifter 2 having a combination of switch circuits as shown in FIG. 6 is shown. The control line 104 from the control unit 4 switches the internal switching means, and the data bus 1
The data pattern from 01 is shifted and output to the output bus 102.

The above will be collectively described with reference to FIG. 7 until the reverse pattern is written in the memory 3. Incidentally, here, FIG. 5 (a)
It is assumed that the pattern of the arrow pointing to the right shown in FIG. 2 is turned over (left-right inversion), right-shifted by 4 bits, and 4 bits (b4 to b7) from the right end are written in the memory 3. In FIG.
The pattern (a) given from the data bus 100 is converted into the flip pattern (b) by the bit position flip circuit 1 as described above and given to the shifter 2. The shifter 2 shifts the pattern of (b) as shown in (c) by an instruction from the control unit 4 (for example, by switching the switch in the shifter using the switch means as shown in FIG. 6). Next, the content (e) of the output 107 from the write control unit (write control means) 5 writes the content of the output bus 102 of the shifter 3 only to the bit of the memory 3 corresponding to the shaded portion of (e), and eventually Only the beginning portion of the leftward arrow as shown in FIG.

As described above, the conversion from the pattern (a) to the pattern (b), which has been conventionally performed by software processing such as a microprocessor to write the inside-out pattern in the memory 3, can be easily performed by the bit-position inside-out circuit. The first effect is that the load on the software can be reduced.

Further, as can be seen by comparing the example of the bit position inverting circuit 1 of FIG. 4 with the example of the shifter 2 of FIG. 6, the bit position inverting circuit 1 can be realized by adding a small amount of hardware as compared with the shifter 2. Particularly, in this embodiment, the bit position inverting circuit 1 and the shifter 2 are realized by the switch means. In such a case, the bit position inverting circuit can always be realized by the switch means of one stage, while the shifter 2 has the bus width of As the number of switches increases, the number of switch stages also increases. Therefore, when the bus width is large, there is a second effect that the cost increase ratio due to the addition of the bit position inverting circuit 1 (for example, 16-bit or 32-bit width) can be suppressed. This is an effect peculiar to the case where the switch means is used.

Although the switch means has been described above, it goes without saying that this includes, for example, a data selector circuit realized by the logic circuit shown in FIG.

Next, another embodiment of the present invention will be described with reference to FIG. 9th
In the configuration shown in FIG. 1, a register 6 for temporarily storing read data from the memory 3, a bus switch (second bus) for switching the data line 109 and the data bus 100 from the register (temporary storage means) 6 are provided. Selection means 7) is added. In the present embodiment, there is an effect that the data pattern already written in the memory 3 can be rewritten in an arbitrary position in the memory 3 with the image of the inside out. Now, it is assumed that the pattern 300 has been written in advance in the memory 3 as shown in FIG. This pattern 300 can be read word by word from the memory 3 into the register 6 by the data bus 108 from the memory 3. The read data is given to the bit position inverting circuit 1 by switching the bus switch 7, and after that, it can be written in the memory 3 again by the same procedure as described in the above embodiment. As a result, an upside-down (mirror image) pattern of the original pattern 300 can be written in the memory 3, such as the pattern 301 in FIG. 10 (b).

Next, a third embodiment will be described with reference to FIG. FIG. 11 shows an example in which the present invention is applied to a color or monochrome multi-tone graphic display. In general, such a display has a plurality of memories 3 in order to obtain colors or multiple gradations. Here, each memory 3 will be referred to as a "plane 200". In FIG. 11, n planes 200 are provided. The number of n may be any number as long as it is 1 or more. The inside of the plane 200 is the same as that of the embodiment described with reference to FIG. 9 here. According to this embodiment, the effects described in the first and second embodiments can be obtained at once for the memories 3 of the plurality of planes 200.

In other words, the larger the bus width of the data bus 100 and the larger the number of planes 200, the larger the amount of data that can be flipped over at one time, which reduces the load on the software for processing. Processing time is also reduced.

As described above with reference to the three embodiments, it is obvious that the present invention is a memory system which can be applied to a wide range of applications such as a graphic display, a buffer memory for a printer and a memory for processing image data. The embodiment shown in FIGS. 9 and 11 has been described with reference to the basic structure shown in FIG. 1, but the structure shown in FIG. 3 is shown in FIGS.
It goes without saying that this may be applied to the illustrated embodiment.

〔The invention's effect〕

According to the present invention, the bit position of specific data in the data transferred from the microprocessor is inverted or shifted, and then each data is directly stored in the memory. Data for drawing an image including the image can be written in the memory at high speed.

[Brief description of drawings]

1 and 3 are basic configuration diagrams of the present invention, FIG. 2 is a diagram for explaining a conventional example, and FIG. 4 is a bit position inverting circuit 1
FIG. 5 is a diagram showing an example of the configuration of the pattern inside out, FIG. 5 is a diagram showing an example of the configuration of the shifter 2, FIG. 7 is an illustration of writing the inside out pattern, and FIG. FIG. 9, FIG. 9 and FIG. 11 are views showing one configuration example, and FIG. 10 is an explanatory view thereof showing an embodiment of the present invention. 1 ... Bit position reverse circuit, 2 ... Shifter, 3 ... Memory, 4 ... Control unit, 5 ... Write control unit.

Claims (4)

[Claims] 1. A memory comprising: a memory connected to a microprocessor for processing data to store a plurality of bits of data; and a data bus for transferring a plurality of bits of write data output from the microprocessor to the memory. In the system, any one of a bit position conversion unit that reverses a bit position of data transferred from the data bus to the memory, data converted by the bit position conversion unit, and data before conversion by the bit position conversion unit First selecting means for selecting one of the data, shift means for shifting the data transferred from the data bus to the memory by an arbitrary number of bits, and the shift means selected by the first selecting means. Allows writing to the memory of any bit of the data shifted by And a write control unit, wherein the bit position conversion unit, the first selection unit and the shift unit are connected in series with each other. 2. The memory system according to claim 1, wherein the bit position conversion means and the first selection means are provided between the data bus and the shift means. 3. A temporary storage unit for temporarily storing data read from the memory, and a second unit for selecting one of the data stored in the temporary storage unit and the data on the data bus. 3. The memory system according to claim 2, further comprising: selecting means, wherein the data selected by the second selecting means is input to the bit position converting means. 4. A memory system comprising a plurality of sets of the memory system according to claim 3.